CN214069805U - Front-end protection device for switching power supply - Google Patents
Front-end protection device for switching power supply Download PDFInfo
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- CN214069805U CN214069805U CN202023201587.2U CN202023201587U CN214069805U CN 214069805 U CN214069805 U CN 214069805U CN 202023201587 U CN202023201587 U CN 202023201587U CN 214069805 U CN214069805 U CN 214069805U
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Abstract
The utility model provides a front end protection device for a switching power supply, which comprises a preceding stage switching circuit and a preceding stage slow starting circuit; the pre-stage switch circuit comprises a resistor R7, a PMOS tube M1 and a detection control circuit for detecting undervoltage or overvoltage of input voltage; the source electrode of the PMOS tube M1 is connected with one end of a resistor R7, and the other end of the resistor R7 is used as the input end of a preceding stage switch circuit; the preceding stage slow starting circuit comprises an NMOS (N-channel metal oxide semiconductor) tube M2, a first buffer circuit and a second buffer circuit; the input end of the first buffer circuit is connected to the drain electrode of the NMOS transistor M2, and the control end of the first buffer circuit is connected to the grid electrode of the NMOS transistor M2; the direct current can be slowly loaded on the switching element and the inductive element of the switching power supply at the moment of electrifying the switching power supply, so that the impact on the switching element is avoided, and the undervoltage and overvoltage detection and the real-time protection of the input direct current can be carried out.
Description
Technical Field
The utility model relates to a switching power supply protection circuit especially relates to a front end protection device for switching power supply.
Background
In the process of switching the power supply from the first alternating current to the direct current, alternating currents such as commercial power and the like are generally rectified to form direct currents, and then conversion processing is performed, during the process, when a rectifying circuit is powered on and outputs, instantaneous currents are large and often cause impact on a subsequent switch control part in the switching power supply, on the other hand, due to the fact that inductive elements such as a transformer exist in the switching power supply, when the switching power supply is powered off, a primary winding of the transformer induces high voltage and cannot be rapidly discharged, and therefore the switching power supply is damaged due to the impact, and the switching power supply is poor in stability based on the two reasons.
Second, although the switching power supply has voltage and power regulation, the regulation is mainly realized by duty ratio regulation of a driving pulse signal of a switching device in the switching power supply, and good overvoltage or undervoltage protection cannot be realized.
Therefore, in order to solve the above technical problems, it is necessary to provide a new technical means.
SUMMERY OF THE UTILITY MODEL
In view of this, the utility model aims at providing a front end protection device for switching power supply can realize that the direct current slowly loads in switching power supply's on switching power supply and inductive element in the twinkling of an eye, thereby avoid strikeing switching element, prevent that inductive element from producing last high voltage, and can realize inductive element's induced-current when the outage is released fast, prevent that the high voltage from burning out inductive element, and can carry out undervoltage and overvoltage detection and carry out real-time protection to the input direct current, thereby effectively ensure the safety of rear end electric part, promote whole switching power supply's security.
The utility model provides a front end protection device for a switching power supply, which comprises a preceding stage switching circuit and a preceding stage slow starting circuit;
the pre-stage switch circuit comprises a resistor R7, a PMOS tube M1 and a detection control circuit for detecting undervoltage or overvoltage of input voltage;
the source electrode of the PMOS tube M1 is connected with one end of a resistor R7, and the other end of the resistor R7 is used as the input end of a preceding stage switch circuit; the detection input end of the detection control circuit is connected to one end of the resistor R7 serving as the input end of the preceding stage circuit, the control output end of the detection control circuit is connected to the grid electrode of the PMOS tube M1 and controls the PMOS tube M1 to be turned off when under-voltage or over-voltage occurs, and the drain electrode of the PMOS tube M1 serves as the output end of the preceding stage switch circuit;
the preceding stage slow starting circuit comprises an NMOS (N-channel metal oxide semiconductor) tube M2, a first buffer circuit and a second buffer circuit;
the input end of the first buffer circuit is connected to the drain electrode of the NMOS transistor M2, and the control end of the first buffer circuit is connected to the grid electrode of the NMOS transistor M2;
the input end of the second buffer circuit is connected to the drain electrode of the NMOS transistor M2, and the output end of the second buffer circuit is connected to the source electrode of the NMOS transistor M2; the drain of the NMOS transistor M2 is connected to the source of the PMOS transistor M1, and the source of the NMOS transistor M2 serves as the output terminal of the front-end protection device.
Further, the detection control circuit comprises a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a resistor R6, a resistor R8, a voltage regulator tube ZD1, a voltage regulator tube ZD2, a triode Q1 and a triode Q2;
one end of a resistor R1 is used as a first input end of the detection control circuit and connected with the input end of the preceding stage switch circuit, the other end of the resistor R1 is connected with the negative electrode of a voltage regulator tube ZD1, the positive electrode of the voltage regulator tube ZD1 is grounded through a resistor R2, the positive electrode of the voltage regulator tube ZD2 is connected with the base electrode of a triode Q2 through a resistor R3, the emitting electrode of a triode Q2 is grounded, and the collector electrode of a triode Q2 is connected with the base electrode of a triode Q1;
the negative electrode of the voltage regulator tube ZD2 is used as the second input end of the detection control circuit and is connected with the input end of the preceding stage switch circuit, the positive electrode of the voltage regulator tube ZD2 is grounded through a resistor R4, the positive electrode of the voltage regulator tube ZD2 is connected with the base electrode of a triode Q1 through a resistor R5, the emitter electrode of a triode Q1 is grounded, the collector electrode of the triode Q1 is connected with the source electrode of a PMOS tube M1 after being connected in series through a resistor R8 and a resistor R6, and the common connection point between the resistor R6 and the resistor R8 is used as the control output end of the detection control circuit and is connected with the grid electrode of the PMOS tube M1.
Further, the first buffer circuit comprises a resistor R10, a resistor R11, a resistor R12, a resistor R13 and a capacitor C1;
one end of the resistor R10 is used as the input end of the first buffer circuit and is connected to the drain electrode of the NMOS transistor M2, the other end of the resistor R10 is connected to one end of the resistor R11 through the capacitor C1, and the other end of the resistor R11 is grounded;
one end of the resistor R12 is connected to the gate of the NMOS transistor M2 as the first control end of the first buffer circuit, the other end of the resistor R4 is grounded through the resistor R13, and the common connection point between the resistor R12 and the resistor R13 is connected to the common connection point between the resistor R10 and the capacitor C1.
Further, the second buffer circuit comprises a resistor R9, a transistor Q5 and a capacitor C2;
one end of the resistor R9 is used as the input end of the second buffer circuit and is connected with the drain electrode of the NMOS tube M2, the other end of the resistor R9 is connected with the emitting electrode of the triode Q5, one end of the capacitor C2 is connected with the source electrode of the NMOS tube M2, the other end of the capacitor C2 is grounded, and the collector electrode of the triode Q5 is connected with the common connection point of the capacitor C2 and the NMOS tube M2;
the base of the transistor Q5 is connected to the common connection point between the capacitor C1 and the resistor R10; the transistor Q1 is a P-type transistor.
Further, the circuit also comprises a bleeder circuit, wherein the bleeder circuit comprises a resistor R14, a resistor R15, a resistor R17, a resistor R16, a triode Q4 and a triode Q3;
one end of the resistor R14 is used as a first control end of the bleeder circuit and is connected to the common connection point of the resistor R3 and the capacitor C1; the other end of the resistor R14 is connected to the base of the triode Q3, the base of the triode Q3 is connected with one end of the resistor R15, the other end of the resistor R15 is used as the second control end of the bleeder circuit and is connected to the common connection point between the capacitor C1 and the resistor R11, the emitter of the triode Q3 is used as the first input end of the bleeder circuit and is connected to the grid of the NMOS tube M2, and the collector of the triode Q3 is used as the first output end of the bleeder circuit and is grounded;
one end of the resistor R17 is connected to the source of the NMOS transistor M2, the other end of the resistor R17 is connected to the base of the triode Q4, the base of the triode Q4 is connected to one end of the resistor R16, the other end of the resistor R16 is connected to the common connection point between the capacitor C1 and the resistor R11 as the fourth control end of the bleeder circuit, the emitter of the triode Q4 is connected to the source of the NMOS transistor M2 as the second input end of the bleeder circuit, and the collector of the triode Q3 is grounded as the second output end of the bleeder circuit;
the transistor Q3 and the transistor Q4 are P-type transistors.
The utility model has the advantages that: through the utility model discloses, can realize direct current in the twinkling of an eye on switching power supply and slowly load in switching power supply's on-off element and perception component, thereby avoid strikeing switching element, prevent that perception component from producing the last electric high pressure, and can realize that the induced-current of perception component is released fast when the outage, prevent that high pressure from burning out perception component, and can carry out undervoltage and overvoltage detection and carry out real-time protection to the input direct current, thereby effectively ensure the safety of rear end consumer, promote whole switching power supply's security.
Drawings
The invention will be further described with reference to the following figures and examples:
fig. 1 is a schematic circuit diagram of the present invention.
Detailed Description
The invention is described in further detail below with reference to the drawings in the specification:
the utility model provides a front end protection device for a switching power supply, which comprises a preceding stage switching circuit and a preceding stage slow starting circuit;
the pre-stage switch circuit comprises a resistor R7, a PMOS tube M1 and a detection control circuit for detecting undervoltage or overvoltage of input voltage;
the source electrode of the PMOS tube M1 is connected with one end of a resistor R7, and the other end of the resistor R7 is used as the input end of a preceding stage switch circuit; the detection input end of the detection control circuit is connected to one end of the resistor R7 serving as the input end of the preceding stage circuit, the control output end of the detection control circuit is connected to the grid electrode of the PMOS tube M1 and controls the PMOS tube M1 to be turned off when under-voltage or over-voltage occurs, and the drain electrode of the PMOS tube M1 serves as the output end of the preceding stage switch circuit;
the preceding stage slow starting circuit comprises an NMOS (N-channel metal oxide semiconductor) tube M2, a first buffer circuit and a second buffer circuit;
the input end of the first buffer circuit is connected to the drain electrode of the NMOS transistor M2, and the control end of the first buffer circuit is connected to the grid electrode of the NMOS transistor M2;
the input end of the second buffer circuit is connected to the drain electrode of the NMOS transistor M2, and the output end of the second buffer circuit is connected to the source electrode of the NMOS transistor M2; the drain electrode of the NMOS tube M2 is connected to the source electrode of the PMOS tube M1, and the source electrode of the NMOS tube M2 is used as the output end of the front-end protection device.
In this embodiment, the detection control circuit includes a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a resistor R6, a resistor R8, a voltage regulator ZD1, a voltage regulator ZD2, a transistor Q1, and a transistor Q2;
one end of a resistor R1 is used as a first input end of the detection control circuit and connected with the input end of the preceding stage switch circuit, the other end of the resistor R1 is connected with the negative electrode of a voltage regulator tube ZD1, the positive electrode of the voltage regulator tube ZD1 is grounded through a resistor R2, the positive electrode of the voltage regulator tube ZD2 is connected with the base electrode of a triode Q2 through a resistor R3, the emitting electrode of a triode Q2 is grounded, and the collector electrode of a triode Q2 is connected with the base electrode of a triode Q1;
the negative electrode of the voltage regulator tube ZD2 is used as the second input end of the detection control circuit and is connected to the input end of the preceding stage switch circuit, the positive electrode of the voltage regulator tube ZD2 is grounded through a resistor R4, the positive electrode of the voltage regulator tube ZD2 is connected to the base electrode of a triode Q1 through a resistor R5, the emitter electrode of a triode Q1 is grounded, the collector electrode of the triode Q1 is connected to the source electrode of a PMOS tube M1 after being connected in series through a resistor R8 and a resistor R6, the common connection point between the resistor R6 and the resistor R8 is used as the control output end of the detection control circuit and is connected to the grid electrode of the PMOS tube M1, wherein the resistor R1, the voltage regulator tube ZD1, the resistor R2, the resistor R3 and the triode Q2 form an overvoltage detection circuit, and other devices form an undervoltage detection circuit and control the turn-off and turn-on of the PMOS tube M1.
The detection protection control principle is as follows:
when the working voltage is normal, namely no undervoltage or no overvoltage, at the moment, the voltage regulator tube ZD2 is conducted to provide a conducting voltage for the triode Q1, the triode Q1 is conducted, because the switching device is a P-type MOS tube, a reverse bias voltage is required to be applied between a grid electrode and a source electrode, the PMOS tube M1 is conducted, otherwise, the PMOS tube M1 is turned off, therefore, due to the conduction of the triode Q1, the voltage division control of a resistor R6 and a resistor R8, the PMOS tube M1 is reversely biased and conducted to supply power for the subsequent power, if undervoltage exists, the voltage regulator tube ZD2 is cut off, the triode Q1 is cut off, the point position between the source electrode and the grid electrode of the PMOS tube M1 is equal, the PMOS tube M1 is turned off to stop supplying power, undervoltage protection is realized, when the voltage is overvoltage, the voltage regulator tube 1 is conducted, so that the triode Q2 is conducted, the triode Q2 pulls down the base potential of the triode Q1, and the triode Q1 is cut off, at the ZD1, the PMOS transistor M1 is also turned off to stop supplying power, thereby realizing overvoltage protection.
Through above-mentioned structure, can realize undervoltage and overvoltage detection simultaneously and control PMOS pipe M1 and turn-off and realize undervoltage and overvoltage protection, promote switching power supply's safety in utilization to control circuit is simple, and is reliable and stable.
In this embodiment, the first buffer circuit includes a resistor R10, a resistor R11, a resistor R12, a resistor R13, and a capacitor C1;
one end of the resistor R10 is used as the input end of the first buffer circuit and is connected to the drain electrode of the NMOS transistor M2, the other end of the resistor R10 is connected to one end of the resistor R11 through the capacitor C1, and the other end of the resistor R11 is grounded;
one end of the resistor R12 is used as a first control end of the first buffer circuit and is connected to the grid of the NMOS transistor M2, the other end of the resistor R4 is grounded through a resistor R13, and a common connection point between the resistor R12 and the resistor R13 is connected to a common connection point of the resistor R10 and the capacitor C1; through the structure, the NMOS tube M2 can be slowly switched on in the power-on process, so that the buffer effect is achieved, and the principle is as follows:
when the power is supplied initially, the current charges the capacitor C1 through a loop among the resistor R10, the capacitor C1, the resistor R11 and the ground, the voltage of the capacitor C1 rises slowly, the M1 is turned on slowly along with the rise of the voltage of the capacitor C1, and the distributed capacitor between the grid and the source of the NMOS tube M2 is matched with the capacitor C1, so that good slow start is realized.
In this embodiment, the second buffer circuit includes a resistor R9, a transistor Q5, and a capacitor C2;
one end of the resistor R9 is used as the input end of the second buffer circuit and is connected with the drain electrode of the NMOS tube M2, the other end of the resistor R9 is connected with the emitting electrode of the triode Q5, one end of the capacitor C2 is connected with the source electrode of the NMOS tube M2, the other end of the capacitor C2 is grounded, and the collector electrode of the triode Q5 is connected with the common connection point of the capacitor C2 and the NMOS tube M2;
the base of the transistor Q5 is connected to the common connection point between the capacitor C1 and the resistor R10; wherein, the triode Q1 is a P-type triode; the capacitor C2 is used for absorbing spike voltage and performing certain filtering, however, the setting of the capacitor C2 will certainly affect the overall turn-on speed, and therefore, the capacitor C2 is charged in advance through the second buffer circuit, so that the turn-on time of the whole circuit depends on the parameters of the resistor R10, the resistor R11, the resistor R12 and the capacitor C1, therefore, after the NMOS transistor M2 is turned on, the capacitor C10 will not be affected by the delay of the capacitor C2, and by adjusting the parameters of the resistor R9 and the capacitor C2, when the voltage of the capacitor C1 reaches the NMOS transistor M1, the transistor Q1 is turned off, and the charging of the capacitor C2 is completed.
In this embodiment, the circuit further includes a bleeder circuit, where the bleeder circuit includes a resistor R14, a resistor R15, a resistor R17, a resistor R16, a transistor Q4, and a transistor Q3;
one end of the resistor R14 is used as a first control end of the bleeder circuit and is connected to the common connection point of the resistor R3 and the capacitor C1; the other end of the resistor R14 is connected to the base of the triode Q3, the base of the triode Q3 is connected with one end of the resistor R15, the other end of the resistor R15 is used as the second control end of the bleeder circuit and is connected to the common connection point between the capacitor C1 and the resistor R11, the emitter of the triode Q3 is used as the first input end of the bleeder circuit and is connected to the grid of the NMOS tube M2, and the collector of the triode Q3 is used as the first output end of the bleeder circuit and is grounded;
one end of the resistor R17 is connected to the source of the NMOS transistor M2, the other end of the resistor R17 is connected to the base of the triode Q4, the base of the triode Q4 is connected to one end of the resistor R16, the other end of the resistor R16 is connected to the common connection point between the capacitor C1 and the resistor R11 as the fourth control end of the bleeder circuit, the emitter of the triode Q4 is connected to the source of the NMOS transistor M2 as the second input end of the bleeder circuit, and the collector of the triode Q3 is grounded as the second output end of the bleeder circuit;
the transistor Q3 and the transistor Q4 are P-type transistors.
Wherein, through above-mentioned structure, can play good effect of bleeding to switching power supply, prevent induced-current impact, its principle is as follows:
in a switching power supply, a switching element (a MOS transistor, a triode, an IGBT, etc.) is used in cooperation with a transformer, a pulse control signal is input through the switching element to convert direct current into alternating current, and when power is off, the transformer generates induced high voltage, where: incidentally, the principle of sensing a high voltage:
taking an inductor as an example (a transformer is equivalent to two inductors coupled), if a current after the inductor is connected to a circuit is from left to right, when the inductor is initially electrified, the inductor has an effect of hindering the current from increasing (i.e., the inductor current cannot pass), then an induced current flows from right to left in the inductor, at this time, the transformer itself cannot be damaged, but a high voltage is generated at an input end of the inductor, and the high voltage reversely impacts a front-end circuit, so that the circuit is burnt; at the moment of power failure, an induced current is generated inside the inductor to prevent the current of the inductor from being reduced, so that a high voltage is generated at the right end of the inductor, and the high voltage can cause burning loss of the switching element and the transformer, therefore, a freewheeling diode is often connected in reverse to a primary winding of the transformer, and although the freewheeling diode protects a rear-end circuit, a reverse impact is formed on a rectifying circuit and the like to burn a front-end circuit.
Therefore, under the above structure, due to the effect of the current first buffer circuit, the induced electromotive force of the primary winding of the transformer during power-on can be greatly reduced, so as to form protection, and during normal power supply, the transistor Q3 and the transistor Q4 are cut off, and during power-off, by using the voltage non-transient property of the capacitor C1, the lower end of the capacitor C1 can be set to be in a negative pressure state, so as to rapidly turn on the transistor Q4 and the transistor Q3, on one hand, the grid capacitor of the NMOS transistor M2 is rapidly discharged, on the other hand, the induced current of the primary winding of the transformer is rapidly discharged, so as to form good protection.
Finally, although the present invention has been described in detail with reference to the preferred embodiments, it should be understood by those skilled in the art that the present invention can be modified or replaced by other means without departing from the spirit and scope of the present invention, which should be construed as limited only by the appended claims.
Claims (5)
1. A front end protection device for a switching power supply, characterized in that: the circuit comprises a preceding stage switch circuit and a preceding stage slow starting circuit;
the pre-stage switch circuit comprises a resistor R7, a PMOS tube M1 and a detection control circuit for detecting undervoltage or overvoltage of input voltage;
the source electrode of the PMOS tube M1 is connected with one end of a resistor R7, and the other end of the resistor R7 is used as the input end of a preceding stage switch circuit; the detection input end of the detection control circuit is connected to one end of the resistor R7 serving as the input end of the preceding stage circuit, the control output end of the detection control circuit is connected to the grid electrode of the PMOS tube M1 and controls the PMOS tube M1 to be turned off when under-voltage or over-voltage occurs, and the drain electrode of the PMOS tube M1 serves as the output end of the preceding stage switch circuit;
the preceding stage slow starting circuit comprises an NMOS (N-channel metal oxide semiconductor) tube M2, a first buffer circuit and a second buffer circuit;
the input end of the first buffer circuit is connected to the drain electrode of the NMOS transistor M2, and the control end of the first buffer circuit is connected to the grid electrode of the NMOS transistor M2;
the input end of the second buffer circuit is connected to the drain electrode of the NMOS transistor M2, and the output end of the second buffer circuit is connected to the source electrode of the NMOS transistor M2; the drain of the NMOS transistor M2 is connected to the source of the PMOS transistor M1, and the source of the NMOS transistor M2 serves as the output terminal of the front-end protection device.
2. The front-end protection device for a switching power supply according to claim 1, characterized in that: the detection control circuit comprises a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a resistor R6, a resistor R8, a voltage regulator tube ZD1, a voltage regulator tube ZD2, a triode Q1 and a triode Q2;
one end of a resistor R1 is used as a first input end of the detection control circuit and connected with the input end of the preceding stage switch circuit, the other end of the resistor R1 is connected with the negative electrode of a voltage regulator tube ZD1, the positive electrode of the voltage regulator tube ZD1 is grounded through a resistor R2, the positive electrode of the voltage regulator tube ZD2 is connected with the base electrode of a triode Q2 through a resistor R3, the emitting electrode of a triode Q2 is grounded, and the collector electrode of a triode Q2 is connected with the base electrode of a triode Q1;
the negative electrode of the voltage regulator tube ZD2 is used as the second input end of the detection control circuit and is connected with the input end of the preceding stage switch circuit, the positive electrode of the voltage regulator tube ZD2 is grounded through a resistor R4, the positive electrode of the voltage regulator tube ZD2 is connected with the base electrode of a triode Q1 through a resistor R5, the emitter electrode of a triode Q1 is grounded, the collector electrode of the triode Q1 is connected with the source electrode of a PMOS tube M1 after being connected in series through a resistor R8 and a resistor R6, and the common connection point between the resistor R6 and the resistor R8 is used as the control output end of the detection control circuit and is connected with the grid electrode of the PMOS tube M1.
3. The front-end protection device for a switching power supply according to claim 2, characterized in that: the first buffer circuit comprises a resistor R10, a resistor R11, a resistor R12, a resistor R13 and a capacitor C1;
one end of the resistor R10 is used as the input end of the first buffer circuit and is connected to the drain electrode of the NMOS transistor M2, the other end of the resistor R10 is connected to one end of the resistor R11 through the capacitor C1, and the other end of the resistor R11 is grounded;
one end of the resistor R12 is connected to the gate of the NMOS transistor M2 as the first control end of the first buffer circuit, the other end of the resistor R4 is grounded through the resistor R13, and the common connection point between the resistor R12 and the resistor R13 is connected to the common connection point between the resistor R10 and the capacitor C1.
4. The front-end protection device for a switching power supply according to claim 3, characterized in that: the second buffer circuit comprises a resistor R9, a triode Q5 and a capacitor C2;
one end of the resistor R9 is used as the input end of the second buffer circuit and is connected with the drain electrode of the NMOS tube M2, the other end of the resistor R9 is connected with the emitting electrode of the triode Q5, one end of the capacitor C2 is connected with the source electrode of the NMOS tube M2, the other end of the capacitor C2 is grounded, and the collector electrode of the triode Q5 is connected with the common connection point of the capacitor C2 and the NMOS tube M2;
the base of the transistor Q5 is connected to the common connection point between the capacitor C1 and the resistor R10; the transistor Q1 is a P-type transistor.
5. The front-end protection device for a switching power supply according to claim 3, characterized in that: the circuit further comprises a bleeder circuit, wherein the bleeder circuit comprises a resistor R14, a resistor R15, a resistor R17, a resistor R16, a triode Q4 and a triode Q3;
one end of the resistor R14 is used as a first control end of the bleeder circuit and is connected to the common connection point of the resistor R3 and the capacitor C1; the other end of the resistor R14 is connected to the base of the triode Q3, the base of the triode Q3 is connected with one end of the resistor R15, the other end of the resistor R15 is used as the second control end of the bleeder circuit and is connected to the common connection point between the capacitor C1 and the resistor R11, the emitter of the triode Q3 is used as the first input end of the bleeder circuit and is connected to the grid of the NMOS tube M2, and the collector of the triode Q3 is used as the first output end of the bleeder circuit and is grounded;
one end of the resistor R17 is connected to the source of the NMOS transistor M2, the other end of the resistor R17 is connected to the base of the triode Q4, the base of the triode Q4 is connected to one end of the resistor R16, the other end of the resistor R16 is connected to the common connection point between the capacitor C1 and the resistor R11 as the fourth control end of the bleeder circuit, the emitter of the triode Q4 is connected to the source of the NMOS transistor M2 as the second input end of the bleeder circuit, and the collector of the triode Q3 is grounded as the second output end of the bleeder circuit;
the transistor Q3 and the transistor Q4 are P-type transistors.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202023201587.2U CN214069805U (en) | 2020-12-24 | 2020-12-24 | Front-end protection device for switching power supply |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202023201587.2U CN214069805U (en) | 2020-12-24 | 2020-12-24 | Front-end protection device for switching power supply |
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| CN214069805U true CN214069805U (en) | 2021-08-27 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114069825A (en) * | 2021-10-28 | 2022-02-18 | 国家电网有限公司 | Multi-output power direct current system |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114069825A (en) * | 2021-10-28 | 2022-02-18 | 国家电网有限公司 | Multi-output power direct current system |
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