CN214045469U

CN214045469U - Anti-disturbance laser power supply circuit

Info

Publication number: CN214045469U
Application number: CN202022753098.1U
Authority: CN
Inventors: 赖阳明; 王海根; 赖炳初
Original assignee: Guangzhou Leadway Electronic Co ltd
Current assignee: Guangzhou Leadway Electronic Co ltd
Priority date: 2020-11-24
Filing date: 2020-11-24
Publication date: 2021-08-24
Anticipated expiration: 2030-11-24

Abstract

The utility model relates to an anti-disturbance laser power supply circuit, include and be used for the filtering rectification input unit to commercial power rectification filtering with the commercial power connection, the PFC major loop unit is coupled to the filtering rectification input unit, and PFC major loop unit electricity is connected with SB standby unit, and PFC major loop unit still electricity is connected with the voltage reduction unit, and SB standby unit electricity is connected with power output feedback voltage stabilization unit. This application has filtering rectification input unit mainly is filtering input alternating current electric wire netting and produces the interference, prevent to damage the power, also can filtering power itself produced the interference to the electric wire netting, become the alternating current through the rectification and provide the back level power supply, PFC major loop passes through signal control circuit and peripheral element and steps up the voltage after the rectification to the stable direct current voltage supply voltage reduction unit that the user needs the voltage value, voltage reduction unit steps down the high pressure, in order to obtain the effect with the stable output voltage value that the user needs.

Description

Anti-disturbance laser power supply circuit

Technical Field

The application relates to the field of power supplies, in particular to an anti-disturbance laser power supply circuit.

Background

The power supply is a power component of the computer, and the electric energy source of each component in the computer depends on the power supply, which is the most basic premise for ensuring the normal operation of computer hardware. Every accessory in the computer has certain power consumption, needs direct current with different voltage, and the main function of the power supply is to convert external alternating current into direct current meeting the requirements of the computer, and the function of the power supply is similar to that of an alternating current adapter used for connecting a small electric appliance with commercial power. The power supply of the PC is not used in the situation that the power supply of the PC requires a relatively fixed standard, unlike the situation that the adapter is only suitable for a specific container, and the work flow of the power supply is relatively complicated, so the quality of the power supply directly influences whether the computer can normally operate.

In view of the above-mentioned related technologies, the inventor believes that due to the discreteness of products of different power manufacturers, the quality of the power may be different, which may cause the situation that the motherboard cannot work when being collocated with a certain power, that is, the motherboard is incompatible with the power, and normal power supply of the power to the motor is affected.

SUMMERY OF THE UTILITY MODEL

For the stability of power output voltage, this application provides an anti-disturbance laser power supply circuit.

The application provides an anti-disturbance laser power supply circuit adopts following technical scheme:

the utility model provides an anti-disturbance laser power supply circuit, include with the commercial power connection and be used for the filter rectification input unit to commercial power rectification filtering, the PFC major loop unit that boosts the commercial power is coupled to the filter rectification input unit, PFC major loop unit electricity is connected with the SB standby unit that detects PFC major loop unit output voltage, PFC major loop unit still electricity is connected with the voltage reduction unit that is used for stepping down PFC major loop unit output voltage, SB standby unit electricity is connected with power output feedback voltage stabilization unit for the normal work of protection circuit.

By adopting the technical scheme, the filtering and rectifying input unit mainly filters and inputs an alternating current power grid to generate interference, the power supply is prevented from being damaged, the interference generated by the power supply per se to the power grid can be filtered, alternating current is converted into direct current through rectification to provide rear-stage power supply, a PFC main loop boosts rectified voltage to stable direct current voltage of a voltage value required by a user through a signal control circuit and a peripheral element to supply a voltage reduction unit, the voltage reduction unit reduces the voltage of the high voltage to obtain a stable output voltage value required by the user, a power output feedback voltage stabilization unit is used for protecting the normal work of a circuit, and an SB standby unit is used for realizing the under-voltage protection of the circuit.

Optionally, the filtering and rectifying input unit includes a common-mode inductor LF1, a second common-mode inductor LF2, a third common-mode inductor LF3, and a rectifier bridge BD1, a voltage dependent resistor VD1 is connected in series between two input ends of the common-mode inductor LF1, two input ends of the common-mode inductor LF1 are respectively connected with a first fuse F1 and a second fuse F2, a first resistor RX1 and a second resistor RX2 are sequentially connected in series between the first fuse F1 and the second fuse F2, and a first capacitor CX1 is connected between the first fuse F1 and the second fuse F2; two output ends of the common mode inductor LF1 are further connected in series with a first capacitor CY1, the first capacitor CY1 is connected in series with a second capacitor CY2, a connection node of the first capacitor CY1 and the second capacitor CY2 is grounded, a first thermistor TH1 is connected between an input end of the common mode inductor LF1 and the second fuse F2, a second capacitor CX2 is connected between two input ends of the second common mode inductor LF2, a fourth capacitor CX4 is connected in series between two output ends of the third common mode inductor LF3, a third capacitor CY3 and a fourth capacitor CY4 are connected between two output ends of the third common mode inductor LF3 in sequence, a connection node of the third capacitor CY 9 and the fourth capacitor CY4 is grounded, a fourth resistor RX4 and a third resistor RX3 are connected between two output ends of the third common mode inductor LF3 in sequence, a common mode inductor BD 6867 of the third common mode inductor LF3 is coupled to a common mode rectifier LF3, the negative electrode of the rectifier bridge BD1 is connected with the PFC main circuit unit, the positive electrode of the rectifier bridge BD1 is connected with the VAC terminal, and a first capacitor C1 is connected between the positive electrode and the negative electrode of the rectifier bridge BD 1; the negative pole of the rectifier bridge BD1 is connected with the VSB terminal through a forty-eighth resistor R48 and a ninety-fifth electrolytic capacitor C95, a forty-ninth resistor R49 is connected with the two ends of the forty-eighth resistor R48 in parallel, and a sixty-seventh resistor R67 is connected with the two ends of the forty-eighth resistor R48 in parallel.

Through adopting above-mentioned technical scheme, through the effect of three common mode inductance and other electronic components mutually supporting to be used for restraining the electromagnetic wave external radiation emission that the high-speed signal line produced, reduce the power at the during operation, to other electronic equipment's influence, first thermistor TH 1's resistance is directly proportional with the generating heat of circuit, and first thermistor TH1 plays the effect of protection circuit.

Optionally, the PFC main loop unit includes a first inductor L1 and a second inductor L2 connected in sequence, the first inductor L1 is connected to the VAC terminal, a seventeenth diode D17 is connected in series to the first inductor L1 in the forward direction, a cathode of the seventeenth diode D17 is connected to the VSB terminal, and one end of the second inductor L2 is connected to three diodes connected in parallel in the forward direction: cathodes of the second diode D2, the first diode D1 and the fifteenth diode D15, cathodes of the second diode D2, the first diode D1 and the fifteenth diode D15 are connected with each other, cathode connection nodes of the second diode D2, the first diode D1 and the fifteenth diode D15 are sequentially connected with a ninety-sixth electrolytic capacitor C96 and a seventh resistor R7, and one end of a seventh resistor R7 is connected with an anode connection node of the second inductor L2, the second diode D2, the first diode D1 and the fifteenth diode D15;

the seventh resistor R7 is respectively connected with a depletion type first mos tube Q1 and a depletion type second mos tube Q2, a thirty-sixth electrolytic capacitor C36 and a thirty-seventh electrolytic capacitor C37 are sequentially connected between the drain electrode and the source electrode of the depletion type first mos tube Q1, the thirty-seventh electrolytic capacitor C37 is grounded, the grid electrode of the depletion type first mos tube Q1 is grounded through a sixth resistor R6, the grid electrode of the depletion type first mos tube Q1 is connected with a PNP type seventh triode Q7, the collector electrode of the seventh triode Q7 is grounded, the base electrode of the seventh triode Q7 is connected with the base electrode of an NPN type fourth triode Q4, and the emitter electrode of the fourth triode Q4 is connected with the grid electrode of the depletion type first mos tube Q1 through a fifth resistor R5; the grid of the depletion type second mos tube Q2 is connected with the connection node of the collector of the fourth triode Q4 and the fifth resistor R5 through the third resistor R3, the source of the depletion type second mos tube Q2 is grounded, the drain of the depletion type second mos tube Q2 is connected with the second inductor L2, the grid of the depletion type second mos tube Q2 is connected with the PNP type sixth triode Q6, the collector of the sixth triode Q6 is grounded, the base of the sixth triode Q6 is connected with the connection node of the base of the seventh triode Q7 and the base of the fourth triode Q4, the emitter of the sixth triode Q6 is connected with the fourth resistor R4, and the fourth resistor R4 is grounded;

a second capacitor C2 is connected to the forty-eighth resistor R48, one end of the second capacitor C2 is connected to the cathode connection nodes of the second diode D2, the first diode D1 and the fifteenth diode D15, the forty-eighth resistor R48 is connected to the forty-eighth electrolytic capacitor C40, the forty-eighth electrolytic capacitor C40 is connected to the VDC terminal, the cathode connection nodes of the second diode D2, the first diode D1 and the fifteenth diode D15 are connected to the step-down circuit through a fourth fuse F4, the cathode connection nodes of the second diode D2, the first diode D1 and the fifteenth diode D15 are grounded through a fourth capacitor C4, the cathode connection nodes of the second diode D2, the first diode D1 and the fifteenth diode D1 are grounded through a third capacitor C1, and the cathode connection nodes of the second diode D1, the first diode D1 and the fifteenth diode D1 are connected in parallel to a first fuse F1, a fifth fuse F5 is grounded through a twenty-fourth electrolytic capacitor C24, a fifth fuse F5 is grounded through a seventy-ninth capacitor C79, a fifth fuse F5 is grounded through an eighty-third electrolytic capacitor C83, a fifth fuse F5 is grounded through an eighty-fourth electrolytic capacitor C84, a fifth fuse F5 is grounded through an eighty-fifth electrolytic capacitor C85, and a fifth fuse F5 is connected with a VDC-1 terminal;

the cathode connection node of the second diode D2, the first diode D1 and the fifteenth diode D15 is connected with a third fuse F3, and the third fuse F3 is connected with a VDC-2 terminal; the third fuse F3 is grounded after passing through a seventy-sixth capacitor C76, the third fuse F3 is grounded after passing through an eighty-first electrolytic capacitor C81, the third fuse F3 is grounded after passing through an eighty-second electrolytic capacitor C82, and the third fuse F3 is grounded after passing through an eighty-second electrolytic capacitor C80.

Through adopting above-mentioned technical scheme, through the effect of mutually supporting between inductance, triode and the depletion type MOS pipe to the realization is stepped up the voltage of input, in order to reach the higher voltage of commercial power, so that supply with the voltage reduction unit.

Optionally, the voltage reduction unit includes a depletion type eleventh MOS transistor Q11 and a depletion type twelfth MOS transistor Q12, a drain of the depletion type eleventh MOS transistor Q11 is connected to the VDC port, a gate of the depletion type eleventh MOS transistor Q11 is connected to a MOSG1 pin of the PWM control chip through a tenth resistor R10, a seventh diode D7 is connected in parallel in a forward direction at two ends of the tenth resistor R1, an eleventh resistor R11 is connected in series between a gate and a source of the depletion type eleventh MOS transistor Q11, an eleventh resistor R11 and a source connection node of the depletion type eleventh MOS transistor Q11 are connected to a MOSs1 pin of the PWM control chip, a source of the depletion type eleventh MOS transistor Q11 is electrically connected to a drain of the depletion type twelfth MOS transistor Q12, a gate of the depletion type twelfth MOS transistor Q12 is connected to a MOSG2 pin of the PWM control chip through a twelfth resistor R12, a positive terminal of the twelfth resistor R12 is connected in parallel to a drain of the depletion type twelfth MOS transistor Q375, and a source of the depletion type twelfth MOS transistor Q13 is connected in series between the depletion type twelfth transistor Q57323, the source electrode of the depletion type twelfth MOS tube Q12 is connected with the GND1 pin of the PWM control chip after passing through the eighth electrolytic capacitor CY 8;

a fourth inductor L4 is connected to a connection node of a source of the depletion-type eleventh MOS transistor Q11 and a drain of the depletion-type twelfth MOS transistor Q12, one end of the second inductor L2 is connected with a fifth transformer T5, the fifth transformer T5 comprises a main coil and two secondary coils, a first terminal of the fifth transformer T5 is connected with the fourth inductor L4, a second terminal of the fifth transformer T5 is grounded through a fifth electrolytic capacitor C5, a second terminal of the fifth transformer T5 is sequentially connected with a sixth electrolytic capacitor C6 and a fourteenth resistor R14 in series and then connected with an OPP pin of the PWM control chip, and two ends of the fourteenth resistor R1 are connected with a fifteenth resistor R15 in parallel;

a fourth terminal and a fifth terminal of the fifth transformer T5 are connected with a GND1 pin of the PWM control chip and are electrically connected;

a fourth diode group D4 and a fifth diode group D5 are connected to a third terminal of the fifth transformer T5, the fourth diode group D4 and the fifth diode group D5 both comprise two diodes connected in parallel in the forward direction, the fourth diode group D4 and the fifth diode group D5 are connected in parallel in the forward direction, a cathode of the fourth diode group D4 is connected with a cathode of the fifth diode group D5, a connection node of a cathode of the fourth diode group D4 and a cathode of the fifth diode group D5 is electrically connected with a GND1 pin of the PWM control chip after passing through a nineteenth electrolytic capacitor C19, two ends of a nineteenth electrolytic capacitor C19 are connected in parallel with a twentieth electrolytic capacitor C20, and two ends of the twentieth electrolytic capacitor C20 are connected in parallel with a forty-fourth resistor R44;

a sixth diode group D6 and a third diode group D3 having the same structure as the fourth diode group D4 and the fifth diode group D5 are also connected to the sixth terminal of the fifth transformer T5, and the cathode of the sixth diode group D6 and the cathode of the third diode group D3 are connected to a connection node between the cathode of the fifth diode group D5 and the cathode of the fourth diode group D4;

a connection node of the cathode of the fifth diode group D5 and the cathode of the fourth diode group D4 is connected with a fourth inductor L4, the fourth inductor L4 is connected with a terminal of VOUT24V, one end of the fourth inductor L4 is connected with a GND1 terminal after sequentially passing through a twenty-first electrolytic capacitor C21 and a forty-sixth resistor R46, and two ends of the forty-sixth resistor R46 are respectively connected with a forty-fifth resistor R45 and a sixty-third resistor R63 in parallel; two ends of the twenty-first electrolytic capacitor C2 are connected with a twenty-eighth electrolytic capacitor C28 in parallel, the twenty-eighth electrolytic capacitor C28 is grounded, two ends of the twenty-first electrolytic capacitor C2 are connected with a forty-seventh resistor R47 in parallel, the forty-seventh resistor R47 is grounded, two ends of the twenty-first electrolytic capacitor C2 are connected with a twenty-second electrolytic capacitor C22 in parallel, the twenty-second electrolytic capacitor C22 is grounded, two ends of the twenty-first electrolytic capacitor C2 are connected with a twenty-fifth electrolytic capacitor C25 in parallel, and the twenty-fifth electrolytic capacitor C25 is grounded;

one end of the fourth inductor L4 connected through the one hundred thirty four resistor R134 is connected with an LED lamp group, and one anode end of the LED lamp group is connected with the GND2 port.

By adopting the technical scheme, the depletion type MOS tube is used as a switch to control the on-off between the voltage reduction unit and the PFC main loop unit, and the transformer reduces the voltage of the output voltage of the PFC main loop unit to obtain the voltage meeting the user requirement.

Optionally, the SB standby unit includes a third transformer T3, a first terminal of the third transformer T3 is connected to the VS3 port, a second terminal of the third transformer T3 is connected to the sixth pin of the FSL-126HR first chip IC1, a third terminal of the third transformer T3 is connected in series with a twelfth diode D10 in forward direction, the twelfth diode D10 is grounded through an eighth electrolytic capacitor C8, a cathode of the twelfth diode D10 is connected to an NPN-type ninth triode Q9, a base of the ninth triode Q9 is connected to the fourth zener diode DZ4 and grounded, a collector of the ninth triode Q9 is grounded through a twenty-third resistor R23, a collector of the ninth triode Q9 is grounded through a ninth electrolytic capacitor C9, an emitter of the thirteenth triode Q13 is grounded, a collector of the ninth triode Q9 is connected to the thirteenth triode Q24 through a twenty-fourth resistor R24 and a base of the thirteenth triode Q13 is grounded through a twenty-fourth resistor R27, a cathode of a twelfth diode D10 is connected with a receiving side of a third optocoupler IC3 after passing through a twenty-sixth resistor R26, an emitter of the third optocoupler IC3 is connected with a twenty-seventh resistor R27, a fourth terminal of a third transformer T3 is sequentially connected with a ninth diode D9, a twenty-fifth resistor R25 and a third voltage stabilizing diode ZD3 in series, an anode of the third voltage stabilizing diode ZD3 is grounded, and a fifth pin of the third transformer T3 is grounded after passing through a nineteenth resistor R19;

the SB standby unit further comprises a PNP type thirteenth polar tube Q10, the collector of the thirteenth polar tube Q10 is grounded through a twenty-seventh resistor R27, the collector of the thirteenth polar tube Q10 is grounded through a one hundred thirty three resistor R133, the collector of the thirteenth polar tube Q10 is electrically connected with a VCC2 terminal, a twenty-first resistor R21 is connected in series between the emitter and the base of the thirteenth polar tube Q10, the emitter of the thirteenth polar tube Q10 is electrically connected with a PNP type eighth polar tube Q8, the emitter of the eighth polar tube Q8 is electrically connected with the emitter of the ninth polar tube Q9, the base of the thirteenth polar tube Q10 is electrically connected with the receiving side of the seventh optocoupler IC7 through a twenty-second resistor, the emitter of the seventh optocoupler IC7 is grounded, the emitter of the thirteenth polar tube Q10 is grounded through a sixty eight resistor R68, and the emitter of the thirteenth polar tube Q10 is grounded through a twenty-first electrolytic capacitor C21;

a second terminal of the third transformer T3 is connected with a first chip IC1, a fifth pin of the first chip IC1 is sequentially connected in series with an eighteenth resistor R18 and a seventeenth resistor R17, the seventeenth resistor R17 is connected with the VSB port after passing through a first fuse FR1, eight pins of the first chip IC1 are connected in series with a thirteenth diode D13 in the forward direction, a cathode of the thirteenth diode D13 is connected in series with a sixteenth resistor R16, a sixteenth resistor R16 is connected with the first fuse FR1, and two ends of the sixteenth resistor R16 are connected in parallel with a seventh capacitor C7; a third pin of the first chip IC1 is connected with a receiving side of a second optical coupler IC2, an emitter of the second optical coupler IC2 is grounded, two ends of the second optical coupler IC2 are connected with a ninth voltage regulator tube ZD9 in parallel, two ends of the second optical coupler IC2 are connected with a twentieth resistor R20 in parallel, and two ends of the second optical coupler IC2 are connected with a twenty-second capacitor C22 in parallel;

an eleventh diode group D11 is connected in series with the sixth pin of the third transformer T3 in the forward direction, and the cathode of the eleventh diode group D11 is connected with 12 VSB; the cathode of the eleventh diode group D11 is grounded through a thirteenth electrolytic capacitor C13, and the cathode of the eleventh diode group D11 is grounded through a fourteenth electrolytic capacitor C14;

a twelfth diode D12 is connected in series in the forward direction at a seventh terminal of the third transformer T3, a sixteenth electrolytic capacitor C16 is connected between a cathode of the twelfth diode D12 and an eighth terminal of the third transformer T3, an eighth terminal of the third transformer T3 is grounded after passing through a fifth capacitor CY5, both ends of the sixteenth electrolytic capacitor C16 are connected in parallel with a thirty-eighth resistor R38, both ends of the thirty-eighth resistor R38 are connected in parallel with a thirty-sixth resistor R36, a cathode of the twelfth diode D12 is connected in series with a thirty-eleventh resistor R31, the thirty-eleventh resistor R31 is connected in series with the emitting side of the second opto-coupler IC2, a cathode of the second opto-coupler IC2 is connected in series in the reverse direction with a fourth zener diode IC4, an anode of the fourth zener diode IC4 is grounded, a cathode of the twelfth diode D12 is connected in series with a thirty-third resistor R33 and a thirty-fourth resistor R34, one end of the thirty-fourth diode 4, the other end of the thirty-fourth resistor R34 is grounded; a fifteenth capacitor C15 is connected in series between the cathode of the third optocoupler IC3 and the thirty-third resistor R33;

the cathode of the twelfth diode D12 is electrically connected to a sixth inductor L6, one end of the sixth inductor L6 is grounded after passing through a thirty-seventh resistor R37, one end of the sixth inductor L6 is connected to the receiving side of a third optocoupler C3 after passing through a twenty-eighth resistor R28, the cathode of the third optocoupler C3 is connected to an NPN-type fourteenth triode Q14, the emitter of the fourteenth triode Q14 is grounded, the base of the fourteenth triode Q14 is grounded after passing through a thirty-eighth resistor R30, the base of the fourteenth triode Q14 is connected to the twenty-ninth resistor R29, the rear end of a fifth voltage stabilizing diode ZD5 is connected with the terminal VOUT24V, one end of a sixth inductor L6 is grounded through a fifty-seventh resistor R57, one end of the sixth inductor L6 is grounded through a sixteenth resistor R60, one end of a sixth inductor L6 is grounded through a thirty-fourth capacitor C34, one end of the sixth inductor L6 is grounded through a thirty-fifth capacitor C35, and one end of the sixth inductor L6 is connected with the terminal 5 VSB.

Through adopting above-mentioned technical scheme, SB standby unit is used for implementing the output voltage value that detects the voltage reduction unit to when the voltage of the output of voltage reduction unit is less than the rated value, realize the undervoltage protection to the circuit.

Optionally, the PFC main circuit unit is electrically connected to a PFC small card control unit for detecting an output voltage of the voltage reduction unit.

By adopting the technical scheme, the PFC small card control unit provides driving signal control for the PFC main loop unit.

Optionally, the PFC smart card control unit includes a first chip 1IC1 of model CM6500, a first resistor 1R1 and a first electrolytic capacitor 1C1 are sequentially connected in series with a first pin of the first chip 1IC1, a seventh pin of the first chip 1IC1 is connected with the first electrolytic capacitor 1C1 through a seventeenth resistor 1R17, a seventh pin of the first chip 1IC1 is connected with a seventh electrolytic capacitor 1C7, a third electrolytic capacitor 1C3, a thirteenth resistor 1R13, a twelfth resistor 1R12 and an eleventh resistor 1R11 in series with a seventh pin of the first chip 1IC1, a sixth pin of the first chip 1IC1 is connected with the first electrolytic capacitor 1C1 through a nineteenth capacitor 1R19, a sixth pin of the first chip 1IC1 is connected with the third electrolytic capacitor 1C 24 through an eighteenth resistor 1R18, a fourth pin of the first chip 1IC 599 is connected with the fourth capacitor 599 through a fourth capacitor 591C 599, a fourth pin of the first chip 1IC1 is connected with a third electrolytic capacitor 1C3 through a fifteenth resistor 1R15, and a fourth pin of the first chip 1IC1 is connected with a third electrolytic capacitor 1C3 and a connection node of a thirteenth resistor 1R13 through a fourteenth resistor 1R 14; a third pin of the first chip 1IC1 is connected with a third electrolytic capacitor 1C3 through a first zener diode 1ZD1, a third pin of the first chip 1IC1 is connected with a third electrolytic capacitor 1C3 through a sixth electrolytic capacitor 1C6, and a third pin of the first chip 1IC1 is connected with connection nodes of a sixteenth resistor 1R16 and then a sixteenth resistor R67, a forty ninth resistor R49 and a forty eighth resistor R48; a second pin of the first chip 1IC1 is sequentially connected with a tenth resistor 1R10, a ninth resistor 1R9 and an eighth resistor 1R8, the eighth resistor 1R8 is connected with a VCA terminal, and a second pin of the first chip 1IC1 is connected with a third electrolytic capacitor 1C3 after passing through a fourteenth electrolytic capacitor C14;

a first pin of the first chip 1IC1 is connected with a second electrolytic capacitor 1C2 and a thirteenth electrolytic capacitor 1C13 in series, one end of the second electrolytic capacitor 1C2 is connected with the first electrolytic capacitor 1C1, and the thirteenth electrolytic capacitor 1C13 is connected with the third electrolytic capacitor 1C 3;

a fourteenth pin of the first chip 1IC1 is sequentially connected with a second resistor 1R2 and an eighth electrolytic capacitor 1C8 in series, an eighth electrolytic capacitor 1C8 is connected with a third electrolytic capacitor 1C3, a fourteenth pin of the first chip 1IC1 is connected with a ninth electrolytic capacitor 1C9, the other end of the ninth electrolytic capacitor 1C9 is connected with a connection node of the eighth electrolytic capacitor 1C8 and the third electrolytic capacitor 1C3, a thirteenth pin of the first chip 1IC1 is connected with the third electrolytic capacitor 1C3 through a twelfth electrolytic capacitor 1C12, a thirteenth pin of the first chip 1IC1 is connected with the third electrolytic capacitor 1C3 through a third resistor 1R3, a thirteenth pin of the first chip 1IC1 is sequentially connected with a twenty-second resistor 1R22, a twenty-first resistor 1R21, a twenty-first resistor 1R20 in series, and a twenty-first resistor VDC 20 is electrically connected with a VDC terminal; a twelfth pin of the first chip 1IC1 is electrically connected with an emission side of the second optical coupler 1IC2 through a fifth resistor 1R5, a cathode of the second optical coupler 1IC2 is electrically connected with a ninth pin of the first chip 1IC1, an eleventh pin of the first chip 1IC1 is connected with a VCC3 terminal, an eleventh pin of the first chip 1IC1 is connected with a third electrolytic capacitor 1C3 through an eleventh electrolytic capacitor 1C11, an eleventh pin of the first chip 1IC1 is connected with a collector of a fourth triode Q4, an eleventh pin of the first chip 1IC1 is connected with a ninth resistor R9, a tenth pin of the first chip 1IC1 is connected with a base of a fourth triode Q4 after passing through a fourth resistor 1R4, the fourth resistor 1R4 is connected with a base of a sixth triode Q6, and an eighth pin of the first chip 1IC 539 1 is connected with a third electrolytic capacitor 1C 3;

the ninth resistor R9 is connected with a PNP type eighth triode Q8, the base electrode of the eighth triode Q8 is connected with the collector electrode of the second optocoupler 1IC2 after passing through the eighth resistor R8, and the emitter electrode of the second optocoupler 1IC2 is grounded; the collector of the eighth transistor Q8 is connected to the terminal VCC1, the collector of the eighth transistor Q8 is connected to the terminal VCC1 of the PWM control chip, and the emitter of the thirteenth diode Q10 is connected to the emitter of the thirteenth diode Q10.

By adopting the technical scheme, the driving signal is provided for the PFC main loop unit through the matching of electronic components of all parts.

Optionally, a relay for controlling the on/off of the first thermistor TH1 is connected to both ends of the first thermistor TH 1.

Through adopting above-mentioned technical scheme, the relay mainly is the first thermistor TH1 of short circuit after the power starts, makes the normal operating loss of power minimum.

In summary, the present application includes at least one of the following beneficial technical effects:

1. the filtering and rectifying input unit is mainly used for filtering interference generated by an input alternating current power grid, preventing the power supply from being damaged, and also filtering interference generated by the power supply to the power grid, alternating current is rectified to be direct current to provide power for a later stage, a PFC (power factor correction) main loop boosts rectified voltage to stable direct current voltage with a voltage value required by a user through a signal control circuit and a peripheral element and supplies the stable direct current voltage to the voltage reduction unit, and the voltage reduction unit reduces the voltage of the high voltage to obtain a stable output voltage value required by the user;

the SB standby unit is used for detecting the output voltage value of the voltage reduction unit so as to realize the undervoltage protection of the circuit when the output voltage of the voltage reduction unit is lower than a rated value;

and 3, the PFC small card control unit provides driving signal control for the PFC main loop unit.

Drawings

FIG. 1 is a schematic diagram of an overall circuit structure according to an embodiment of the present application;

FIG. 2 is a schematic diagram illustrating a connection relationship between a smoothing and rectifying input unit and a relay according to an embodiment of the present application;

fig. 3 is a schematic diagram of an overall structure of a PFC main loop unit according to an embodiment of the present disclosure;

fig. 4 is a schematic diagram of an overall structure of a voltage reduction circuit according to an embodiment of the present application;

FIG. 5 is a schematic diagram of the overall structure of an SB standby unit in an embodiment of the present application;

fig. 6 is a schematic diagram of an overall structure of a PFC smart card control unit according to an embodiment of the present disclosure;

fig. 7 is a schematic diagram of an overall structure of a power output feedback voltage stabilization unit according to an embodiment of the present application.

Description of reference numerals: 1. a filtering rectification input unit; 2. a PFC main loop unit; 3. a voltage reduction unit; 4. an SB standby unit; 5. a PFC small card control unit; 6. a relay; 7. a power output feedback voltage stabilizing unit; 8. and a PWM chip control circuit.

Detailed Description

The present application is described in further detail below with reference to figures 1-7.

The embodiment of the application discloses an anti-disturbance laser power supply circuit. Referring to fig. 1, the anti-disturbance laser power circuit includes a filter rectification input unit 1 connected to a mains supply and used for rectifying and filtering the mains supply, a PFC main loop unit 2 for boosting the mains supply is coupled to the filter rectification input unit 1, the PFC main loop unit 2 is electrically connected to an SB standby unit for detecting an output voltage of the PFC main loop unit 2, the PFC main loop unit 2 is further electrically connected to a voltage reduction unit 3 for reducing the output voltage of the PFC main loop unit 2, and the SB standby unit 4 is electrically connected to a power output feedback voltage stabilization unit 7 for protecting normal operation of the circuit.

Referring to fig. 2, the filtering and rectifying input unit 1 includes a common-mode inductor LF1, a second common-mode inductor LF2, a third common-mode inductor LF3, and a rectifier bridge BD1, a voltage dependent resistor VD1 is connected in series between two input ends of the common-mode inductor LF1, a first fuse F1 and a second fuse F2 are respectively connected to two input ends of the common-mode inductor LF1, a first resistor RX1 and a second resistor RX2 are sequentially connected in series between the first fuse F1 and the second fuse F2, and a first capacitor CX1 is connected between the first fuse F1 and the second fuse F2; two output ends of the common mode inductor LF1 are further connected in series with a first capacitor CY1, the first capacitor CY1 is connected in series with a second capacitor CY2, a connection node of the first capacitor CY1 and the second capacitor CY2 is grounded, a first thermistor TH1 is connected between an input end of the common mode inductor LF1 and the second fuse F2, a second capacitor CX2 is connected between two input ends of the second common mode inductor LF2, a fourth capacitor CX4 is connected in series between two output ends of the third common mode inductor LF3, a third capacitor CY3 and a fourth capacitor CY4 are sequentially connected between two output ends of the third common mode inductor LF3, a connection node of the third capacitor CY3 and the fourth capacitor CY 695 2 is grounded, a fourth resistor RX4 and a third resistor RX3 are sequentially connected between two output ends of the third common mode inductor LF3, a third common mode inductor RX 868627 is coupled to an output end of the second common mode inductor CY 686 3, and a common mode rectifier bridge LF3 is coupled to an output end of the common mode inductor BD 36 2, the negative pole of the rectifier bridge BD1 is connected with the PFC main circuit unit 2, the positive pole of the rectifier bridge BD1 is connected with the VAC terminal, and a first capacitor C1 is connected between the positive pole and the negative pole of the rectifier bridge BD 1; the negative pole of the rectifier bridge BD1 is connected with the VSB terminal through a forty-eighth resistor R48 and a ninety-fifth electrolytic capacitor C95, a forty-ninth resistor R49 is connected with the two ends of the forty-eighth resistor R48 in parallel, and a sixty-seventh resistor R67 is connected with the two ends of the forty-eighth resistor R48 in parallel.

Referring to fig. 2, a relay 6 for controlling the on/off of the first thermistor TH1 is connected to both ends of the first thermistor TH 1.

Referring to fig. 3, the PFC main circuit unit 2 includes a first inductor L1 and a second inductor L2 connected in sequence, the first inductor L1 is connected to a VAC terminal, the first inductor L1 is connected in series in the forward direction to a seventeenth diode D17, the cathode of the seventeenth diode D17 is connected to a VSB terminal, one end of the second inductor L2 is connected to three diodes connected in parallel in the forward direction, the second diode D2, the first diode D1, and the fifteenth diode D15, the cathodes of the second diode D2, the first diode D1, and the fifteenth diode D15 are connected to each other, the cathode connection node of the second diode D2, the first diode D1, and the fifteenth diode D15 is connected in sequence to a ninety-sixth electrolytic capacitor C96 and a seventh resistor R7, and one end of a seventh resistor R7 is connected to the anode connection node of the second inductor L2 and the second diode D2, the first diode D1, and the fifteenth diode D15.

Referring to fig. 3, the seventh resistor R7 is connected to a depletion type first mos tube Q1 and a depletion type second mos tube Q2, a thirty-sixth electrolytic capacitor C36 and a thirty-seventh electrolytic capacitor C37 are sequentially connected between the drain and the source of the depletion type first mos tube Q1, the thirty-seventh electrolytic capacitor C37 is grounded, the gate of the depletion type first mos tube Q1 is grounded through the sixth resistor R6, the gate of the depletion type first mos tube Q1 is connected to a PNP type seventh triode Q7, the collector of the seventh triode Q7 is grounded, the base of the seventh triode Q7 is connected to the base of the NPN type fourth triode Q4, and the emitter of the fourth triode Q4 is connected to the gate of the depletion type first mos tube Q1 through the fifth resistor R5; the grid of the depletion type second mos tube Q2 is connected with the connection node of the collector of the fourth triode Q4 and the fifth resistor R5 through the third resistor R3, the source of the depletion type second mos tube Q2 is grounded, the drain of the depletion type second mos tube Q2 is connected with the second inductor L2, the grid of the depletion type second mos tube Q2 is connected with the PNP type sixth triode Q6, the collector of the sixth triode Q6 is grounded, the base of the sixth triode Q6 is connected with the connection node of the base of the seventh triode Q7 and the base of the fourth triode Q4, the emitter of the sixth triode Q6 is connected with the fourth resistor R4, and the fourth resistor R4 is grounded.

Referring to fig. 3, a second capacitor C2 is connected to the forty-eighth resistor R48, one end of the second capacitor C2 is connected to the cathode connection node of the second diode D2, the first diode D1 and the fifteenth diode D15, the forty-eighth resistor R48 is connected to the forty-eighth electrolytic capacitor C40, the forty-eighth electrolytic capacitor C40 is connected to the VDC terminal, the cathode connection nodes of the second diode D2, the first diode D1 and the fifteenth diode D15 are connected to the step-down circuit through the fourth fuse F4, the cathode connection nodes of the second diode D2, the first diode D1 and the fifteenth diode D15 are connected to the ground through the fourth capacitor C4, the cathode connection nodes of the second diode D2, the first diode D1 and the fifteenth diode D1 are connected to the ground through the third capacitor C1, and the cathode connection nodes of the first diode D1, the fifteenth diode D1 and the fifteenth diode D1 are connected to the cathode connection node 1 in parallel, the fifth fuse F5 is grounded through a twenty-fourth electrolytic capacitor C24, the fifth fuse F5 is grounded through a seventy-ninth capacitor C79, the fifth fuse F5 is grounded through an eighty-third electrolytic capacitor C83, the fifth fuse F5 is grounded through an eighty-fourth electrolytic capacitor C84, the fifth fuse F5 is grounded through an eighty-fifth electrolytic capacitor C85, and the fifth fuse F5 is connected with a VDC-1 terminal.

Referring to fig. 3, a cathode connection node of the second diode D2, the first diode D1, and the fifteenth diode D15 is connected with a third fuse F3, and the third fuse F3 is connected with a VDC-2 terminal; the third fuse F3 is grounded after passing through a seventy-sixth capacitor C76, the third fuse F3 is grounded after passing through an eighty-first electrolytic capacitor C81, the third fuse F3 is grounded after passing through an eighty-second electrolytic capacitor C82, and the third fuse F3 is grounded after passing through an eighty-second electrolytic capacitor C80.

Referring to fig. 4, the voltage dropping unit 3 includes a depletion type eleventh MOS transistor Q11 and a depletion type twelfth MOS transistor Q12, a drain of the depletion type eleventh MOS transistor Q11 is connected to the VDC port, a gate of the depletion type eleventh MOS transistor Q11 is connected to a MOSG1 pin of the PWM control chip through a tenth resistor R10, a seventh diode D7 is connected in parallel in a forward direction at both ends of the tenth resistor R1, an eleventh resistor R11 is connected in series between a gate and a source of the depletion type eleventh MOS transistor Q11, an eleventh resistor R11 is connected to a source connection node of the depletion type eleventh MOS transistor Q11 and a MOSSs 1 pin of the PWM control chip, a source of the depletion type eleventh MOS transistor Q11 is electrically connected to a drain of the depletion type twelfth MOS transistor Q84, a gate of the depletion type twelfth MOS transistor Q12 is connected to a MOSG2 pin of the PWM control chip through a twelfth resistor twelfth 12, a thirteenth diode Q375 is connected in parallel between both ends of the depletion type twelfth MOS transistor Q12, and an eighth diode Q5857324, the source of the depletion type twelfth MOS transistor Q12 is connected to the GND1 pin of the PWM control chip through the eighth electrolytic capacitor CY 8.

Referring to fig. 4, a fourth inductor L4 is connected to a connection node between a source of the depletion-type eleventh MOS transistor Q11 and a drain of the depletion-type twelfth MOS transistor Q12, one end of the second inductor L2 is connected to a fifth transformer T5, the fifth transformer T5 includes a primary coil and two secondary coils, a first terminal of a fifth transformer T5 is connected to the fourth inductor L4, a second terminal of the fifth transformer T5 is grounded through a fifth electrolytic capacitor C5, a second terminal of the fifth transformer T5 is connected in series to a sixth electrolytic capacitor C6 and a fourteenth resistor R14 in sequence and then connected to an OPP pin of the PWM control chip, and both ends of the fourteenth resistor R1 are connected in parallel to a fifteenth resistor R15.

Referring to fig. 4, the fourth and fifth terminals of the fifth transformer T5 are connected to the GND1 pin of the PWM control chip.

Referring to fig. 4, a fourth diode group D4 and a fifth diode group D5 are connected to a third terminal of a fifth transformer T5, each of the fourth diode group D4 and the fifth diode group D5 includes two diodes connected in parallel in a forward direction, a fourth diode group D4 and a fifth diode group D5 are connected in parallel in a forward direction, a cathode of the fourth diode group D4 and a cathode of the fifth diode group D5 are connected, a connection node of a cathode of the fourth diode group D4 and a cathode of the fifth diode group D5 is electrically connected to a GND1 pin of the PWM control chip through a nineteenth electrolytic capacitor C19, two ends of the nineteenth electrolytic capacitor C19 are connected in parallel to a twentieth electrolytic capacitor C20, and two ends of the twentieth electrolytic capacitor C20 are connected in parallel to a forty-fourth resistor R44.

Referring to fig. 4, a sixth diode group D6 and a third diode group D3, which have the same structure as the fourth diode group D4 and the fifth diode group D5, are also connected to the sixth terminal of the fifth transformer T5, and the cathode of the sixth diode group D6 and the cathode of the third diode group D3 are connected to a connection node between the cathode of the fifth diode group D5 and the cathode of the fourth diode group D4.

Referring to fig. 4, a connection node between the cathode of the fifth diode group D5 and the cathode of the fourth diode group D4 is connected to a fourth inductor L4, the fourth inductor L4 is connected to a terminal of VOUT24V, one end of the fourth inductor L4 is connected to a terminal of GND1 after passing through a twenty-first electrolytic capacitor C21 and a forty-sixth resistor R46 in sequence, and two ends of the forty-sixth resistor R46 are respectively connected in parallel to a forty-fifth resistor R45 and a sixty-third resistor R63; two ends of the twenty-first electrolytic capacitor C2 are connected with a twenty-eighth electrolytic capacitor C28 in parallel, the twenty-eighth electrolytic capacitor C28 is grounded, two ends of the twenty-first electrolytic capacitor C2 are connected with a forty-seventh resistor R47 in parallel, the forty-seventh resistor R47 is grounded, two ends of the twenty-first electrolytic capacitor C2 are connected with a twenty-second electrolytic capacitor C22 in parallel, the twenty-second electrolytic capacitor C22 is grounded, two ends of the twenty-first electrolytic capacitor C2 are connected with a twenty-fifth electrolytic capacitor C25 in parallel, and the twenty-fifth electrolytic capacitor C25 is grounded.

Referring to fig. 4, one end of the fourth inductor L4 connected through the one hundred thirty four resistor R134 is connected to an LED lamp set, and one anode end of the LED lamp set is connected to the GND2 port.

Referring to fig. 5, the SB standby unit 4 includes a third transformer T3, a first terminal of the third transformer T3 is connected to a VS3 port, a second terminal of the third transformer T3 is connected to a sixth pin of the FSL-126HR first chip IC1, a third terminal of the third transformer T3 is connected in series in the forward direction to a twelfth diode D10, the twelfth diode D10 is grounded through an eighth electrolytic capacitor C8, a cathode of the twelfth diode D10 is connected to a ninth NPN-type triode Q9, a base of the ninth triode Q9 is connected to the fourth zener diode DZ4 and grounded, a collector of the ninth triode Q9 is grounded through a twenty-third resistor R23, a collector of the ninth triode Q9 is grounded through a ninth electrolytic capacitor C9, an emitter of the thirteenth triode Q13 is grounded, a collector of the ninth triode Q9 is connected to the thirteenth Q6342 through a twenty-fourth resistor R24 and a collector of the thirteenth resistor Q5928 is grounded through a twenty-third resistor R599, the cathode of the twelfth diode D10 is connected with the receiving side of the third optocoupler IC3 after passing through the twenty-sixth resistor R26, the emitter of the third optocoupler IC3 is connected with the twenty-seventh resistor R27, the fourth terminal of the third transformer T3 is sequentially connected with a ninth diode D9, a twenty-fifth resistor R25 and a third zener diode ZD3 in series, the anode of the third zener diode ZD3 is grounded, and the fifth pin of the third transformer T3 is grounded after passing through the nineteenth resistor R19.

Referring to fig. 5, the SB standby unit 4 further includes a PNP-type thirteenth diode Q10, a collector of the thirteenth diode Q10 is grounded through a twenty-seventh resistor R27, a collector of the thirteenth diode Q10 is grounded through a one hundred thirty three resistor R133, a collector of the thirteenth diode Q10 is electrically connected to the VCC2 terminal, a twenty-first resistor R21 is connected in series between an emitter and a base of the thirteenth diode Q10, an emitter of the thirteenth diode Q10 is electrically connected to a PNP-type eighth transistor Q8, an emitter of the eighth transistor Q8 is electrically connected to an emitter of the ninth transistor Q9, a base of the thirteenth diode Q10 is electrically connected to a receiving side of the seventh opto-coupler IC7 through a twenty-second resistor, an emitter of the seventh opto-coupler IC7 is grounded, an emitter of the thirteenth diode Q10 is grounded through a sixty-eighth resistor R68, and an emitter of the thirteenth diode Q10 is grounded through a first electrolytic capacitor C21.

Referring to fig. 5, a first chip IC1 is connected to a second terminal of the third transformer T3, an eighteenth resistor R18 and a seventeenth resistor R17 are sequentially connected in series to a fifth pin of the first chip IC1, a seventeenth resistor R17 is connected to the VSB port after passing through a first fuse FR1, a thirteenth diode D13 is connected in series to an eight pin of the first chip IC1 in the forward direction, a sixteenth resistor R16 is connected in series to a cathode of the thirteenth diode D13, a sixteenth resistor R16 is connected to the first fuse FR1, and a seventh capacitor C7 is connected in parallel to two ends of the sixteenth resistor R16; a third pin of the first chip IC1 is connected with a receiving side of a second optical coupler IC2, an emitter of the second optical coupler IC2 is grounded, two ends of the second optical coupler IC2 are connected in parallel with a ninth voltage regulator tube ZD9, two ends of the second optical coupler IC2 are connected in parallel with a twentieth resistor R20, and two ends of the second optical coupler IC2 are connected in parallel with a twenty-second capacitor C22.

Referring to fig. 5, an eleventh diode group D11 is forward-connected in series to a sixth pin of the third transformer T3, and a cathode of the eleventh diode group D11 is connected to 12 VSB; the cathode of the eleventh diode group D11 is grounded through the thirteenth electrolytic capacitor C13, and the cathode of the eleventh diode group D11 is grounded through the fourteenth electrolytic capacitor C14.

Referring to fig. 5, a twelfth diode D12 is connected in series in the forward direction at the seventh terminal of the third transformer T3, a sixteenth electrolytic capacitor C16 is connected between the cathode of the twelfth diode D12 and the eighth terminal of the third transformer T3, the eighth terminal of the third transformer T3 is grounded after passing through a fifth capacitor CY5, a thirty eighth resistor R38 is connected in parallel at both ends of the sixteenth electrolytic capacitor C16, a thirty sixth resistor R36 is connected in parallel at both ends of the thirty eighth resistor R38, a thirty eleventh resistor R31 is connected to the cathode of the twelfth diode D12, a thirty eleventh resistor R31 is connected in series with the emission side of the second optical coupler IC2, a fourth zener diode IC4 is connected in series in the reverse direction at the cathode of the second optical coupler IC2, the anode of the fourth zener diode IC4 is grounded, a cathode of the twelfth diode D12 is connected in series with a thirty third resistor R33 and a thirty fourth resistor R34 in series in turn, and a thirty fourth zener diode R34 is connected in series with the cathode of the twelfth diode D4, the other end of the thirty-fourth resistor R34 is grounded; a fifteenth capacitor C15 is connected in series between the cathode of the third optocoupler IC3 and the thirty-third resistor R33.

Referring to fig. 5, a cathode of the twelfth diode D12 is electrically connected to a sixth inductor L6, one end of the sixth inductor L6 is grounded after passing through a thirty-seventh resistor R37, one end of the sixth inductor L6 is connected to a receiving side of a third optocoupler C3 after passing through a twenty-eighth resistor R28, a cathode of the third optocoupler C3 is connected to an NPN-type fourteenth triode Q14, an emitter of the fourteenth triode Q14 is grounded, a base of the fourteenth triode Q14 is grounded after passing through a thirty-eighth resistor R30, a base of the fourteenth triode Q14 is grounded through a twenty-ninth resistor R29, the rear end of a fifth voltage stabilizing diode ZD5 is connected with the terminal VOUT24V, one end of a sixth inductor L6 is grounded through a fifty-seventh resistor R57, one end of the sixth inductor L6 is grounded through a sixteenth resistor R60, one end of a sixth inductor L6 is grounded through a thirty-fourth capacitor C34, one end of the sixth inductor L6 is grounded through a thirty-fifth capacitor C35, and one end of the sixth inductor L6 is connected with the terminal 5 VSB.

Referring to fig. 6, the PFC main circuit unit 2 is electrically connected with a PFC small card control unit 5 for detecting the output voltage of the voltage reducing unit 3.

Referring to fig. 6, the PFC smart card control unit (5) includes a first chip 1IC1 of model CM6500, a first resistor 1R1 and a first electrolytic capacitor 1C1 are sequentially connected in series with a first pin of the first chip 1IC1, a seventh pin of the first chip 1IC1 is connected with a first electrolytic capacitor 1C1 through a seventeenth resistor 1R17, a seventh pin of the first chip 1IC1 is connected with a seventh electrolytic capacitor 1C7, a third electrolytic capacitor 1C3, a thirteenth resistor 1R13, a twelfth resistor 1R 6384 and an eleventh resistor 1R11 in series, an eleventh resistor 1R11 is connected with a VCA terminal, a sixth pin of the first chip 1IC1 is connected with a first electrolytic capacitor 1C1 through a nineteenth capacitor 1R19, a sixth pin of the first chip 1IC1 is connected with a third electrolytic capacitor 1C 24 through an eighteenth resistor 1R18, a fourth pin of the first electrolytic capacitor 591C 599 is connected with a fourth capacitor 591C 599, a fourth pin of the first chip 1IC1 is connected with a third electrolytic capacitor 1C3 through a fifteenth resistor 1R15, and a fourth pin of the first chip 1IC1 is connected with a third electrolytic capacitor 1C3 and a connection node of a thirteenth resistor 1R13 through a fourteenth resistor 1R 14; a third pin of the first chip 1IC1 is connected with a third electrolytic capacitor 1C3 through a first zener diode 1ZD1, a third pin of the first chip 1IC1 is connected with a third electrolytic capacitor 1C3 through a sixth electrolytic capacitor 1C6, and a third pin of the first chip 1IC1 is connected with connection nodes of a sixteenth resistor 1R16 and then a sixteenth resistor R67, a forty ninth resistor R49 and a forty eighth resistor R48; the second pin of the first chip 1IC1 is connected to a tenth resistor 1R10, a ninth resistor 1R9 and an eighth resistor 1R8 in sequence, the eighth resistor 1R8 is connected to the terminal of the VCA, and the second pin of the first chip 1IC1 is connected to a third electrolytic capacitor 1C3 through a fourteenth electrolytic capacitor C14.

Referring to fig. 6, a second electrolytic capacitor 1C2 and a thirteenth electrolytic capacitor 1C13 are connected in series to a first pin of the first chip 1IC1, one end of the second electrolytic capacitor 1C2 is connected to the first electrolytic capacitor 1C1, and the thirteenth electrolytic capacitor 1C13 is connected to the third electrolytic capacitor 1C 3.

Referring to fig. 6, a fourteenth pin of the first chip 1IC1 is sequentially connected in series with a second resistor 1R2 and an eighth electrolytic capacitor 1C8, the eighth electrolytic capacitor 1C8 is connected with a third electrolytic capacitor 1C3, a fourteenth pin of the first chip 1IC1 is connected with a ninth electrolytic capacitor 1C9, the other end of the ninth electrolytic capacitor 1C9 is connected with a connection node of the eighth electrolytic capacitor 1C8 and the third electrolytic capacitor 1C3, a thirteenth pin of the first chip 1IC1 is connected with the third electrolytic capacitor 1C3 through a twelfth electrolytic capacitor 1C12, a thirteenth pin of the first chip 1IC1 is connected with the third electrolytic capacitor 1C3 through the third resistor 1R3, and a thirteenth pin of the first chip 1IC1 is sequentially connected in series with a twenty-second resistor 1R22, a twenty-first resistor 1R21, a twenty-resistor 1R20, and a twentieth resistor 1R 20; the twelfth pin of the first chip 1IC1 is electrically connected to the emitting side of the second optocoupler 1IC2 through a fifth resistor 1R5, the cathode of the second optocoupler 1IC2 is electrically connected to the ninth pin of the first chip 1IC1, the eleventh pin of the first chip 1IC1 is connected to a VCC3 terminal, the eleventh pin of the first chip 1IC1 is connected to a third electrolytic capacitor 1C3 through an eleventh electrolytic capacitor 1C11, the eleventh pin of the first chip 1IC1 is connected to the collector of the fourth triode Q4, the eleventh pin of the first chip 1IC1 is connected to a ninth resistor R9, the tenth pin of the first chip 1IC1 is connected to the base of the fourth triode Q4 through a fourth resistor 1R4, the fourth resistor 1R4 is connected to the base of the sixth triode Q6, and the eighth pin of the first chip 1IC1 is connected to a third electrolytic capacitor 1C 3.

Referring to fig. 6, the ninth resistor R9 is connected to a PNP-type eighth triode Q8, the base of the eighth triode Q8 is connected to the collector of the second optocoupler 1IC2 via the eighth resistor R8, and the emitter of the second optocoupler 1IC2 is grounded; the collector of the eighth transistor Q8 is connected to the terminal VCC1, the collector of the eighth transistor Q8 is connected to the terminal VCC1 of the PWM control chip, and the emitter of the thirteenth diode Q10 is connected to the emitter of the thirteenth diode Q10.

Referring to fig. 7, the collector of the twenty-fifth triode Q25 is electrically connected to the power output feedback voltage stabilizing unit 7 for protecting the normal operation of the circuit.

Referring to fig. 7, the power output feedback voltage regulator unit 7 includes an eighth comparator IC8A and an eighth comparator IC8B, wherein a signal output terminal of the eighth comparator IC8B is connected with an eighteenth diode D18 in a forward direction, a cathode of the eighteenth diode D18 is connected with a base of a fourteenth transistor Q14, a signal output terminal of the eighth comparator IC8B is connected with a 5VSB terminal through a seventy-second resistor R72, an inverting input terminal of the eighth comparator IC8B is connected with a TMC terminal, a non-inverting input terminal of the eighth comparator IC8B is connected with a seventy resistor R70, an eighteenth capacitor C18, and a fifty-first resistor R51 in series in sequence and then electrically connected with a PS/ON terminal, and a non-inverting input terminal of the eighth comparator IC8B is connected with the 5VSB terminal through a seventy-first resistor R71.

Referring to fig. 7, a signal output terminal of the eighth comparator IC8A is connected to an NPN-type eighteenth transistor Q18, an emitter of the eighteenth transistor Q18 is connected to an eighteenth capacitor C18, a collector of the eighteenth transistor Q18 is connected to a transmitting side of the seventh optocoupler IC7, an anode of the seventh optocoupler IC7 is connected to the 5VSB terminal through a fifty-second resistor R52, a signal output terminal of the eighth comparator IC8A is connected to the 5VSB terminal through a fifty-third resistor R53, a signal output terminal of the eighth comparator IC8A is connected to the fifty-eighth capacitor C18 through a fifty-fourth resistor R54, a non-inverting input terminal of the eighth comparator IC8A is connected to the 5VSB terminal through a fifty-fifth resistor R55, a non-inverting input terminal of the eighth comparator IC8A is connected to the first resistor R51, and both ends of the eighteenth capacitor C18 are connected in parallel to a fifty-resistor R50.

The implementation principle of the disturbance-resistant laser power supply circuit in the embodiment of the application is as follows:

the filtering and rectifying input unit 1 mainly filters interference generated by an input alternating current power grid, prevents damage to a power supply, and also can filter interference generated by the power supply to the power grid, converts alternating current into direct current through rectification to provide power for a later stage, the PFC main loop unit 2 boosts rectified voltage to stable direct current voltage of a voltage value required by a user through a sixth triode Q6, a seventh triode Q7, a depletion type first MOS transistor Q1 and a depletion type second MOS transistor Q2 and supplies the stable direct current voltage to a fifth transformer T5 (in the embodiment, the commercial power is boosted to 380V for output), and the voltage reduction unit 3 reduces the high voltage to obtain output voltage values (24V and 5V in the embodiment) required by the user.

The depletion type eleventh MOS transistor Q11 and the depletion type twelfth MOS transistor Q12 function as switches to control the on/off of the circuit between the PFC main circuit unit 2 and the buck unit 3.

The above embodiments are preferred embodiments of the present application, and the protection scope of the present application is not limited by the above embodiments, so: all equivalent changes made according to the structure, shape and principle of the present application shall be covered by the protection scope of the present application.

Claims

1. An anti-disturbance laser power supply circuit is characterized in that: the power supply protection circuit comprises a filtering rectification input unit (1) connected with a mains supply and used for rectifying and filtering the mains supply, wherein a PFC main loop unit (2) for boosting the mains supply is coupled with the filtering rectification input unit (1), the PFC main loop unit (2) is electrically connected with an SB standby unit (4) for detecting the output voltage of the PFC main loop unit (2), the PFC main loop unit (2) is also electrically connected with a voltage reduction unit (3) for reducing the output voltage of the PFC main loop unit (2), and the SB standby unit (4) is electrically connected with a power output feedback voltage stabilization unit (7) for normal work of the protection circuit.

2. The disturbance-resistant laser power supply circuit according to claim 1, wherein: the filtering and rectifying input unit (1) comprises a common-mode inductor LF1, a second common-mode inductor LF2, a third common-mode inductor LF3 and a rectifying bridge BD1, wherein a voltage dependent resistor VD1 is connected in series between two input ends of the common-mode inductor LF1, a first fuse F1 and a second fuse F2 are respectively connected to two input ends of the common-mode inductor LF1, a first resistor RX1 and a second resistor RX2 are sequentially connected in series between the first fuse F1 and the second fuse F2, and a first capacitor CX1 is connected between the first fuse F1 and the second fuse F2; two output ends of the common mode inductor LF1 are further connected in series with a first capacitor CY1, the first capacitor CY1 is connected in series with a second capacitor CY2, a connection node of the first capacitor CY1 and the second capacitor CY2 is grounded, a first thermistor TH1 is connected between an input end of the common mode inductor LF1 and the second fuse F2, a second capacitor CX2 is connected between two input ends of the second common mode inductor LF2, a fourth capacitor CX4 is connected in series between two output ends of the third common mode inductor LF3, a third capacitor CY3 and a fourth capacitor CY4 are connected between two output ends of the third common mode inductor LF3 in sequence, a connection node of the third capacitor CY 9 and the fourth capacitor CY4 is grounded, a fourth resistor RX4 and a third resistor RX3 are connected between two output ends of the third common mode inductor LF3 in sequence, a common mode inductor BD 6867 of the third common mode inductor LF3 is coupled to a common mode rectifier LF3, the negative electrode of the rectifier bridge BD1 is connected with the PFC main loop unit (2), the positive electrode of the rectifier bridge BD1 is connected with a VAC terminal, and a first capacitor C1 is connected between the positive electrode and the negative electrode of the rectifier bridge BD 1; the negative pole of the rectifier bridge BD1 is connected with the VSB terminal through a forty-eighth resistor R48 and a ninety-fifth electrolytic capacitor C95, a forty-ninth resistor R49 is connected with the two ends of the forty-eighth resistor R48 in parallel, and a sixty-seventh resistor R67 is connected with the two ends of the forty-eighth resistor R48 in parallel.

3. The disturbance-resistant laser power supply circuit according to claim 2, wherein: the PFC main loop unit (2) comprises a first inductor L1 and a second inductor L2 which are sequentially connected, wherein the first inductor L1 is connected with a VAC end, a seventeenth diode D17 is connected in series with the first inductor L1 in the forward direction, the cathode of the seventeenth diode D17 is connected with a VSB terminal, and one end of a second inductor L2 is connected with three diodes which are connected in parallel in the forward direction: cathodes of the second diode D2, the first diode D1 and the fifteenth diode D15, cathodes of the second diode D2, the first diode D1 and the fifteenth diode D15 are connected with each other, cathode connection nodes of the second diode D2, the first diode D1 and the fifteenth diode D15 are sequentially connected with a ninety-sixth electrolytic capacitor C96 and a seventh resistor R7, and one end of a seventh resistor R7 is connected with an anode connection node of the second inductor L2, the second diode D2, the first diode D1 and the fifteenth diode D15;

4. The disturbance-resistant laser power supply circuit according to claim 3, wherein: the voltage reduction unit (3) comprises a depletion type eleventh MOS tube Q11 and a depletion type twelfth MOS tube Q12, the drain of the depletion type eleventh MOS tube Q11 is connected with a VDC port, the grid of the depletion type eleventh MOS tube Q11 is connected with a MOSG1 pin of the PWM control chip after passing through a tenth resistor R10, a seventh diode D7 is connected in parallel in the forward direction of the two ends of the tenth resistor R1, an eleventh resistor R11 is connected in series between the grid and the source of the depletion type eleventh MOS tube Q11, an eleventh resistor R11 and the source connecting node of the depletion type eleventh MOS tube Q11 are connected with a MOSS1 pin of the PWM control chip, the source of the depletion type eleventh MOS tube Q11 is electrically connected with the drain of the depletion type twelfth MOS tube Q12, the grid of the depletion type twelfth MOS tube Q12 is connected with a MOSG2 pin of the PWM control chip after passing through a twelfth resistor R12, a thirteenth diode Q585 is connected in series between the forward direction of the two ends of the depletion type eleventh MOS tube Q12 and the source of the depletion type twelfth MOS tube Q13, the source electrode of the depletion type twelfth MOS tube Q12 is connected with the GND1 pin of the PWM control chip after passing through the eighth electrolytic capacitor CY 8;

5. The disturbance-resistant laser power supply circuit according to claim 4, wherein: the SB standby unit (4) comprises a third transformer T3, a first terminal of the third transformer T3 is connected with a VS3 port, a second terminal of the third transformer T3 is connected with a sixth pin of a first chip IC1 with the model FSL-126HR, a third terminal of the third transformer T3 is connected with a twelfth tube D10 in series in the forward direction, a twelfth tube D10 is grounded after passing through an eighth electrolytic capacitor C8, the cathode of the twelfth tube D10 is connected with a ninth triode Q9 with the NPN type, the base of a ninth triode Q9 is connected with a fourth zener diode DZ4 and then grounded, the collector of the ninth triode Q9 is grounded after passing through a twenty-third resistor R23, the collector of the ninth triode Q9 is grounded after passing through a ninth electrolytic capacitor C9, the emitter of the thirteenth triode Q13 is grounded, the collector of the ninth triode Q9 is connected with the thirteenth tube Q24 through a twenty-fourth resistor R24 and the base of the thirteenth tube Q13 is grounded after passing through a twenty-fourth resistor R27, a cathode of a twelfth diode D10 is connected with a receiving side of a third optocoupler IC3 after passing through a twenty-sixth resistor R26, an emitter of the third optocoupler IC3 is connected with a twenty-seventh resistor R27, a fourth terminal of a third transformer T3 is sequentially connected with a ninth diode D9, a twenty-fifth resistor R25 and a third voltage stabilizing diode ZD3 in series, an anode of the third voltage stabilizing diode ZD3 is grounded, and a fifth pin of the third transformer T3 is grounded after passing through a nineteenth resistor R19;

the SB standby unit (4) further comprises a PNP type thirteenth polar tube Q10, the collector of the thirteenth polar tube Q10 is grounded through a twenty-seventh resistor R27, the collector of the thirteenth polar tube Q10 is grounded through a one hundred thirty three resistor R133, the collector of the thirteenth polar tube Q10 is electrically connected with a VCC2 terminal, a twenty-first resistor R21 is connected in series between the emitter and the base of the thirteenth polar tube Q10, the emitter of the thirteenth polar tube Q10 is electrically connected with a PNP type eighth polar tube Q8, the emitter of the eighth polar tube Q8 is electrically connected with the emitter of the ninth polar tube Q9, the base of the thirteenth polar tube Q10 is electrically connected with the receiving side of a seventh optical coupler IC7 through a twenty-second resistor, the emitter of the seventh optical coupler IC7 is grounded, the emitter of the thirteenth polar tube Q10 is grounded through a sixty-eighth resistor R68, and the emitter of the thirteenth polar tube Q10 is grounded through a twenty-first electrolytic capacitor C21;

6. The disturbance-resistant laser power supply circuit according to claim 5, wherein: the PFC main loop unit (2) is electrically connected with a PFC small card control unit (5) used for detecting the output voltage of the voltage reduction unit (3).

7. The disturbance-resistant laser power supply circuit according to claim 6, wherein: the PFC small card control unit (5) comprises a first chip 1IC1 with the model number CM6500, a first resistor 1R1 and a first electrolytic capacitor 1C1 are sequentially connected in series with a first pin of the first chip 1IC1, a seventh pin of the first chip 1IC1 is connected with the first electrolytic capacitor 1C1 through a seventeenth resistor 1R17, a seventh pin of the first chip 1IC1 is connected with a seventh electrolytic capacitor 1C7, a third electrolytic capacitor 1C3, a thirteenth resistor 1R13, a twelfth resistor 1R12 and an eleventh resistor 1R11 in series, the eleventh resistor 1R11 is connected with a VCA terminal, a sixth pin of the first chip 1IC1 is connected with the first electrolytic capacitor 1C1 through a nineteenth capacitor 1R19, a sixth pin of the first chip 1IC1 is connected with a third electrolytic capacitor 1C 6324 through an eighteenth resistor 631R 18, a fourth pin of the first chip 1IC 599 is connected with a fourth capacitor 591C 599, a fourth pin of the first chip 1IC1 is connected with a third electrolytic capacitor 1C3 through a fifteenth resistor 1R15, and a fourth pin of the first chip 1IC1 is connected with a third electrolytic capacitor 1C3 and a connection node of a thirteenth resistor 1R13 through a fourteenth resistor 1R 14; a third pin of the first chip 1IC1 is connected with a third electrolytic capacitor 1C3 through a first zener diode 1ZD1, a third pin of the first chip 1IC1 is connected with a third electrolytic capacitor 1C3 through a sixth electrolytic capacitor 1C6, and a third pin of the first chip 1IC1 is connected with connection nodes of a sixteenth resistor 1R16 and then a sixteenth resistor R67, a forty ninth resistor R49 and a forty eighth resistor R48; a second pin of the first chip 1IC1 is sequentially connected with a tenth resistor 1R10, a ninth resistor 1R9 and an eighth resistor 1R8, the eighth resistor 1R8 is connected with a VCA terminal, and a second pin of the first chip 1IC1 is connected with a third electrolytic capacitor 1C3 after passing through a fourteenth electrolytic capacitor C14;

8. The disturbance-resistant laser power supply circuit according to claim 2, wherein: two ends of the first thermistor TH1 are connected with a relay (6) for controlling the on-off of the first thermistor TH 1.