CN214045434U

CN214045434U - Power supply circuit with voltage stabilization control

Info

Publication number: CN214045434U
Application number: CN202022753243.6U
Authority: CN
Inventors: 王海根; 赖阳明; 赖炳初
Original assignee: Guangzhou Leadway Electronic Co ltd
Current assignee: Guangzhou Leadway Electronic Co ltd
Priority date: 2020-11-24
Filing date: 2020-11-24
Publication date: 2021-08-24
Anticipated expiration: 2030-11-24

Abstract

The utility model relates to a power supply circuit who possesses steady voltage control, include with the commercial power connection and be used for the filtering rectification input unit to commercial power rectification filtering, filtering rectification input unit is coupled with the PFC main loop unit that steps up the commercial power, PFC main loop unit electricity is connected with carries out the SB standby unit that detects PFC main loop unit output voltage, PFC main loop unit still electricity is connected with and is used for carrying out the step-down unit that steps down to PFC main loop unit output voltage. This application has filtering rectification input unit mainly is filtering input alternating current electric wire netting and produces the interference, prevent to damage the power, also can filtering power itself produced the interference to the electric wire netting, become the alternating current through the rectification and provide the back level power supply, PFC major loop passes through signal control circuit and peripheral element and steps up the voltage after the rectification to the stable direct current voltage supply voltage reduction unit that the user needs the voltage value, voltage reduction unit steps down the high pressure, in order to obtain the effect with the output voltage value that the user needs.

Description

Power supply circuit with voltage stabilization control

Technical Field

The present application relates to the field of power supplies, and more particularly, to a power supply circuit with voltage stabilization control.

Background

The power supply is a power component of the computer, and the electric energy source of each component in the computer depends on the power supply, which is the most basic premise for ensuring the normal operation of computer hardware. Every accessory in the computer has certain power consumption, needs direct current with different voltage, and the main function of the power supply is to convert external alternating current into direct current meeting the requirements of the computer, and the function of the power supply is similar to that of an alternating current adapter used for connecting a small electric appliance with commercial power. The power supply of the PC is not used in the situation that the power supply of the PC requires a relatively fixed standard, unlike the situation that the adapter is only suitable for a specific container, and the work flow of the power supply is relatively complicated, so the quality of the power supply directly influences whether the computer can normally operate.

In view of the above-mentioned related technologies, the inventor believes that due to the discreteness of products of different power manufacturers, the quality of the power may be different, which may cause the situation that the motherboard cannot work when being collocated with a certain power, that is, the motherboard is incompatible with the power, and normal power supply of the power to the motor is affected.

SUMMERY OF THE UTILITY MODEL

The application provides a power supply circuit with voltage stabilization control for the stability of power supply output voltage.

The power supply circuit with voltage stabilization control adopts the following technical scheme:

a power supply circuit with voltage stabilization control comprises a filtering and rectifying input unit which is connected with a mains supply and used for rectifying and filtering the mains supply, wherein the filtering and rectifying input unit is coupled with a PFC (power factor correction) main loop unit for boosting the mains supply, the PFC main loop unit is electrically connected with an SB standby unit for detecting the output voltage of the PFC main loop unit, and the PFC main loop unit is also electrically connected with a voltage reduction unit for reducing the output voltage of the PFC main loop unit.

By adopting the technical scheme, the filtering and rectifying input unit mainly filters interference generated by an input alternating current power grid, prevents the power supply from being damaged, and can also filter the interference generated by the power supply to the power grid, the alternating current is rectified to be converted into direct current to provide the post-stage power supply, the PFC main loop boosts the rectified voltage to the stable direct current voltage of the voltage value required by a user through the signal control circuit and the peripheral element and supplies the stable direct current voltage to the voltage reduction unit, and the voltage reduction unit reduces the voltage of the high voltage to obtain the output voltage value required by the user.

Optionally, the filtering and rectifying input unit includes a first common-mode inductor LF1, a second common-mode inductor LF2, a third common-mode inductor LF3, and a rectifier bridge BD1, an input end of the first common-mode inductor LF1 is connected in parallel with a voltage dependent resistor VD1, and two input ends of the first common-mode inductor LF1 are respectively connected with a first fuse F1 and a second fuse F2; the output end of the first common mode inductor LF1 is further connected in parallel with a first capacitor CY1, the first capacitor CY1 is connected in series with a second capacitor CY2, the connection node of the first capacitor CY1 and the second capacitor CY2 is grounded, a first thermistor TH1 is connected between the input end of the second common mode inductor LF2 and the output end of the first common mode inductor LF1, a first electrolytic capacitor CX1 is connected between the two input ends of the second common mode inductor LF2, a first resistor RX1 and a fourth resistor RX4 are further connected in series between the two input ends of the second common mode inductor LF2 in sequence, a third capacitor CY3 and a fourth capacitor CY4 are connected between the two output ends of the second common mode inductor LF2 in sequence, the connection node of the third capacitor CY3 and the fourth capacitor CY4 is grounded, a fourth resistor RX 23, a fourth resistor RX3, a fourth resistor RX 58573 57324 and a fourth resistor RX 58573 are connected between the two output ends of the second common mode inductor LF 5 in sequence, the third common mode inductor LF3 is coupled to the output end of the second common mode inductor LF2, the rectifier bridge BD1 is coupled to the output end of the third common mode inductor LF3, the negative pole of the rectifier bridge BD1 is connected to the PFC main circuit unit, and the positive pole of the rectifier bridge BD1 is connected to the VAC terminal.

Through adopting above-mentioned technical scheme, through the effect of three common mode inductance and other electronic components mutually supporting to be used for restraining the electromagnetic wave external radiation emission that the high-speed signal line produced, reduce the power at the during operation, to other electronic equipment's influence, first thermistor TH 1's resistance is directly proportional with the generating heat of circuit, and first thermistor TH1 plays the effect of protection circuit.

Optionally, the PFC main loop unit includes an NPN type second transistor Q2, a PNP type third transistor QW3, a depletion type first MOS tube Q1, a sixth electrolytic capacitor C6 and a seventh electrolytic capacitor C7 are sequentially connected in series between the drain and the source of the depletion type first MOS tube Q1, the source of the depletion type first MOS tube Q1 is grounded, the gate of the depletion type first MOS tube Q1 is electrically connected with the emitter of a third triode Q3, the gate of the depletion type first MOS tube Q1 is grounded through a third resistor R3, the gate of the depletion type first MOS tube Q1 is electrically connected with the emitter of a second triode Q2 through a fourth resistor R4, the collector of the third triode Q3 is grounded, the base of the third triode Q3 is connected with the base of the second triode Q2, the emitter of the second triode Q2 is connected with a fourth resistor R4, the collector of the second triode Q2 is grounded through a fourth electrolytic capacitor C4, and the second triode Q2 is grounded through a fifth electrolytic capacitor C5;

the PFC main loop unit further comprises a first capacitor C1 connected in parallel at two ends of a rectifier bridge, the anode of the rectifier bridge is connected with a first inductor L1, a twelfth diode D12 is electrically connected in the forward direction between the anode of the rectifier bridge and the first inductor L1, the anode of a twelfth diode D12 is connected in series with an eleventh diode D11 in the forward direction, the cathode of an eleventh diode D11 is connected with the second capacitor C2 and then grounded, the cathode of a twelfth diode D12 is connected with a VSB port, the first inductor L1 is connected with a first diode D1 in the forward direction, the cathode of a first diode D1 is connected with a VDC port, the forward direction of a first diode D1 is connected with a second diode D2 in parallel, the drain of a depletion type first MOS tube Q1 is electrically connected with the connection node of the first diode D1 and the second diode D2, and the cathode of an eleventh diode D11 is electrically connected with the connection node of the first diode D1 and the second diode D2; the first diode D1 is connected with the voltage reduction unit after passing through the third fuse F3;

the cathode of the first diode D1 is grounded after passing through the third capacitor C3, and the cathode of the first diode D1 is grounded after passing through the eighth fuse F8 and the socket CON 4;

the negative electrode of the rectifier bridge is connected with a second capacitor C2 after passing through a second resistor R2, and a second resistor R2 is connected with the cathode of a twelfth diode D12 after passing through a seventeenth capacitor C17.

Through adopting above-mentioned technical scheme, through the effect of mutually supporting between first inductance L1, second triode Q2, third triode Q3 and the first MOS pipe Q1 of depletion type to the realization is stepped up the voltage of input, in order to reach the higher voltage of higher commercial power, so that supply voltage reduction unit.

Optionally, the voltage reduction unit includes a depletion type sixth MOS transistor Q6 and a depletion type fifth MOS transistor Q5, a drain of the depletion type sixth MOS transistor Q6 is connected to the VDC port through a third fuse F3, a gate of the depletion type sixth MOS transistor Q6 is connected to a MOSG1 pin of the PWM control chip through a twelfth resistor R12, two ends of the twelfth resistor R12 are connected in parallel in a forward direction with a fourth diode D4, a thirteenth resistor R13 is connected in series between the gate and the source of the depletion type sixth MOS transistor Q6, a source of the depletion type sixth MOS transistor Q6 is electrically connected to a drain of the depletion type fifth MOS transistor Q5, a gate of the depletion type fifth MOS transistor Q5 is connected to a MOSG2 pin of the PWM control chip through a fourteenth resistor R14, two ends of the fourteenth resistor R14 are connected in parallel in a forward direction with a third diode D3, a drain of the depletion type fifth MOS transistor Q5 is connected between the gate and the source of the depletion type fifth MOS transistor Q5 in series with a fifteenth resistor R585, and a source of the depletion type sixth MOS transistor Q15 is connected to a fifteenth transistor vvc 23 and a PWM control chip;

a source electrode of the depletion type sixth MOS transistor Q6 and a drain electrode connection node of the depletion type fifth MOS transistor Q5 are connected with a second inductor L2, one end of the second inductor L2 is connected with a first transformer T1, the first transformer T1 comprises a primary coil and two secondary coils, a first terminal of the first transformer T1 is connected with a second inductor L2, a second terminal of the first transformer T1 is grounded through an eighth electrolytic capacitor C8, the eighth electrolytic capacitor C8 is connected with a source electrode of the depletion type fifth MOS transistor Q5, a second terminal of the first transformer T1 is sequentially connected in series with a ninth electrolytic capacitor C9 and a sixteenth resistor R16 and then is connected with an OPP pin of a PWM control chip, and two ends of the sixteenth resistor R16 are connected in parallel with a seventeenth resistor R17;

the fourth terminal and the fifth terminal of the first transformer T1 are connected with a GND1 pin of a PWM control chip and are electrically connected;

a fifth diode group D5 and a sixth diode group D6 are connected to a third terminal of the first transformer T1, the fifth diode group D5 and the sixth diode group D6 both comprise two diodes connected in parallel in the forward direction, the fifth diode group D5 and the sixth diode group D6 are connected in parallel in the forward direction, a cathode of the fifth diode group D5 and a cathode of the sixth diode group D6 are connected, a cathode of the fifth diode group D5 and a cathode connection node of the sixth diode group D6 are electrically connected with a GND1 pin of the PWM control chip after passing through a tenth electrolytic capacitor C10, and a cathode of the fifth diode group D5 and a cathode connection node of the sixth diode group D6 are electrically connected with a GND1 pin of the PWM control chip after passing through an eleventh electrolytic capacitor C11;

a seventh diode group D7 and an eighth diode group D8 having the same structures as the fifth diode group D5 and the sixth diode group D6 are also connected to the sixth terminal of the first transformer T1, and the cathode of the seventh diode group D7 and the cathode of the eighth diode group D8 are connected to a connection node between the cathode of the fifth diode group D5 and the cathode of the sixth diode group D6;

the voltage reduction unit further comprises a ninth diode group D9, the ninth diode group D9 is respectively connected with the fifth diode group D5 and the sixth diode group D6, one anode of the ninth diode group D9 is connected with the port 24VB, and the other anode pin of the ninth diode group D9 is electrically connected with the GND1 pin of the PWM control chip after passing through a twenty-first resistor R21; a cathode of the ninth diode group D9 is connected with a third inductor L3, one end of a third inductor L3 is electrically connected with a GND1 pin of the PWM control chip after passing through a thirteenth capacitor C13, one end of a third inductor L3 is electrically connected with a GND2 pin of the PWM control chip after passing through a fourteenth capacitor C14, an eighteenth resistor R18 is connected in series between the twenty-first resistor R21 and the thirteenth capacitor C13, a nineteenth resistor R19 is connected in series between the twenty-first resistor R21 and the thirteenth capacitor C13, a twentieth resistor R20 is connected in series between the twenty-first resistor R21 and the thirteenth capacitor C13, one end of the eighteenth resistor R18 is connected at a connection node between the third inductor L3 and the ninth diode group D9, and a 24V port is arranged at a connection node between the third inductor L3 and the ninth diode group D9 to output 24V voltage;

a fourth common-mode inductor L4 is connected to the third inductor L3, one input end of the fourth common-mode inductor L4 is connected to the third inductor L3, the other input end of the fourth common-mode inductor L4 is connected to the twentieth resistor R20, one output end of the fourth common-mode inductor L4 is connected to a VOUT24V port, and the other output end of the fourth common-mode inductor L4 is connected to a GND2 port; a fifteenth electrolytic capacitor C15 is connected between two output ends of the fourth common mode inductor L4, one end of a fifteenth electrolytic capacitor C15 is grounded after passing through a tenth capacitor CY10, a sixteenth electrolytic capacitor C16 is connected between the two output ends of the fourth common mode inductor L4, one end of the fourth common mode inductor L4, which is connected with a twentieth resistor R20, is connected with an LED lamp bank, one anode end of the LED lamp bank is connected with a 24VA port after passing through a twenty-second resistor R22, the other anode end of the LED lamp bank is sequentially connected with a thirty-one-hundred-eleventh resistor R131 in series, an NPN-type twenty-sixth triode Q26 is characterized in that a connection node of the LED lamp group and the twenty-first thirty-first resistor R131 is provided with a 24V/NGK port, an emitting electrode of the twenty-sixth triode Q26 is connected with the twentieth resistor R20, a twenty-third twelve R132 resistor is connected between the emitting electrode and a base electrode of the twenty-sixth triode Q26, and a collector electrode of the twenty-sixth triode Q26 is connected with 24 VB.

By adopting the technical scheme, the depletion type sixth MOS tube Q6 and the depletion type fifth MOS tube Q5 are used as switches to control the on-off of the voltage reduction unit and the PFC main loop unit, and the first transformer T1 reduces the output voltage of the PFC main loop unit to obtain the voltage meeting the requirement of a user.

Optionally, the SB standby unit includes a second transformer T2, a first terminal of the second transformer T2 is connected to the VSB port, a second terminal of the second transformer T2 is connected to a sixth pin of the first chip IC1 of FSL-126HR, a third terminal of the second transformer T2 is connected in series to the positive direction of the fifth diode D15, a fifteenth diode D15 is grounded via a nineteenth electrolytic capacitor C19, a cathode of the fifteenth diode D15 is connected to an NPN-type thirteenth triode Q13, a base of the thirteenth triode Q13 is connected to the fourth zener diode DZ4 and grounded, two ends of the fourth zener diode DZ4 are connected in parallel to a seventy-two capacitor C72, a collector of the thirteenth triode Q13 is connected to a collector of an NPN-type fourth triode Q24 via a fifth resistor R5, an emitter of the twenty-fourth triode Q24 is grounded, a base of the twenty-fourth triode Q24 is grounded via a tenth resistor R10, two ends of the tenth resistor R10 are connected with a seventy-three capacitor C73 in parallel, a sixteenth diode D16, a twenty-eight resistor R28 and a second voltage stabilizing diode ZD2 are sequentially connected with a fourth terminal of the second transformer T2 in series, the second voltage stabilizing diode ZD2 is grounded, and a thirty-third resistor R30 of the second transformer T2 is grounded; a base electrode of the twenty-fourth triode Q24 is connected with a receiving side of a twelfth optocoupler C12, an emitter electrode of the twelfth optocoupler C12 is connected with a tenth resistor R10, and a collector electrode of the twelfth optocoupler C12 is connected with a ninth resistor R9;

a second terminal of the second transformer T2 is connected with a first chip IC1, a fifth pin of the first chip IC1 is sequentially connected in series with a twenty-fourth resistor R24 and a twenty-third resistor R23, the twenty-third resistor R23 is connected with the VSB port after passing through a first fuse FR1, an eight pin of the first chip IC1 is connected in series with a fourteenth diode D14 in the forward direction, a cathode of the fourteenth diode D14 is connected in series with a twenty-fifth resistor R25, the twenty-fifth resistor R25 is connected with the first fuse FR1, and two ends of the twenty-fifth resistor R63 25 are connected in parallel with an eighteenth capacitor C18; a third pin of the first chip IC1 is connected with a receiving side of a third optical coupler IC3, an emitter of the third optical coupler IC3 is grounded, two ends of the third optical coupler IC3 are connected with a third voltage regulator tube ZD3 in parallel, two ends of the third optical coupler IC3 are connected with a twenty-ninth resistor R29 in parallel, and two ends of the third optical coupler IC3 are connected with a twenty-second capacitor C22 in parallel;

an eighteenth diode D18 is connected in series in the forward direction of a seventh terminal of the second transformer T2, a twenty-seventh electrolytic capacitor C27 is connected between the cathode of the eighteenth diode D18 and an eighth terminal of the second transformer T2, a forty-fourth resistor R40 is connected in parallel with two ends of the twenty-seventh electrolytic capacitor C27, a forty-first resistor R41 is connected in parallel with two ends of the forty-fourth resistor R40, a forty-second resistor R42 is connected with the cathode of the eighteenth diode D18, the forty-second resistor R42 is connected in series with the emission side of the third optocoupler IC3, a sixth zener diode IC6 is connected in series in the reverse direction of the cathode of the third optocoupler IC3, the sixth zener diode IC6 is grounded, and one end of the forty-third resistor R43 is connected with the sixth zener diode IC 6; a cathode of the eighteenth diode D18 is connected with a forty-fourth resistor R44, a forty-fourth resistor R44 is connected in series with a forty-fifth resistor R45 and then grounded, and a twenty-ninth capacitor C29 is connected in series between a cathode of the third optocoupler IC3 and the forty-fourth resistor R44;

a cathode of the eighteenth diode D18 is electrically connected with a fifth inductor L5, one end of the fifth inductor L5 is grounded after passing through a forty-sixth resistor R46, one end of the fifth inductor L5 is grounded after passing through a forty-seventh resistor R47, one end of the fifth inductor L5 is connected with a receiving side of a first dodeca-opto-coupler C12 after passing through a seventy-first resistor R71, a cathode of the first dodeca-opto-coupler C12 is connected with an NPN-type twenty-fifth triode Q25, an emitter of the twenty-fifth triode Q25 is grounded, a base of the twenty-fifth triode Q25 is grounded after passing through a seventy-second resistor R72, a base of the twenty-fifth triode Q25 is connected with a 24VB 24 after passing through a hundred-eighth resistor R130 and an eleventh voltage-stabilizing diode ZD 42, two ends of the twelfth resistor R72 are connected with a seventy-fourth capacitor C74 in parallel, one end of the fifth inductor L5 is grounded after passing through a forty-eighth resistor R58 48, one end of a fifth inductor L5 is grounded through a twenty-eighth capacitor C28, one end of a fifth inductor L5 is connected with a nineteenth diode D19 in series in the forward direction, the cathode of the nineteenth diode D19 is connected with a 5VSB terminal, the cathode of the nineteenth diode D19 is grounded through a thirty-sixth capacitor C30, and the cathode of the nineteenth diode D19 is grounded through a thirty-eighth capacitor C31.

Through adopting above-mentioned technical scheme, SB standby unit is used for implementing the output voltage value that detects the voltage reduction unit to when the voltage of the output of voltage reduction unit is less than the rated value, realize the undervoltage protection to the circuit.

Optionally, the PFC main circuit unit is electrically connected to a PFC small card control unit for detecting an output voltage of the voltage reduction unit.

By adopting the technical scheme, the PFC small card control unit provides driving signal control for the PFC main loop unit.

Optionally, the PFC smart card control unit includes a first chip 1IC1, a first pin of a first chip 1IC1 with a model number CM6500 is sequentially connected in series with a first resistor 1R1 and a first electrolytic capacitor 1C1, a seventh pin of the first chip 1IC1 is connected in series with the first electrolytic capacitor 1C1 through a seventeenth resistor 1R17, a seventh pin of the first chip 1IC1 is sequentially connected in series with a seventh electrolytic capacitor 1C7, a third electrolytic capacitor 1C3, a thirteenth resistor 1R13, a twelfth resistor 1R12 and an eleventh resistor 1R11, the eleventh resistor 1R11 is connected with a VCA terminal, a sixth pin of the first chip 1IC1 is connected in series with the first electrolytic capacitor 1C1 through a nineteenth capacitor 1R19, a sixth pin of the first chip 1IC1 is connected in series with a third electrolytic capacitor 1C 18 through an eighteenth resistor 1R18, and a fourth pin of the first chip 1IC 599 is connected with a fourth capacitor 599, a fourth pin of the first chip 1IC1 is connected with a third electrolytic capacitor 1C3 through a fifteenth resistor 1R15, and a fourth pin of the first chip 1IC1 is connected with a third electrolytic capacitor 1C3 and a connection node of a thirteenth resistor 1R13 through a fourteenth resistor 1R 14; a third pin of the first chip 1IC1 is connected with a third electrolytic capacitor 1C3 through a first zener diode 1ZD1, a third pin of the first chip 1IC1 is connected with a third electrolytic capacitor 1C3 through a sixth electrolytic capacitor 1C6, and a third pin of the first chip 1IC1 is connected with a connection node of a first resistor R1 and a second resistor R2 through a sixteenth resistor 1R 16; a second pin of the first chip 1IC1 is sequentially connected with a tenth resistor 1R10, a ninth resistor 1R9 and an eighth resistor 1R8, the eighth resistor 1R8 is connected with a VCA terminal, and a second pin of the first chip 1IC1 is connected with a third electrolytic capacitor 1C3 after passing through a fourteenth electrolytic capacitor C14;

a first pin of the first chip 1IC1 is connected with a second electrolytic capacitor 1C2 and a thirteenth electrolytic capacitor 1C13 in series, one end of the second electrolytic capacitor 1C2 is connected with the first electrolytic capacitor 1C1, and the thirteenth electrolytic capacitor 1C13 is connected with the third electrolytic capacitor 1C 3;

a fourteenth pin of the first chip 1IC1 is sequentially connected with a second resistor 1R2 and an eighth electrolytic capacitor 1C8 in series, an eighth electrolytic capacitor 1C8 is connected with a third electrolytic capacitor 1C3, a fourteenth pin of the first chip 1IC1 is connected with a ninth electrolytic capacitor 1C9, the other end of the ninth electrolytic capacitor 1C9 is connected with a connection node of the eighth electrolytic capacitor 1C8 and the third electrolytic capacitor 1C3, a thirteenth pin of the first chip 1IC1 is connected with the third electrolytic capacitor 1C3 through a twelfth electrolytic capacitor 1C12, a thirteenth pin of the first chip 1IC1 is connected with the third electrolytic capacitor 1C3 through a third resistor 1R3, a thirteenth pin of the first chip 1IC1 is sequentially connected with a twenty-second resistor 1R22, a twenty-first resistor 1R21, a twenty-first resistor 1R20 in series, and a twenty-first resistor VDC 20 is electrically connected with a VDC terminal; a twelfth pin of the first chip 1IC1 is electrically connected with an emission side of the second optical coupler 1IC2 through a fifth resistor 1R5, a cathode of the second optical coupler 1IC2 is electrically connected with a ninth pin of the first chip 1IC1, an eleventh pin of the first chip 1IC1 is connected with a VCC4 terminal, an eleventh pin of the first chip 1IC1 is connected with a third electrolytic capacitor 1C3 through an eleventh electrolytic capacitor 1C11, an eleventh pin of the first chip 1IC1 is connected with a ninth resistor R9, a tenth pin of the first chip 1IC1 is connected with a base of a third triode Q3 through a fourth resistor 1R4, a fourth resistor 1R4 is connected with a base of a second triode Q2, and an eighth pin of the first chip 1IC1 is connected with a third electrolytic capacitor 1C 3;

a PNP-type thirteenth pole tube Q10 is connected to the ninth resistor R9, a thirty-fourth resistor 34 is connected between the base and the emitter of the thirteenth pole tube Q10, the collector of the thirteenth pole tube Q10 is connected with the receiving side of the second optical coupler 1IC2, and the emitter of the second optical coupler 1IC2 is grounded; the collector of the thirteenth polar tube Q10 is grounded through a sixty-seven electrolytic capacitor C67, the collector of the thirteenth polar tube Q10 is grounded through a seventy-three resistor R73, and the collector of the thirteenth polar tube Q10 is connected with the VCC5 port.

By adopting the technical scheme, the driving signal is provided for the PFC main loop unit through the matching of electronic components of all parts.

Optionally, a relay for controlling the on/off of the first thermistor TH1 is connected to both ends of the first thermistor TH 1.

Through adopting above-mentioned technical scheme, the relay mainly is the first thermistor TH1 of short circuit after the power starts, makes the normal operating loss of power minimum.

In summary, the present application includes at least one of the following beneficial technical effects:

1. the filtering and rectifying input unit is mainly used for filtering interference generated by an input alternating current power grid, preventing the power supply from being damaged, and also filtering interference generated by the power supply to the power grid, alternating current is rectified to be direct current to provide power for a later stage, a PFC (power factor correction) main loop boosts rectified voltage to stable direct current voltage with a voltage value required by a user through a signal control circuit and a peripheral element and supplies the stable direct current voltage to the voltage reduction unit, and the voltage reduction unit reduces the voltage of the high voltage to obtain a stable output voltage value required by the user;

the SB standby unit is used for detecting the output voltage value of the voltage reduction unit so as to realize the undervoltage protection of the circuit when the output voltage of the voltage reduction unit is lower than a rated value;

and 3, the PFC small card control unit provides driving signal control for the PFC main loop unit.

Drawings

FIG. 1 is a schematic diagram of an overall circuit structure according to an embodiment of the present application;

FIG. 2 is a schematic diagram illustrating a connection relationship between a smoothing and rectifying input unit and a relay according to an embodiment of the present application;

fig. 3 is a schematic diagram of an overall structure of a PFC main loop unit according to an embodiment of the present disclosure;

fig. 4 is a schematic diagram of an overall structure of a voltage reduction circuit according to an embodiment of the present application;

FIG. 5 is a schematic diagram of the overall structure of an SB standby unit in an embodiment of the present application;

fig. 6 is a schematic diagram of an overall structure of a PFC smart card control unit according to an embodiment of the present disclosure;

fig. 7 is a schematic diagram of an overall structure of a power output feedback voltage stabilization unit according to an embodiment of the present application.

Description of reference numerals: 1. a filtering rectification input unit; 2. a PFC main loop unit; 3. a voltage reduction unit; 4. an SB standby unit; 5. a PFC small card control unit; 6. a relay; 7. a power output feedback voltage stabilizing unit; 8. and a PWM chip control circuit.

Detailed Description

The present application is described in further detail below with reference to figures 1-7.

The embodiment of the application discloses a power supply circuit with voltage stabilization control. Referring to fig. 1, the power circuit with voltage regulation control includes a filtering and rectifying input unit 1 connected to a mains supply and used for rectifying and filtering the mains supply, a PFC main loop unit 2 for boosting the mains supply is coupled to the filtering and rectifying input unit 1, the PFC main loop unit 2 is electrically connected to an SB standby unit 4 for detecting an output voltage of the PFC main loop unit 2, and the PFC main loop unit 2 is also electrically connected to a voltage reduction unit 3 for reducing the output voltage of the PFC main loop unit 2.

Referring to fig. 2, the filtering and rectifying input unit 1 includes a first common mode inductor LF1, a second common mode inductor LF2, a third common mode inductor LF3, and a rectifier bridge BD1, wherein an input end of the first common mode inductor LF1 is connected in parallel with a voltage dependent resistor VD1, and two input ends of the first common mode inductor LF1 are respectively connected with a first fuse F1 and a second fuse F2; the output end of the first common mode inductor LF1 is further connected in parallel with a first capacitor CY1, the first capacitor CY1 is connected in series with a second capacitor CY2, the connection node between the first capacitor CY1 and the second capacitor CY2 is grounded, a first thermistor TH1 is connected between the input end of the second common mode inductor LF2 and the output end of the first common mode inductor LF1, a first electrolytic capacitor CX1 is connected between the two input ends of the second common mode inductor LF2, a first resistor RX1 and a fourth resistor RX4 are further connected in series between the two input ends of the second common mode inductor LF2, a third capacitor CY3 and a fourth capacitor CY4 are connected between the two output ends of the second common mode inductor LF2 in sequence, the connection node between the third capacitor CY3 and the fourth capacitor CY4 is grounded, a fourth resistor RX 2 and a third capacitor RX3 are connected between the two output ends of the second common mode inductor LF2 in sequence, and a second common mode resistor LF3 is coupled to the output end of the third inductor CY3, the rectifier bridge BD1 is coupled to the output end of the third common mode inductor LF3, the negative electrode of the rectifier bridge BD1 is connected to the PFC main circuit unit 2, and the positive electrode of the rectifier bridge BD1 is connected to the VAC terminal.

Referring to fig. 2, a relay for controlling the on/off of the first thermistor TH1 is connected to both ends of the first thermistor TH 1.

Referring to fig. 3, the PFC main circuit unit 2 includes an NPN type second transistor Q2, a PNP type third transistor QW3, a depletion type first MOS tube Q1, a sixth electrolytic capacitor C6 and a seventh electrolytic capacitor C7 are sequentially connected in series between the drain and the source of the depletion type first MOS tube Q1, the source of the depletion type first MOS tube Q1 is grounded, the gate of the depletion type first MOS tube Q1 is electrically connected with the emitter of a third triode Q3, the gate of the depletion type first MOS tube Q1 is grounded through a third resistor R3, the gate of the depletion type first MOS tube Q1 is electrically connected with the emitter of a second triode Q2 through a fourth resistor R4, the collector of the third triode Q3 is grounded, the base of the third triode Q3 is connected with the base of the second triode Q2, the emitter of the second triode Q2 is connected with a fourth resistor R4, the collector of the second triode Q2 is grounded through a fourth electrolytic capacitor C4, and the second triode Q2 is grounded through a fifth electrolytic capacitor C5;

referring to fig. 3, the PFC main circuit unit 2 further includes a first capacitor C1 connected in parallel to two ends of the rectifier bridge, a first inductor L1 is connected to the anode of the rectifier bridge, a twelfth diode D12 is electrically connected in the forward direction between the anode of the rectifier bridge and the first inductor L1, an eleventh diode D11 is connected in the forward direction of the anode of the twelfth diode D12 in series, the cathode of the eleventh diode D11 is connected to the second capacitor C2 and then grounded, the cathode of the twelfth diode D12 is connected to the VSB port, a first diode D1 is connected in the forward direction of the first inductor L1, the cathode of the first diode D1 is connected to the VDC port, a second diode D2 is connected in the forward direction of the first diode D1 in parallel, the drain of the depletion type first MOS transistor Q1 is electrically connected to the connection node of the first diode D1 and the second diode D2, and the cathode of the eleventh diode D11 is electrically connected to the connection node of the first diode D1 and the second diode D2; the first diode D1 is connected to the voltage dropping unit 3 through the third fuse F3.

Referring to fig. 3, the cathode of the first diode D1 is grounded through the third capacitor C3, and the cathode of the first diode D1 is grounded through the eighth fuse F8 and the socket CON 4;

referring to fig. 3, the cathode of the rectifier bridge is connected to the second capacitor C2 through the second resistor R2, and the second resistor R2 is connected to the cathode of the twelfth diode D12 through the seventeenth capacitor C17.

Referring to fig. 4, the voltage dropping unit 3 includes a depletion type sixth MOS transistor Q6 and a depletion type fifth MOS transistor Q5, a drain of the depletion type sixth MOS transistor Q6 is connected to the VDC port through a third fuse F3, a gate of the depletion type sixth MOS transistor Q6 is connected to a MOSG1 pin of the PWM control chip through a twelfth resistor R12, both ends of the twelfth resistor R12 are forward and parallel connected to a fourth diode D4, a thirteenth resistor R13 is connected in series between the gate and the source of the depletion type sixth MOS transistor Q6, a source of the depletion type sixth MOS transistor Q6 is electrically connected to a drain of the depletion type fifth MOS transistor Q5, a gate of the depletion type fifth MOS transistor Q5 is connected to a MOSG2 pin of the PWM control chip through a fourteenth resistor R14, both ends of the fourteenth resistor R14 are forward and parallel connected to a third diode D3, a gate of the depletion type fifth MOS transistor Q5 is connected to a source of the depletion type fifth MOS transistor Q465, and a source of the depletion type fifth MOS transistor Q585 is connected to a source of the PWM control chip through a fifteenth resistor vvr 15 and a fifteenth resistor vvc 585;

referring to fig. 4, a node connecting a source of the depletion type sixth MOS transistor Q6 and a drain of the depletion type fifth MOS transistor Q5 is connected with a second inductor L2, one end of the second inductor L2 is connected with a first transformer T1, the first transformer T1 includes a primary coil and two secondary coils, a first terminal of the first transformer T1 is connected with the second inductor L2, a second terminal of the first transformer T1 is grounded through an eighth electrolytic capacitor C8, the eighth electrolytic capacitor C8 is connected with a source of the depletion type fifth MOS transistor Q5, a second terminal of the first transformer T1 is sequentially connected in series with a ninth electrolytic capacitor C9 and a sixteenth resistor R16 and then connected with an OPP pin of a PWM control chip, and two ends of the sixteenth resistor R16 are connected in parallel with a seventeenth resistor R17;

referring to fig. 4, the fourth terminal and the fifth terminal of the first transformer T1 are connected to the GND1 pin of the PWM control chip;

referring to fig. 4, a fifth diode group D5 and a sixth diode group D6 are connected to a third terminal of the first transformer T1, each of the fifth diode group D5 and the sixth diode group D6 includes two diodes connected in parallel in a forward direction, the fifth diode group D5 and the sixth diode group D6 are connected in parallel in a forward direction, a cathode of the fifth diode group D5 and a cathode of the sixth diode group D6 are connected, a connection node of a cathode of the fifth diode group D5 and a cathode of the sixth diode group D6 is electrically connected to a GND1 pin of the PWM control chip through a tenth electrolytic capacitor C10, and a connection node of a cathode of the fifth diode group D5 and a cathode of the sixth diode group D6 is electrically connected to a GND1 pin of the PWM control chip through an eleventh electrolytic capacitor C11;

referring to fig. 4, a seventh diode group D7 and an eighth diode group D8, which have the same structure as the fifth diode group D5 and the sixth diode group D6, are also connected to the sixth terminal of the first transformer T1, and a cathode of the seventh diode group D7 and a cathode of the eighth diode group D8 are connected to a connection node between the cathode of the fifth diode group D5 and the cathode of the sixth diode group D6;

referring to fig. 4, the voltage dropping unit 3 further includes a ninth diode group D9, the ninth diode group D9 is respectively connected to the fifth diode group D5 and the sixth diode group D6, one anode of the ninth diode group D9 is connected to the 24VB port, and the other anode pin of the ninth diode group D9 is electrically connected to the GND1 pin of the PWM control chip through a twenty-first resistor R21; a cathode of the ninth diode group D9 is connected with a third inductor L3, one end of a third inductor L3 is electrically connected with a GND1 pin of the PWM control chip after passing through a thirteenth capacitor C13, one end of a third inductor L3 is electrically connected with a GND2 pin of the PWM control chip after passing through a fourteenth capacitor C14, an eighteenth resistor R18 is connected in series between the twenty-first resistor R21 and the thirteenth capacitor C13, a nineteenth resistor R19 is connected in series between the twenty-first resistor R21 and the thirteenth capacitor C13, a twentieth resistor R20 is connected in series between the twenty-first resistor R21 and the thirteenth capacitor C13, one end of the eighteenth resistor R18 is connected at a connection node between the third inductor L3 and the ninth diode group D9, and a 24V port is arranged at a connection node between the third inductor L3 and the ninth diode group D9 to output 24V voltage;

referring to fig. 4, a fourth common-mode inductor L4 is connected to the third inductor L3, one input terminal of the fourth common-mode inductor L4 is connected to the third inductor L3, the other input terminal of the fourth common-mode inductor L4 is connected to the twentieth resistor R20, one output terminal of the fourth common-mode inductor L4 is connected to the VOUT24V port, and the other output terminal of the fourth common-mode inductor L4 is connected to the GND2 port; a fifteenth electrolytic capacitor C15 is connected between two output ends of the fourth common mode inductor L4, one end of a fifteenth electrolytic capacitor C15 is grounded after passing through a tenth capacitor CY10, a sixteenth electrolytic capacitor C16 is connected between the two output ends of the fourth common mode inductor L4, one end of the fourth common mode inductor L4, which is connected with a twentieth resistor R20, is connected with an LED lamp bank, one anode end of the LED lamp bank is connected with a 24VA port after passing through a twenty-second resistor R22, the other anode end of the LED lamp bank is sequentially connected with a thirty-one-hundred-eleventh resistor R131 in series, an NPN-type twenty-sixth triode Q26 is characterized in that a connection node of the LED lamp group and the twenty-first thirty-first resistor R131 is provided with a 24V/NGK port, an emitting electrode of the twenty-sixth triode Q26 is connected with the twentieth resistor R20, a twenty-third twelve R132 resistor is connected between the emitting electrode and a base electrode of the twenty-sixth triode Q26, and a collector electrode of the twenty-sixth triode Q26 is connected with 24 VB.

Referring to fig. 5, the SB standby unit 4 includes a second transformer T2, a first terminal of a second transformer T2 is connected to a VSB port, a second terminal of a second transformer T2 is connected to a sixth pin of a first chip IC1 of FSL-126HR, a third terminal of the second transformer T2 is connected in series in a forward direction to a fifteenth diode D15, a fifteenth diode D15 is grounded through a nineteenth electrolytic capacitor C19, a cathode of the fifteenth diode D15 is connected to an NPN-type thirteenth triode Q13, a base of a thirteenth triode Q13 is connected to a fourth zener diode DZ4 and grounded, both ends of the fourth zener diode DZ4 are connected in parallel to a seventy-second capacitor C72, a collector of the thirteenth triode Q13 is connected to a collector of a twenty-fourth triode Q24 of NPN-type through a fifth resistor R5, an emitter of the twenty-fourth triode Q24 is grounded, a base of the twenty-fourth triode Q24 is grounded through a tenth resistor R10, two ends of the tenth resistor R10 are connected with a seventy-three capacitor C73 in parallel, a sixteenth diode D16, a twenty-eight resistor R28 and a second voltage stabilizing diode ZD2 are sequentially connected with a fourth terminal of the second transformer T2 in series, the second voltage stabilizing diode ZD2 is grounded, and a thirty-third resistor R30 of the second transformer T2 is grounded; a base electrode of the twenty-fourth triode Q24 is connected with a receiving side of a twelfth optocoupler C12, an emitter electrode of the twelfth optocoupler C12 is connected with a tenth resistor R10, and a collector electrode of the twelfth optocoupler C12 is connected with a ninth resistor R9;

referring to fig. 5, a first chip IC1 is connected to a second terminal of a second transformer T2, a fifth pin of the first chip IC1 is sequentially connected in series with a twenty-fourth resistor R24 and a twenty-third resistor R23, a twenty-third resistor R23 is connected to a VSB port after passing through a first fuse FR1, an eighth pin of the first chip IC1 is connected in series with a fourteenth diode D14 in the forward direction, a cathode of the fourteenth diode D14 is connected in series with a twenty-fifth resistor R25, a twenty-fifth resistor R25 is connected to the first fuse FR1, and two ends of the twenty-fifth resistor R25 are connected in parallel with an eighteenth capacitor C18; a third pin of the first chip IC1 is connected with a receiving side of a third optical coupler IC3, an emitter of the third optical coupler IC3 is grounded, two ends of the third optical coupler IC3 are connected with a third voltage regulator tube ZD3 in parallel, two ends of the third optical coupler IC3 are connected with a twenty-ninth resistor R29 in parallel, and two ends of the third optical coupler IC3 are connected with a twenty-second capacitor C22 in parallel;

referring to fig. 5, an eighteenth diode D18 is connected in series in the forward direction at the seventh terminal of the second transformer T2, a twenty-seventh electrolytic capacitor C27 is connected between the cathode of the eighteenth diode D18 and the eighth terminal of the second transformer T2, a forty-fourth resistor R40 is connected in parallel at two ends of the twenty-seventh electrolytic capacitor C27, a forty-first resistor R41 is connected in parallel at two ends of the forty-fourth resistor R40, a forty-second resistor R42 is connected to the cathode of the eighteenth diode D18, a forty-second resistor R42 is connected in series with the emitting side of the third optocoupler IC3, a sixth zener diode IC6 is connected in series in the reverse direction at the cathode of the third optocoupler IC3, the sixth zener diode IC6 is grounded, and one end of the forty-third resistor R43 is connected with the sixth zener diode IC 6; a cathode of the eighteenth diode D18 is connected with a forty-fourth resistor R44, a forty-fourth resistor R44 is connected in series with a forty-fifth resistor R45 and then grounded, and a twenty-ninth capacitor C29 is connected in series between a cathode of the third optocoupler IC3 and the forty-fourth resistor R44;

referring to fig. 5, a cathode of the eighteenth diode D18 is electrically connected to a fifth inductor L5, one end of the fifth inductor L5 is grounded through a forty-sixth resistor R46, one end of the fifth inductor L5 is grounded through a forty-seventh resistor R47, one end of the fifth inductor L5 is connected to a receiving side of the first dodeca-opto-coupler C12 through a seventy-first resistor R71, a cathode of the first dodeca-opto-coupler C12 is connected to an NPN-type twenty-fifth triode Q25, an emitter of the twenty-fifth triode Q25 is grounded, a base of the twenty-fifth triode Q25 is grounded through a seventy-second resistor R72, a base of the twenty-fifth triode Q25 is connected to a 24VB through a thirty-third resistor R130 and an eleventh voltage-stabilizing diode ZD11, two ends of the twelfth resistor R72 are connected in parallel to a seventy-fourth capacitor C74, one end of the fifth inductor L5 is grounded through a forty-eighth resistor R5, and a ninth resistor ZD 5857324R 57323, one end of a fifth inductor L5 is grounded through a twenty-eighth capacitor C28, one end of a fifth inductor L5 is connected with a nineteenth diode D19 in series in the forward direction, the cathode of the nineteenth diode D19 is connected with a 5VSB terminal, the cathode of the nineteenth diode D19 is grounded through a thirty-sixth capacitor C30, and the cathode of the nineteenth diode D19 is grounded through a thirty-eighth capacitor C31.

Referring to fig. 6, the PFC main circuit unit 2 is electrically connected with a PFC small card control unit 5 for detecting an output voltage of the voltage dropping unit 3.

Referring to fig. 6, the PFC smart card control unit 5 includes a first chip 1IC1, a first resistor 1R1 and a first electrolytic capacitor 1C1 are sequentially connected in series to a first pin of a first chip 1IC1 of a model CM6500, a seventh pin of the first chip 1IC1 is connected to a first electrolytic capacitor 1C1 through a seventeenth resistor 1R17, a seventh pin of the first chip 1IC1 is connected to a seventh electrolytic capacitor 1C7, a third electrolytic capacitor 1C3, a thirteenth resistor 1R13, a twelfth resistor 1R12 and an eleventh resistor 1R11 in series, an eleventh resistor 1R11 is connected to a VCA terminal, a sixth pin of the first chip 1IC1 is connected to the first electrolytic capacitor 1C1 through a nineteenth capacitor 1R19, a sixth pin of the first chip 1IC1 is connected to a third electrolytic capacitor 1C 6324 through an eighteenth resistor 6324, and a fourth pin of the first chip 1IC 599 is connected to a fourth capacitor 591C 599, a fourth pin of the first chip 1IC1 is connected with a third electrolytic capacitor 1C3 through a fifteenth resistor 1R15, and a fourth pin of the first chip 1IC1 is connected with a third electrolytic capacitor 1C3 and a connection node of a thirteenth resistor 1R13 through a fourteenth resistor 1R 14; a third pin of the first chip 1IC1 is connected with a third electrolytic capacitor 1C3 through a first zener diode 1ZD1, a third pin of the first chip 1IC1 is connected with a third electrolytic capacitor 1C3 through a sixth electrolytic capacitor 1C6, and a third pin of the first chip 1IC1 is connected with a connection node of a first resistor R1 and a second resistor R2 through a sixteenth resistor 1R 16; a second pin of the first chip 1IC1 is sequentially connected with a tenth resistor 1R10, a ninth resistor 1R9 and an eighth resistor 1R8, the eighth resistor 1R8 is connected with a VCA terminal, and a second pin of the first chip 1IC1 is connected with a third electrolytic capacitor 1C3 after passing through a fourteenth electrolytic capacitor C14;

referring to fig. 6, a second electrolytic capacitor 1C2 and a thirteenth electrolytic capacitor 1C13 are connected in series to a first pin of the first chip 1IC1, one end of the second electrolytic capacitor 1C2 is connected to the first electrolytic capacitor 1C1, and the thirteenth electrolytic capacitor 1C13 is connected to the third electrolytic capacitor 1C 3;

referring to fig. 6, a fourteenth pin of the first chip 1IC1 is sequentially connected in series with a second resistor 1R2 and an eighth electrolytic capacitor 1C8, the eighth electrolytic capacitor 1C8 is connected with a third electrolytic capacitor 1C3, a fourteenth pin of the first chip 1IC1 is connected with a ninth electrolytic capacitor 1C9, the other end of the ninth electrolytic capacitor 1C9 is connected with a connection node of the eighth electrolytic capacitor 1C8 and the third electrolytic capacitor 1C3, a thirteenth pin of the first chip 1IC1 is connected with the third electrolytic capacitor 1C3 through a twelfth electrolytic capacitor 1C12, a thirteenth pin of the first chip 1IC1 is connected with the third electrolytic capacitor 1C3 through the third resistor 1R3, and a thirteenth pin of the first chip 1IC1 is sequentially connected in series with a twenty-second resistor 1R22, a twenty-first resistor 1R21, a twentieth resistor 1R20, and a twentieth resistor 1R 20; a twelfth pin of the first chip 1IC1 is electrically connected with an emission side of the second optical coupler 1IC2 through a fifth resistor 1R5, a cathode of the second optical coupler 1IC2 is electrically connected with a ninth pin of the first chip 1IC1, an eleventh pin of the first chip 1IC1 is connected with a VCC4 terminal, an eleventh pin of the first chip 1IC1 is connected with a third electrolytic capacitor 1C3 through an eleventh electrolytic capacitor 1C11, an eleventh pin of the first chip 1IC1 is connected with a ninth resistor R9, a tenth pin of the first chip 1IC1 is connected with a base of a third triode Q3 through a fourth resistor 1R4, a fourth resistor 1R4 is connected with a base of a second triode Q2, and an eighth pin of the first chip 1IC1 is connected with a third electrolytic capacitor 1C 3;

referring to fig. 6, a PNP-type thirteenth diode Q10 is connected to the ninth resistor R9, a thirty-fourth resistor 34 is connected between the base and the emitter of the thirteenth diode Q10, the collector of the thirteenth diode Q10 is connected to the receiving side of the second optocoupler 1IC2, and the emitter of the second optocoupler 1IC2 is grounded; the collector of the thirteenth polar tube Q10 is grounded through a sixty-seven electrolytic capacitor C67, the collector of the thirteenth polar tube Q10 is grounded through a seventy-three resistor R73, and the collector of the thirteenth polar tube Q10 is connected with the VCC5 port.

Referring to fig. 7, the collector of the twenty-fifth triode Q25 is electrically connected to the power output feedback voltage stabilizing unit 7 for protecting the normal operation of the circuit.

The implementation principle of the power supply circuit with voltage stabilization control in the embodiment of the application is as follows:

the filtering and rectifying input unit 1 mainly filters interference generated by an input alternating current power grid, prevents damage to a power supply, and also can filter interference generated by the power supply to the power grid, converts alternating current into direct current through rectification to provide power for a later stage, a PFC main loop boosts rectified voltage to stable direct current voltage of a voltage value required by a user through a second triode Q2, a third triode Q3 and a depletion type first MOS transistor Q1 and supplies the stable direct current voltage to a first transformer T1 (in the embodiment, the commercial power is boosted to 380V output), and the voltage reduction unit 3 reduces the high voltage to obtain an output voltage value required by the user (in the embodiment, 5V and 12V voltages are output).

The above embodiments are preferred embodiments of the present application, and the protection scope of the present application is not limited by the above embodiments, so: all equivalent changes made according to the structure, shape and principle of the present application shall be covered by the protection scope of the present application.

Claims

1. A power supply circuit with voltage stabilization control, characterized in that: the voltage-reducing device comprises a filtering and rectifying input unit (1) which is connected with a mains supply and used for rectifying and filtering the mains supply, wherein a PFC main loop unit (2) for boosting the mains supply is coupled with the filtering and rectifying input unit (1), the PFC main loop unit (2) is electrically connected with an SB standby unit (4) for detecting the output voltage of the PFC main loop unit (2), and the PFC main loop unit (2) is also electrically connected with a voltage-reducing unit (3) for reducing the output voltage of the PFC main loop unit (2).

2. The power supply circuit with voltage stabilization control according to claim 1, characterized in that: the filter rectification input unit (1) comprises a first common mode inductor LF1, a second common mode inductor LF2, a third common mode inductor LF3 and a rectifier bridge BD1, wherein the input end of the first common mode inductor LF1 is connected with a voltage dependent resistor VD1 in parallel, and two input ends of the first common mode inductor LF1 are respectively connected with a first fuse F1 and a second fuse F2; the output end of the first common mode inductor LF1 is further connected in parallel with a first capacitor CY1, the first capacitor CY1 is connected in series with a second capacitor CY2, the connection node of the first capacitor CY1 and the second capacitor CY2 is grounded, a first thermistor TH1 is connected between the input end of the second common mode inductor LF2 and the output end of the first common mode inductor LF1, a first electrolytic capacitor CX1 is connected between the two input ends of the second common mode inductor LF2, a first resistor RX1 and a fourth resistor RX4 are further connected in series between the two input ends of the second common mode inductor LF2 in sequence, a third capacitor CY3 and a fourth capacitor CY4 are connected between the two output ends of the second common mode inductor LF2 in sequence, the connection node of the third capacitor CY3 and the fourth capacitor CY4 is grounded, a fourth resistor RX 23, a fourth resistor RX3, a fourth resistor RX 58573 57324 and a fourth resistor RX 58573 are connected between the two output ends of the second common mode inductor LF 5 in sequence, the third common mode inductor LF3 is coupled to the output end of the second common mode inductor LF2, the rectifier bridge BD1 is coupled to the output end of the third common mode inductor LF3, the negative pole of the rectifier bridge BD1 is connected to the PFC main loop unit (2), and the positive pole of the rectifier bridge BD1 is connected to the VAC terminal.

3. The power supply circuit with voltage stabilization control according to claim 2, characterized in that: the PFC main loop unit (2) comprises an NPN type second triode Q2, a PNP type third triode QW3, a depletion type first MOS tube Q1, a sixth electrolytic capacitor C6 and a seventh electrolytic capacitor C7 are sequentially connected in series between the drain and the source of the depletion type first MOS tube Q1, the source of the depletion type first MOS tube Q1 is grounded, the gate of the depletion type first MOS tube Q1 is electrically connected with the emitter of a third triode Q3, the gate of the depletion type first MOS tube Q1 is grounded through a third resistor R3, the gate of the depletion type first MOS tube Q1 is electrically connected with the emitter of a second triode Q2 through a fourth resistor R4, the collector of the third triode Q3 is grounded, the base of the third triode Q3 is connected with the base of the second triode Q2, the emitter of the second triode Q2 is connected with a fourth resistor R4, the collector of the second triode Q2 is grounded through a fourth electrolytic capacitor C4, and the second triode Q2 is grounded through a fifth electrolytic capacitor C5;

the PFC main loop unit (2) further comprises a first capacitor C1 connected in parallel at two ends of a rectifier bridge BD1, a first inductor L1 is connected with the anode of the rectifier bridge BD1 in series, a twelfth diode D12 is electrically connected between the anode of the rectifier bridge BD1 and the first inductor L1 in the forward direction, an eleventh diode D11 is connected in series with the anode of the twelfth diode D12 in the forward direction, the cathode of an eleventh diode D11 is connected with the second capacitor C2 and then grounded, the cathode of a twelfth diode D12 is connected with a VSB port, a first diode D1 is connected with the first inductor L1 in the forward direction, the cathode of the first diode D1 is connected with the VDC port, a second diode D2 is connected with the first diode D1 in the forward direction in parallel, the drain of a depletion type first MOS transistor Q1 is electrically connected with the connection node of the first diode D1 and the second diode D2, and the cathode of an eleventh diode D11 is electrically connected with the connection node of the first diode D1 and the second diode D2; the first diode D1 is connected with the voltage reduction unit (3) after passing through a third fuse F3;

the cathode of the rectifier bridge BD1 is connected to the second capacitor C2 through the second resistor R2, and the second resistor R2 is connected to the cathode of the twelfth diode D12 through the seventeenth capacitor C17.

4. The power supply circuit with voltage stabilization control according to claim 3, characterized in that: the voltage reduction unit (3) comprises a depletion type sixth MOS tube Q6 and a depletion type fifth MOS tube Q5, the drain of the depletion type sixth MOS tube Q6 is connected with a VDC port through a third fuse F3, the grid of the depletion type sixth MOS tube Q6 is connected with a MOSG1 pin of a PWM control chip through a twelfth resistor R12, the two ends of the twelfth resistor R12 are connected with a fourth diode D4 in a forward parallel mode, a thirteenth resistor R13 is connected between the grid and the source of the depletion type sixth MOS tube Q6 in a serial mode, the source of the depletion type sixth MOS tube Q6 is electrically connected with the drain of the depletion type fifth MOS tube Q5, the grid of the depletion type fifth MOS tube Q5 is connected with the MOSG2 pin of the PWM control chip through a fourteenth resistor R14, the two ends of the fourteenth resistor Q14 are connected with a third diode D3 in a forward parallel mode, the grid of the depletion type fifth MOS tube Q5 is connected with the source of the depletion type fifth MOS tube Q58R 585 in a serial mode, and the source of the depletion type fifth MOS tube Q15 is connected with a fifteenth MOS control chip through a PWM control chip VVC 15C capacitor;

the voltage reduction unit (3) further comprises a ninth diode group D9, the ninth diode group D9 is respectively connected with the fifth diode group D5 and the sixth diode group D6, one anode of the ninth diode group D9 is connected with a 24VB port, and the other anode pin of the ninth diode group D9 is electrically connected with a GND1 pin of the PWM control chip after passing through a twenty-first resistor R21; a cathode of the ninth diode group D9 is connected with a third inductor L3, one end of a third inductor L3 is electrically connected with a GND1 pin of the PWM control chip after passing through a thirteenth capacitor C13, one end of a third inductor L3 is electrically connected with a GND2 pin of the PWM control chip after passing through a fourteenth capacitor C14, an eighteenth resistor R18 is connected in series between the twenty-first resistor R21 and the thirteenth capacitor C13, a nineteenth resistor R19 is connected in series between the twenty-first resistor R21 and the thirteenth capacitor C13, a twentieth resistor R20 is connected in series between the twenty-first resistor R21 and the thirteenth capacitor C13, one end of the eighteenth resistor R18 is connected at a connection node between the third inductor L3 and the ninth diode group D9, and a 24V port is arranged at a connection node between the third inductor L3 and the ninth diode group D9 to output 24V voltage;

5. The power supply circuit with voltage regulation control according to claim 4, characterized in that: the SB standby unit (4) comprises a second transformer T2, a first terminal of a second transformer T2 is connected with a VSB port, a second terminal of a second transformer T2 is connected with a sixth pin of a first chip IC1 with the model of FSL-126HR, a third terminal of the second transformer T2 is connected with a fifteenth diode D15 in series in the positive direction, a fifteenth diode D15 is grounded after passing through a nineteenth electrolytic capacitor C19, the cathode of the fifteenth diode D15 is connected with an NPN-type thirteenth triode Q13, the base of a thirteenth triode Q13 is connected with a fourth zener diode DZ4 and then grounded, two ends of the fourth zener diode DZ4 are connected with a seventy-two capacitor C72 in parallel, the collector of the thirteenth triode Q13 is connected with the collector of an NPN-type twenty-fourth triode Q24 through a fifth resistor R5, the emitter of the twenty-fourth triode Q24 is grounded, the base of the twenty-fourth triode Q24 is grounded through a tenth resistor R10, two ends of the tenth resistor R10 are connected with a seventy-three capacitor C73 in parallel, a sixteenth diode D16, a twenty-eight resistor R28 and a second voltage stabilizing diode ZD2 are sequentially connected with a fourth terminal of the second transformer T2 in series, the second voltage stabilizing diode ZD2 is grounded, and a thirty-third resistor R30 of the second transformer T2 is grounded; a base electrode of the twenty-fourth triode Q24 is connected with a receiving side of a twelfth optocoupler C12, an emitter electrode of the twelfth optocoupler C12 is connected with a tenth resistor R10, and a collector electrode of the twelfth optocoupler C12 is connected with a ninth resistor R9;

6. The power supply circuit with voltage regulation control according to claim 5, characterized in that: the PFC main loop unit (2) is electrically connected with a PFC small card control unit (5) used for detecting the output voltage of the voltage reduction unit (3).

7. The power supply circuit with voltage regulation control according to claim 6, characterized in that: the PFC small card control unit (5) comprises a first chip 1IC1, a first resistor 1R1 and a first electrolytic capacitor 1C1 are sequentially connected in series with a first pin of a first chip 1IC1 with the model number CM6500, a seventh pin of the first chip 1IC1 is connected with the first electrolytic capacitor 1C1 through a seventeenth resistor 1R17, a seventh pin of the first chip 1IC1 is connected with a seventh electrolytic capacitor 1C7, a third electrolytic capacitor 1C3, a thirteenth resistor 1R13, a twelfth resistor 1R12 and an eleventh resistor 1R11 in series, the eleventh resistor 1R11 is connected with a VCA terminal, a sixth pin of the first chip 1IC1 is connected with the first electrolytic capacitor 1C1 through a nineteenth capacitor 1R19, a sixth pin of the first chip 1IC1 is connected with a third electrolytic capacitor 1C 6324 through an eighteenth resistor 631R 18, a fourth pin of the first chip 1IC 589 is connected with a fourth capacitor 591C 599, a fourth pin of the first chip 1IC1 is connected with a third electrolytic capacitor 1C3 through a fifteenth resistor 1R15, and a fourth pin of the first chip 1IC1 is connected with a third electrolytic capacitor 1C3 and a connection node of a thirteenth resistor 1R13 through a fourteenth resistor 1R 14; a third pin of the first chip 1IC1 is connected with a third electrolytic capacitor 1C3 through a first zener diode 1ZD1, a third pin of the first chip 1IC1 is connected with a third electrolytic capacitor 1C3 through a sixth electrolytic capacitor 1C6, and a third pin of the first chip 1IC1 is connected with a connection node of a first resistor R1 and a second resistor R2 through a sixteenth resistor 1R 16; a second pin of the first chip 1IC1 is sequentially connected with a tenth resistor 1R10, a ninth resistor 1R9 and an eighth resistor 1R8, the eighth resistor 1R8 is connected with a VCA terminal, and a second pin of the first chip 1IC1 is connected with a third electrolytic capacitor 1C3 after passing through a fourteenth electrolytic capacitor C14;

8. The power supply circuit with voltage stabilization control according to claim 2, characterized in that: two ends of the first thermistor TH1 are connected with a relay (6) for controlling the on-off of the first thermistor TH 1.