CN213960195U - Pixel merging circuit based on composite dielectric gate double-transistor photosensitive detector - Google Patents
Pixel merging circuit based on composite dielectric gate double-transistor photosensitive detector Download PDFInfo
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- CN213960195U CN213960195U CN202023340957.0U CN202023340957U CN213960195U CN 213960195 U CN213960195 U CN 213960195U CN 202023340957 U CN202023340957 U CN 202023340957U CN 213960195 U CN213960195 U CN 213960195U
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Abstract
The utility model relates to a pixel merging circuit based on a composite dielectric grid double-transistor photosensitive detector, which comprises a transistor array formed by a plurality of composite dielectric grid double-transistors, wherein the front end of the transistor array is provided with a word line gating module, and the rear end of the transistor array is provided with a bit line gating module, a current-voltage conversion module and an analog-to-digital conversion module; the transistor array is connected with the grids of all the transistors in the row to form a word line and is controlled by a word line gating module; the transistor array is connected with drain terminals of all transistors in the same column to form a bit line and is controlled by a bit line gating module; the source ends of all the transistors in the transistor array and the column are connected to form a source line; the output end of the bit line gating module is connected with the input end of the current-voltage conversion module, and the output end of the current-voltage conversion module is connected with the input end of the analog-to-digital conversion module. The utility model discloses can realize the amalgamation with the individual pixel of mxn, the SNR promotes to original mxn times.
Description
Technical Field
The utility model relates to a pixel merging circuit based on photosensitive detector of compound dielectric grid double transistor belongs to power inverter circuit technical field, can be used to.
Background
CCD and CMOS-APS, the two most common imaging devices at present, both have their own limitations. Due to the complex control time sequence and voltage requirements of the CCD, the working speed is low, and the integration is not easy; the CMOS-APS adopts a photosensitive diode and has a complex structure, so that the filling coefficient is low and the full-well charge is small.
The chinese patent of invention with publication number CN 102938409B proposes a two-transistor photosensitive detector, which is characterized in that a single semiconductor device can implement complete functions of resetting, sensing and reading, thereby forming a complete pixel, and greatly improving the fill factor of the pixel. The composite dielectric gate double-transistor photosensitive detector is used as a new generation of imaging device, has higher working speed, larger filling coefficient and more full-well charges, can be integrated with a CMOS (complementary metal oxide semiconductor) process, and has inherent advantages compared with a CCD (charge coupled device) and a CMOS-APS (complementary metal oxide semiconductor-active plate). In addition, in view of the fact that in some application scenarios, the image does not need to have excessively high resolution, but focuses more on rapidly reading out the image to obtain the overall appearance characteristics of the scene, the pixel combination technology has been widely used in CCD and CMOS-APS, but there is no research on the pixel combination technology of the composite dielectric gate two-transistor photosensitive detector.
SUMMERY OF THE UTILITY MODEL
An object of the utility model is to provide a pixel merging circuits based on compound dielectric grid phototransistor photosensitive detector can realize the pixel merging function, and improves the frame frequency and the SNR that read out.
The utility model discloses a pixel merging circuit based on photosensitive detector of compound dielectric grid two transistors, including the transistor array that a plurality of compound dielectric grid two transistors constitute, the front end of transistor array is equipped with word line gating module, the rear end of transistor array is equipped with bit line gating module, current-voltage conversion module and analog-to-digital conversion module; the transistor array is connected with the gates of all the transistors in the row to form a word line and is controlled by the word line gating module; the transistor array is connected with drain terminals of all transistors in the same column to form a bit line and is controlled by the bit line gating module; the source ends of all the transistors in the transistor array and the column are connected to form a source line; the output end of the bit line gating module is connected with the input end of the current-voltage conversion module, and the output end of the current-voltage conversion module is connected with the input end of the analog-to-digital conversion module.
Furthermore, the word line gating module comprises a word line multi-selection multi-decoder and word line level conversion circuits, wherein each word line level conversion circuit corresponds to a word line of the transistor array one by one, the output end of each word line level conversion circuit is connected with each grid of the corresponding word line, and the input end of each word line level conversion circuit is connected with one output end of the word line multi-selection multi-decoder.
Furthermore, a clock signal input end of the word line multi-selection multi-decoder is connected with a word line time sequence signal output end of the digital signal module, an address signal input end of the word line multi-selection multi-decoder is connected with a word line address signal output end of the digital signal module, a composite dielectric gate double-transistor photosensitive detector array is provided with a single word line gating module, and only one word line multi-selection multi-decoder is arranged in one word line gating module.
Furthermore, the bit line gating module is a multi-input and single-output module and comprises a bit line multi-selection multi-decoder and a bit line switch circuit, wherein the input end of the bit line switch circuit is correspondingly connected with the output end of the bit line multi-selection multi-decoder, and the output end of the bit line switch circuit is used as the output end of the bit line gating module.
Furthermore, a clock signal input end of the bit line multi-selection multi-decoder is connected with a bit line timing signal output end of the digital signal module, and an address signal input end of the bit line multi-selection multi-decoder is connected with a bit line address signal output end of the digital signal module.
Furthermore, a unique bit line multi-selection multi-decoder is arranged in one bit line gating module, and bit lines of the composite dielectric gate double transistor arrays correspond to one bit line gating module.
Furthermore, the current-voltage conversion module is a current-voltage conversion amplifier with a voltage clamping function.
The technical effects of the utility model:
1. the circuit can realize the function of quantizing and reading after adding signal currents of multiple pixels, the function improves the signal-to-noise ratio of an image while improving the array reading frame rate, and if the reading current signal, the circuit noise and the signal-to-noise ratio of a single pixel are I respectively0、N0And SNR0Then, the signal and noise after the m pixels are combined are:
the signal-to-noise ratio is:
wherein SNR isTOTFor the combined signal-to-noise ratio, Y is the coefficient, ITOTIs the sum of the current signals, NTOTIs the sum of the circuit noise;
for the noise of the readout circuit, the signal-to-noise ratio is raised to m times compared with the single-pixel readout mode, and m is an integer larger than 1.
2. In the read mode, if WL1, WL2 and BL1, BL2 are gated under logic control, the read-out tubes of the four pixels located at the upper left corner of the array will be turned on simultaneously, and the total signal current entering the current-voltage conversion module through the bit line gating module is the sum of the signal currents of the four pixels, i.e. ITOT＝I1，1+I1，2+I2，1+I2，2. The pixel combination function is realized, and if m rows of adjacent word lines exist in the same reading period, n columns of bit lines sharing the same bit line gating module are selected, the combination of m multiplied by n pixels can be realized, and the signal to noise ratio is improved to the original m multiplied by n times.
3. The multi-selection multi-decoder can realize the functions of one-out-of-multiple, two-out-of-multiple or four-out-of-multiple according to different modes. The one-out-of-multiple mode is that when the address signal of the decoder is given, only one path of signal at the output end is 1, the two-out-of-multiple mode is that for the given address signal, two paths of signals at the output end are 1, the two paths of signals are adjacent, and the four-out-of-multiple mode function is that four continuous lines of word lines are selected at the output end similarly. The output end of the decoder is still a digital logic signal and corresponds to the input end of each level conversion circuit. The level conversion circuit has the function of converting the digital signals into analog levels, and when the input of the level conversion circuit is 0, the corresponding output voltage is 0V; when the input of the level shift circuit is 1, the corresponding output voltage is 5V. The output voltage of the level conversion circuit is connected to the corresponding pixel array word line to determine whether the readout tube of the pixel can be turned on.
4. The input end of the current-voltage conversion module is the input stage of an amplifier, and the voltage of the bit line can be clamped at the reference voltage by adding the required reference voltage to the other input end of the amplifier according to the virtual short of the amplifier. The control mode signal can change the resistance value of the feedback resistor of the module, and the current is converted into voltage with different gains. The analog-to-digital conversion circuit can adopt a standard ADC module.
Drawings
FIG. 1 is a schematic diagram of the connection mode of each port in the array of the composite dielectric gate two-transistor photosensitive detector of the present invention,
FIG. 2 is a system diagram of the pixel array and pixel merging circuit of the composite dielectric gate dual transistor photosensitive detector of the present invention,
figure 3 is a block diagram of the structure of a word line gating module,
FIG. 4 is a block diagram of a bit line strobe block.
Detailed Description
The present invention will now be described in further detail with reference to the accompanying drawings. These drawings are simplified schematic drawings and illustrate the basic structure of the present invention only in a schematic manner, and thus show only the components related to the present invention.
As shown in fig. 1 and fig. 2, the pixel merging circuit based on the composite dielectric gate double-transistor photosensitive detector of the present invention includes a transistor array formed by a plurality of composite dielectric gate double-transistors, a word line gating module is arranged at the front end of the transistor array, and a bit line gating module, a current-voltage conversion module and an analog-to-digital conversion module are arranged at the rear end of the transistor array; the transistor array is connected with the grids of all the transistors in the row to form a word line and is controlled by a word line gating module; the transistor array is connected with drain terminals of all transistors in the same column to form a bit line and is controlled by a bit line gating module; the source ends of all the transistors in the transistor array and the column are connected to form a source line; the output end of the bit line gating module is connected with the input end of the current-voltage conversion module, and the output end of the current-voltage conversion module is connected with the input end of the analog-to-digital conversion module.
As shown in fig. 3, the word line gating module includes a word line multi-selection decoder and word line level shift circuits, wherein each word line level shift circuit corresponds to a word line of the transistor array one by one, an output terminal of each word line level shift circuit is connected to each gate of the corresponding word line, and an input terminal of each word line level shift circuit is connected to one output terminal of the word line multi-selection decoder.
The composite dielectric gate double-transistor photosensitive detector array is provided with a single word line gating module, and only one word line multi-selection multi-decoder is arranged in one word line gating module.
As shown in fig. 4, the bit line gating module is a multi-input and single-output module, and includes a bit line multi-selection multi-decoder and a bit line switch circuit, wherein the input end of the bit line switch circuit is correspondingly connected to the output end of the bit line multi-selection multi-decoder, and the output end of the bit line switch circuit is used as the output end of the bit line gating module.
The clock signal input end of the bit line multi-selection multi-decoder is connected with the bit line timing signal output end of the digital signal module, and the address signal input end of the bit line multi-selection multi-decoder is connected with the bit line address signal output end of the digital signal module.
A single bit line multi-selection multi-decoder is arranged in one bit line gating module, and bit lines of a plurality of composite dielectric gate double transistor arrays correspond to one bit line gating module.
The current-voltage conversion module is a current-voltage conversion amplifier with a voltage clamping function.
The circuit can realize the function of quantizing and reading after adding signal currents of multiple pixels, the function improves the signal-to-noise ratio of an image while improving the array reading frame rate, and if the read current signals of single pixels, circuit noise and signal-to-noise ratio componentsIs other than I0、N0And SNR0Then, the signal and noise after the m pixels are combined are:
the signal-to-noise ratio is:
wherein SNR isTOTFor the combined signal-to-noise ratio, Y is the coefficient, ITOTIs the sum of the current signals, NTOTIs the sum of the circuit noise;
for the noise of the readout circuit, the signal-to-noise ratio is raised to m times compared with the single-pixel readout mode, and m is an integer larger than 1.
In the read mode, if WL1, WL2 and BL1, BL2 are gated under logic control, the read-out tubes of the four pixels located at the upper left corner of the array will be turned on simultaneously, and the total signal current entering the current-voltage conversion module through the bit line gating module is the sum of the signal currents of the four pixels, i.e. ITOT＝I1，1+I1，2+I2，1+I2，2. The pixel combination function is realized, and if m rows of adjacent word lines exist in the same reading period, n columns of bit lines sharing the same bit line gating module are selected, the combination of m multiplied by n pixels can be realized, and the signal to noise ratio is improved to the original m multiplied by n times.
The multi-selection multi-decoder can realize the functions of one-out-of-multiple, two-out-of-multiple or four-out-of-multiple according to different modes. The one-out-of-multiple mode is that when the address signal of the decoder is given, only one path of signal at the output end is 1, the two-out-of-multiple mode is that for the given address signal, two paths of signals at the output end are 1, the two paths of signals are adjacent, and the four-out-of-multiple mode function is that four continuous lines of word lines are selected at the output end similarly. The output end of the decoder is still a digital logic signal and corresponds to the input end of each level conversion circuit. The level conversion circuit has the function of converting the digital signals into analog levels, and when the input voltage of the level conversion circuit is 0, the corresponding output voltage is 0V; when the input of the level shift circuit is 1, the corresponding output voltage is 5V. The output voltage of the level conversion circuit is connected to the corresponding pixel array word line to determine whether the readout tube of the pixel can be turned on.
The input end of the current-voltage conversion module is the input stage of an amplifier, and the voltage of the bit line can be clamped at the reference voltage by adding the required reference voltage to the other input end of the amplifier according to the virtual short of the amplifier. The control mode signal can change the resistance value of the feedback resistor of the module, and the current is converted into voltage with different gains. The analog-to-digital conversion circuit may employ standard ADC modules.
In light of the foregoing, it will be apparent to those skilled in the art from this disclosure that various changes and modifications can be made without departing from the spirit and scope of the invention. The technical scope of the present invention is not limited to the content of the specification, and must be determined according to the scope of the claims.
Claims (7)
1. A pixel merging circuit based on a composite dielectric gate double-transistor photosensitive detector comprises a transistor array formed by a plurality of composite dielectric gate double transistors, and is characterized in that: the front end of the transistor array is provided with a word line gating module, and the rear end of the transistor array is provided with a bit line gating module, a current-voltage conversion module and an analog-digital conversion module; the transistor array is connected with the gates of all the transistors in the row to form a word line and is controlled by the word line gating module; the transistor array is connected with drain terminals of all transistors in the same column to form a bit line and is controlled by the bit line gating module; the source ends of all the transistors in the transistor array and the column are connected to form a source line; the output end of the bit line gating module is connected with the input end of the current-voltage conversion module, and the output end of the current-voltage conversion module is connected with the input end of the analog-to-digital conversion module.
2. The pixel merging circuit based on the composite dielectric gate two-transistor photosensitive detector as claimed in claim 1, wherein: the word line gating module comprises a word line multi-selection decoder and word line level conversion circuits, wherein each word line level conversion circuit corresponds to a word line of the transistor array one by one, the output end of each word line level conversion circuit is connected with each grid of the corresponding word line, and the input end of each word line level conversion circuit is connected with one output end of the word line multi-selection decoder.
3. The pixel merging circuit based on the composite dielectric gate two-transistor photosensitive detector as claimed in claim 2, wherein: the word line multi-selection multi-decoder comprises a word line multi-selection multi-decoder, a word line time sequence signal output end, a word line address signal input end, a composite dielectric gate double-transistor photosensitive detector array and a word line gating module, wherein the word line multi-selection multi-decoder is connected with the clock signal input end of the word line multi-selection multi-decoder and the word line time sequence signal output end of the digital signal module, the word line multi-selection multi-decoder is connected with the word line address signal output end of the digital signal module, the composite dielectric gate double-transistor photosensitive detector array is provided with the single word line gating module, and only one word line multi-selection multi-decoder is arranged in the word line gating module.
4. The pixel merging circuit based on the composite dielectric gate two-transistor photosensitive detector as claimed in claim 1, wherein: the bit line gating module is a multi-input and single-output module and comprises a bit line multi-selection multi-decoder and a bit line switch circuit, wherein the input end of the bit line switch circuit is correspondingly connected with the output end of the bit line multi-selection multi-decoder, and the output end of the bit line switch circuit is used as the output end of the bit line gating module.
5. The pixel merging circuit based on the composite dielectric gate two-transistor photosensitive detector, according to claim 4, is characterized in that: the clock signal input end of the bit line multi-selection multi-decoder is connected with the bit line timing signal output end of the digital signal module, and the address signal input end of the bit line multi-selection multi-decoder is connected with the bit line address signal output end of the digital signal module.
6. The pixel merging circuit based on the composite dielectric gate two-transistor photosensitive detector, according to claim 4, is characterized in that: a single bit line multi-selection multi-decoder is arranged in one bit line gating module, and bit lines of a plurality of composite dielectric gate double transistor arrays correspond to one bit line gating module.
7. The pixel merging circuit based on the composite dielectric gate two-transistor photosensitive detector, according to any one of claims 1 to 6, wherein: the current-voltage conversion module is a current-voltage conversion amplifier with a voltage clamping function.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN114071041A (en) * | 2021-11-10 | 2022-02-18 | 南京大学 | Line-column subtraction reading circuit based on composite dielectric gate double-transistor photosensitive detector |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN114071041A (en) * | 2021-11-10 | 2022-02-18 | 南京大学 | Line-column subtraction reading circuit based on composite dielectric gate double-transistor photosensitive detector |
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Effective date of registration: 20220623 Address after: Room 801, building 9, No.100 Tianjiao Road, Qilin hi tech Industrial Development Zone, Jiangning District, Nanjing City, Jiangsu Province, 211100 Patentee after: Nanjing Weipaishi Semiconductor Technology Co.,Ltd. Patentee after: Nanjing University Address before: Room 801, building 9, No.100 Tianjiao Road, Qilin hi tech Industrial Development Zone, Jiangning District, Nanjing City, Jiangsu Province, 211100 Patentee before: Nanjing Weipaishi Semiconductor Technology Co.,Ltd. |