JP2002094882A - Mos solid-state image pickup device and method for driving the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a solid-state image pickup device capable of acquiring only the movement information of picture data without making it unnecessary to provide a digital converting circuit such as an A/D converting circuit or memory circuit for temporarily preserving picture data at the time of processing the picture data irradiated by photoelectric converting elements. SOLUTION: This solid-state image pickup device 11 is constituted of a photoelectric conversion cell array 13 in which plural photoelectric conversion cells 31 are arrayed in matrix, a horizontal selecting circuit 15 and a vertical selecting circuit 19 connected to the photoelectric conversion cell array 13, a control circuit 21, and an output amplifier 23 connected to the horizontal selecting circuit 15. In this solid-state image pickup device 11, the respective photoelectric conversion cells 31 are constituted so that picture data in the first frame and picture data in the second frame can be temporarily stored, and that both picture data can be outputted according to a prescribed control signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state image pickup device and a method of driving the same, and more particularly, to a MOS type device having a circuit configuration of photoelectric conversion cells arranged in a matrix and a readout method. The present invention relates to a solid-state imaging device, particularly a MOS-type solid-state imaging device suitable for easily acquiring movement information of a subject, and a driving method thereof.

[0002]

2. Description of the Related Art Conventionally, a MOS type solid-state imaging device has been generally used as a method for obtaining movement information of a subject.

FIG. 4 is a circuit diagram of a conventional MOS type solid-state imaging device. FIG. 5 is a diagram showing a configuration of photoelectric conversion cells arranged in a matrix of the MOS solid-state imaging device shown in FIG. 4. FIG. 6 is a diagram showing image data irradiated to the MOS solid-state imaging device shown in FIG. FIG. 7 is a system block diagram for reading out image data applied to the MOS solid-state imaging device in FIG. 4 and obtaining movement information of a subject.

First, the configuration of a conventional MOS type solid-state imaging device will be described with reference to FIG.

[0005] The MOS type solid-state imaging device 111 has a photoelectric conversion cell array 113 arranged in a matrix and a photoelectric conversion cell array 113 arranged in a matrix.
A vertical selection circuit 119 connected to the photoelectric conversion cell array 113 to select the row direction of the pixel, a horizontal selection circuit 115 connected to the photoelectric conversion cell array 113 to select output data from the photoelectric conversion cell array 113, Load circuit 200 connected to photoelectric conversion cell array 113 to read data from conversion cell array 113
And a control circuit 121 and an output amplifier 123 for controlling the MOS-type solid-state imaging device 111.
5 and the vertical selection circuit 119 and the photoelectric conversion cell array 113. The horizontal selection circuit 115 is connected to the output amplifier 123, and the output data from the photoelectric conversion cell array 113 is sequentially output from the output terminal 125.

Incidentally, the load circuit 200 according to the present invention.
Includes a resistor array connected to an end of a signal line for each column in the photoelectric conversion cell array.

Next, the configuration of the photoelectric conversion cell 131 constituting the photoelectric conversion cell array 113 will be described with reference to FIG.

The drain terminal of the reset MOS transistor 133 is commonly connected to all the photoelectric conversion cells 131 as a reset voltage terminal 135, and the gate terminal of the reset MOS transistor 133 is a reset signal terminal 13.
7 is commonly connected to all the photoelectric conversion cells 131. The source terminal of the reset MOS transistor 133 is connected to the cathode terminal of the photodiode 139 serving as a photoelectric conversion element, one end of the first parasitic capacitance 141, and the source of the shutter MOS transistor 143.

The gate terminal of the shutter MOS transistor 143 is commonly connected to all the photoelectric conversion cells 131 as a shutter signal terminal 145, and the shutter MO
The drain of the S transistor 143 is connected to the second parasitic capacitance 14.
7 is connected to the gate terminal of the amplifier MOS transistor 149.

The drain of the amplifier MOS transistor 149 is connected to the source of the selection MOS transistor 151, and the drain of the selection MOS transistor 151 is common to the columns of the photoelectric conversion cells 131 arranged in a matrix as the data output terminal 157. And to the load circuit 200 and the horizontal selection circuit 115.

The gate of the selection MOS transistor 151 is commonly connected as a vertical selection terminal 153 for each row of the photoelectric conversion cells 131 arranged in a matrix, and is connected to the vertical selection circuit 119. Also reset MOS
The bulk of the transistor 133, the bulk of the MOS transistor for shutter 143, the bulk of the MOS transistor for amplifier 149, and the bulk of the selection MOS transistor
1, the other terminal of the first parasitic capacitance 141, the other terminal of the second parasitic capacitance 147, and the anode terminal of the photodiode 139 are all commonly connected to the ground terminal 155.

Next, referring to FIG. 4, FIG. 5, and FIG.
An operation of reading image data of a subject irradiated on the S-type solid-state imaging device will be described.

FIG. 6 shows the timing at which the image data of the N frame 171 is fetched. First, reset time 173 is applied to reset signal terminals 137 of all photoelectric conversion cells 131.
, And the shutter signal 163 of the shutter time 175 is input to the shutter signal terminals 145 of all the photoelectric conversion cells 131.

By this operation, all the photoelectric conversion cells 131
The first parasitic capacitance 141 and the second parasitic capacitance 1
47 is in a reset state. And reset time 173
The image data illuminated on each photodiode 139, which is the light receiving section of each photoelectric conversion cell 131, during the period from the end of the shutter period 175 to the end of the shutter time 175, depends on the amount of incident light. 2 parasitic capacitance 14
7 is stored.

When the shutter time 175 of the shutter signal 163 ends, the shutter MOS transistor 143 turns off, and the image data of the subject is stored in the second parasitic capacitance 147. The upper part of the second parasitic capacitance 147 is shielded from light by aluminum or the like, so that charge as image data does not leak.

The image data stored in the second parasitic capacitance 147 is amplified by the amplifier MOS transistor 149 arranged in each photoelectric conversion cell 131, and is turned on by the selection MOS transistor 151 so as to be applied to the load circuit 200. The voltage can be converted and read as image data.

That is, in order to read the image data stored in each of the second parasitic capacitances 147 arranged in all the photoelectric conversion cells 131, the vertical address signal from the vertical selection circuit 119 after the shutter time 175 ends. 167
Selects the vertical selection terminal 153 in one row of the photoelectric conversion cell array 113, thereby turning on the selection MOS transistor 151 and outputting the voltage-converted image data to the load circuit 200 as the output signal 169 from the data output terminal 157. You.

Further, a certain row of vertical address signals 16
7 is selected, the image data of this row is sequentially sent to the output circuit 123 by the horizontal address signal 165 from the horizontal selection circuit 115, amplified, and output from the output terminal 125.

As described above, by sequentially inputting the vertical address signal and the horizontal address signal to the photoelectric conversion cell array 113, the image data stored in each of the second parasitic capacitances 147 arranged in all the photoelectric conversion cells 131 is converted. It can be obtained as an output signal 169 from the data output terminal 157 sequentially.

According to the above-described driving method, the image data stored in all the photoelectric conversion cells 131 is stored in one frame period 171.
Are output from the MOS-type solid-state imaging device 111.

Although the parasitic capacitance is shown in the circuit configuration of the photoelectric conversion cell of the conventional MOS transistor type solid-state imaging device, the parasitic capacitance does not have a structure as shown in the drawing. Instead, it is considered to be naturally formed between the diffusion layers provided with the parasitic capacitance shown in the figure.

Next, the conventional MOS type solid-state imaging device 11 will be described.
Means for obtaining the movement information of the subject by using 1 will be described with reference to FIG.

In FIG. 7, a MOS type solid-state imaging device 111 is shown.
Is connected to the A / D conversion circuit 181,
The input of the first memory 183 and the input of the second memory 185 are connected to the output of the / D conversion circuit 181. A data comparison circuit 187 is connected to the output of the first memory 183 and the output of the second memory 185.

Next, the operation of this circuit will be described. First, N-frame image data obtained from the MOS solid-state imaging device 111 is digitized by the A / D conversion circuit 181 and is input to the first memory circuit 183 and stored.

Next, the image data of the (N + 1) th frame obtained from the MOS type solid-state image pickup device 111 is digitized by the A / D conversion circuit 181 and the second memory circuit 18
5 is entered and stored.

Then, the N-frame image data and the (N + 1) -frame image data are compared by the data comparison circuit 187 and output from the comparison data output terminal 189. The movement information of the subject can be obtained from the output signal from the comparison data output terminal 189.

[0027]

The conventional MOS-type solid-state imaging device is constructed as described above, reads out the irradiated image data by driving as described above, and outputs the image data to an A / D conversion circuit. And temporarily stored in a memory circuit for each frame.

In order to obtain the movement information of the subject,
The image data of the N frame and the image data of the N + 1 frame are temporarily stored in separate memory circuits, respectively, and then compared to obtain the movement information of the subject.

That is, an A / D conversion circuit and a memory circuit are required in addition to the solid-state imaging device to obtain the movement information of the subject. Further, even if the solid-state imaging device, the A / D conversion circuit, and the memory circuit are integrated into one chip, there is a problem that the chip area is significantly increased, the driving method of each circuit is complicated, and the processing time is long.

Accordingly, an object of the present invention is to provide a solid-state imaging device which can improve the above-mentioned drawbacks of the prior art, is suitable for miniaturization, can easily acquire high-precision object movement information, and has a low manufacturing cost. It is intended to provide a cheap solid-state imaging device.

[0031]

SUMMARY OF THE INVENTION In order to achieve the above-mentioned object, the present invention employs the following technical configuration.

That is, as a first aspect according to the present invention,
A photoelectric conversion cell array in which a plurality of photoelectric conversion cells are arranged in a matrix, and a horizontal selection circuit, a vertical selection circuit, a control circuit, and an output amplifier connected to the horizontal selection circuit connected to the photoelectric conversion cell array. In each solid-state imaging device, each of the photoelectric conversion cells temporarily stores the image data in the first frame and the image data in the second frame, and in accordance with a predetermined control signal. And a solid-state imaging device configured to output both image data. As a second aspect of the present invention, in the above-described solid-state imaging device, in each of the photoelectric conversion cells, M for second shutter
The gate of the OS transistor is turned off, the pixel data of the frame obtained by turning on the first shutter transistor, and the gate of the first shutter MOS transistor are turned off in the next frame, and the second shutter transistor is turned on. Is a driving method of a MOS-type solid-state imaging device configured to always obtain comparison image data with the image data of the previous frame by comparing and reading out pixel data obtained by turning on the data comparison circuit.

[0033]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The solid-state image pickup device and the method for driving the solid-state image pickup device according to the present invention employ the above-mentioned technical configuration. Therefore, each photoelectric conversion cell itself has a pixel in the current frame. A function of holding data and pixel data in the immediately preceding frame is provided, and the respective outputs of the individual photoelectric conversion cells are directly input to an analog comparison circuit, and the pixel in the current frame is input. By comparing the data with the pixel data in the immediately preceding frame, it is possible to obtain the movement information of the subject accurately and reliably, and as a result, it is used in comparison with the conventional solid-state imaging device. Since the amount of memory is greatly reduced and the use of an analog / digital converter is not required, the circuit design is simplified, and the data is simply converted without analog / digital conversion. There is an effect that the analysis accuracy is improved.

Further, according to the present invention, since the circuit design can be simplified and reduced, the manufacturing process can be shortened, and at the same time, it can be manufactured with substantially the same processing configuration. Overall manufacturing costs are also significantly reduced.

[0035]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A specific example of a solid-state imaging device according to the present invention and a driving method thereof will be described in detail with reference to the drawings.

1 and 2 are block diagrams showing the configuration of a specific example of the solid-state imaging device 11 according to the present invention, in which a plurality of photoelectric conversion cells are arranged in a matrix. Photoelectric conversion cell array 13, horizontal selection circuit 1 connected to photoelectric conversion cell array 13
5, in the solid-state imaging device 11 including the vertical selection circuit 19, the control circuit 21, and the output amplifier 23 connected to the horizontal selection circuit 15, the individual photoelectric conversion cells 31 are arranged as shown in FIG. Each is configured to temporarily store the image data in the first frame and the image data in the second frame, and to output both image data in accordance with a predetermined control signal. The solid-state imaging device 11 is shown.

It is desirable that each of the photoelectric conversion cells 31 in this specific example has at least two image data output lines 91 and 93 as shown in FIG.

In this embodiment, the two image data output lines 91 and 93 in each of the photoelectric conversion cells 31 are connected to a plurality of data lines connected to the horizontal selection circuit 15. Preferably, it is connected to one of the comparison circuits 73.

The photoelectric conversion cell 31 of the present invention
Are one photoelectric conversion element 39, one reset means 33 for the photoelectric conversion element 39, a pair of shutter means 43 and 53, which are alternately driven, and a pair of amplification means 4
9 and 59, and a pair of selecting means 51 and 61.

On the other hand, the photoelectric conversion cell 3 of the present invention
1, reset means 33, shutter means 43,
53, amplification means 49, 59 and selection means 51, 61
It is desirable that each of them is constituted by a MOS transistor.

Next, the solid-state imaging device 11 according to the present invention.
A detailed example of a more detailed circuit configuration of the photoelectric conversion cell 31 used in the first embodiment will be described in detail with reference to FIG. 2. If a plurality of photoelectric conversion cells 31 are arranged in a matrix, The cell array 13 and the data comparison circuit 17 and the vertical selection circuit 1
9 is connected to the control circuit 21, the data comparison circuit 17 is connected to the horizontal selection circuit 15, the horizontal selection circuit 15 is connected to the output amplifier 23, and the control circuit 21 is connected to the vertical selection circuit 19 and the data comparison circuit. Solid-state imaging device 11 connected to horizontal selection circuit 15
In the above, each of the individual photoelectric conversion cells 31
The solid-state imaging device 11 is configured to temporarily store the image data in the first frame and the image data in the second frame, and output both image data in accordance with a predetermined control signal. .

Further, in the present invention, each of the photoelectric conversion cells 31 arranged in a matrix includes one photoelectric conversion element 39 and one reset MOS transistor, and one set of shutter MOS transistors. And 1
Set of MOS transistors for amplifier and one set of M for selection
It is also desirable to comprise an OS transistor.

The configuration of the solid-state imaging device 11 according to the present invention using the MOS transistor will be described. The reset signal controlled by a reset signal 37 is connected to the other end of the photoelectric conversion element 39 whose one end is grounded. One end of the MOS transistor 33 and one end of the first MOS transistor for shutter 43 controlled by the shutter signal 45 are connected to each other,
The other end of the S transistor 43 has an appropriate amplifier M
One end is connected to the first image data output line 91 via the OS transistor 49 and the gate is connected to the vertical selection line 6.
3 is connected to the other end of the first selection MOS transistor 51 and the other end of the photoelectric conversion element 39 connected to one end of the reset MOS transistor 33. One end of a second shutter MOS transistor 53 controlled by a signal 55 is connected to the other end of the second shutter MOS transistor 53, and an appropriate amplifier MOS transistor is connected to the other end of the second shutter MOS transistor 53.
A solid state in which one end is connected to the second image data output line 93 via the transistor 59 and the other end of the second selection MOS transistor 61 whose gate is connected to the vertical selection line 63 is connected. Photoelectric conversion cell 3 of imaging device 11
1 is shown.

In the present invention, the photoelectric conversion element 39
Is preferably formed of a photodiode.

The gates of the amplifying MOS transistors 49 and 59 according to the present invention are connected to one end of the first or second shutter MOS transistor, and the source or drain thereof is connected to the first MOS transistor 49 or 59. And one end of the second selection MOS transistor.

It should be noted that, also in the present invention, the first shutter MOS transistor 43 and the first amplification MOS transistor 4 are provided between both terminals of the photoelectric conversion element 39.
9 between the connecting portion with the grounding portion and the second shutter M
Between the ground and the connection between the OS transistor 53 and the second amplifying MOS transistor 59, there is a portion where at least a part of the charge generated by the photoelectric conversion element is accumulated. This is a part which is usually recognized as a parasitic capacitance part in which at least a part of the charge generated by the photoelectric conversion element is stored.

Accordingly, in the specific example shown in FIG. 2 of the photoelectric conversion cell 31 according to the present invention, a specific example of the circuit configuration including the above-mentioned parasitic capacitance is as follows. That is, in the photoelectric conversion cell, the drain of the reset MOS transistor 33 is connected in common to all the photoelectric conversion cells 31 as the reset voltage terminal 35, and the gate of the reset MOS transistor 33 is connected to the reset signal terminal 3
7 is commonly connected to all the photoelectric conversion cells 31.

The reset MOS transistor 33
Are connected to the cathode terminal of the photodiode 39, which is a photoelectric conversion element, one end of the first parasitic capacitance 41, the source of the first MOS transistor for shutter 43, and the source of the second MOS transistor 53 for shutter. are doing.

The gate of the first shutter MOS transistor 43 is commonly connected as a first shutter terminal 45 to all the photoelectric conversion cells 31, and the drain of the first shutter MOS transistor 43 is a second parasitic capacitance. 47 and a first amplifier MOS transistor 49
Connect to the gate of

The drain of the first amplifier MOS transistor 49 is connected to the first selection MOS transistor 51.
Of the first selection MOS transistor 5
The first gate is connected to the gate of the second selection MOS transistor 61 and commonly connected as a vertical selection terminal 63 for each row, and the drain of the first selection MOS transistor 51 is connected to the first data output line 91 as a column. They are commonly connected every time.

Further, the gate of the second shutter MOS transistor 53 is commonly connected to all the photoelectric conversion cells 31 as the second shutter terminal 55, and the drain of the second shutter MOS transistor 53 is the third parasitic capacitance. 57 and second MOS transistor 5 for amplifier
9 gate.

The drain of the second amplifier MOS transistor 59 is connected to the second selection MOS transistor 61.
Of the second selection MOS transistor 6
One drain is commonly connected as a second data output line 93 for each column.

The bulk of the reset MOS transistor 33 and the first shutter MOS transistor 43
And the second MOS transistor 5 for shutter
3, the bulk of the first amplifier transistor 49, the bulk of the second amplifier transistor 59, the bulk of the first selection transistor 51, the bulk of the second selection transistor 61, The other terminal of one parasitic capacitance 41, the other terminal of the second parasitic capacitance 47, the other terminal of the third parasitic capacitance 57, and the anode terminal of the photodiode 39 are all connected to the ground terminal 65. Connected in common.

Further, the photoelectric conversion cell 3 according to the present invention
In the photoelectric conversion cell 31 having the above-described configuration, the drain of the first selection MOS transistor is commonly connected as a first output line for each column, and the second selection signal is connected to the second output signal. The drain of the MOS transistor is commonly connected as a second output line for each column, the gate of the first MOS transistor for a shutter is commonly connected as a first shutter line to all photoelectric conversion cells, The gate of the MOS transistor is commonly connected to all photoelectric conversion cells as a second shutter line, and the gate of the second selection MOS transistor connected to the gate of the first selection MOS transistor is connected to the address selection line for each row. And the drain of the reset MOS transistor and the gate of the reset MOS transistor In which are arranged in a matrix are connected in common conversion cells.

Next, an example of the configuration of the data comparison circuit 71 used in the present invention will be described.

That is, the data comparison circuit 71 is composed of the same number of differential amplification circuits 73 as the number of columns of the photoelectric conversion cells 31 constituting the photoelectric conversion cell array 13. The first input line 91 and the second output line 93 described above are connected to the two inputs, respectively.

That is, each data comparison circuit cell 71 according to the present invention is constituted by a plurality of data comparison circuits 73, for example, the same number as the number of columns of the photoelectric conversion cells 31.

The output of the data comparison circuit 73 is output from a comparison result output terminal 95.

Next, a method of driving the MOS solid-state imaging device will be described in detail with reference to FIGS.

First, during the image data acquisition period of the N frame 97, the reset signal 81 of the reset time 103 is input to the reset signal terminals 37 of all the photoelectric conversion cells 31 and the first shutters of all the photoelectric conversion cells 31 The first shutter signal 83 of the shutter time 105 is input to the signal terminal 45. At this time, the L-level second shutter signal 85 is input to the second shutter signal terminals 55 of all the photoelectric conversion cells 31. By this operation, the first parasitic capacitances 41 arranged in all the photoelectric conversion cells 31 are obtained. And the second parasitic capacitance 47 is reset. Then, after the reset time 103 ends, the first shutter signal 8
3 is a light receiving section of each photoelectric conversion cell 31 in a period until the shutter time 105 of the photodiode 3 ends.
The image data of the subject irradiated on 9 is stored in the first parasitic capacitance 41 and the second parasitic capacitance 47 according to the amount of incident light. When the shutter time 105 of the first shutter signal 83 ends and the first MOS transistor for shutter 43 is turned off, the image data of the subject is stored in the second parasitic capacitance 47. The upper part of the second parasitic capacitance 47 is shielded from light with aluminum or the like, so that the stored image data does not leak.

The image data of the N frame 97 stored in the second parasitic capacitance 47 is amplified by the first amplifying MOS transistor 49 disposed in each photoelectric conversion cell 31, and is amplified by the first selecting MOS transistor. 51 can be selected and read.

Next, during the image data acquisition period of the (N + 1) th frame 99, the reset signal 81 of the reset time 103 is input to the reset signal terminals 37 of all the photoelectric conversion cells 31 and the second signal of all the photoelectric conversion cells 31 The second shutter signal 85 having a shutter time 107 is input to the shutter signal terminal 55 of the second embodiment. At this time, the shutter times 105 and 107 for inputting the L-level first shutter signal 83 to the first shutter signal terminals 45 of all the photoelectric conversion cells 31 are the same.

By this operation, the first parasitic capacitance 41 and the third parasitic capacitance 57 arranged in all the photoelectric conversion cells 31 are reset. Then, after the reset time 103 ends, the shutter time 1 of the second shutter signal 85
The image data of the subject illuminated on each photodiode 39 which is the light receiving unit of each photoelectric conversion cell 31 during the period until 07 ends is converted into the first parasitic capacitance 4 by the amount of incident light.
1 and the third parasitic capacitance 57.

When the shutter time 107 of the second shutter signal 85 ends and the second shutter MOS transistor 53 turns off, the image data of the subject is stored in the third parasitic capacitance 57. This third parasitic capacitance 57
The upper part is light-shielded with aluminum or the like so that the stored image data does not leak.

The image data of the (N + 1) th frame 99 stored in the third parasitic capacitance 57 is stored in each photoelectric conversion cell 3.
1st MOS transistor 59 for amplifier arranged in
And the second selection MOS transistor 61
Can be selected and read.

Next, a method of reading image data will be described. After the shutter time 105 of the second shutter signal 85 ends in the (N + 1) th frame 99 and the second shutter signal 85 becomes L level, the vertical selection circuit 15
The vertical address signal 87 selects the vertical selection terminal 63 in one row of the photoelectric conversion cell array 13.

The first selection MOS transistor 51 and the second selection MOS transistor 51 of all the photoelectric conversion cells 31 connected to one row of the selected photoelectric conversion cell array 13
The transistor 61 is turned on, and the first data output line 91
The N frame 97 stored in the second parasitic capacitance 47
Is output. On the other hand, the image data of the (N + 1) th frame 99 stored in the third parasitic capacitance 57 is output to the second data output line 93.

The image data of the N frame 97 output as the first data line signal 91 and the image data of the N + 1 frame 99 output as the second data line signal 93 are compared with the data connected to the respective columns. The data is input to the circuit 73, and the data comparison circuit 73
7 and the image data of the (N + 1) th frame 99 are output from the comparison result output terminal 75 as an amplified differential circuit output signal 95.

The output from the comparison result output terminal 75 is
In response to a horizontal address signal 89 from the horizontal selection circuit 19, the signals are sequentially transmitted to the output amplifier circuit 23 in serial. After the data of one row of the photoelectric conversion cells 31 is read, the vertical address signal changes, and the next row is selected, and the image data is read out similarly. Thus, the image data of all the photoelectric conversion cells 31 are read.

By reading out the image data of the photoelectric conversion cell array 13 as described above, the image signal of the N frame 97 and the N + 1 frame 99 are output from the output signal terminal 25 of the MOS solid-state imaging device 11 in the N + 1 frame 99 read cycle. Only the image data difference is output.

That is, the difference between the immediately preceding frame image data and the current frame image data is always output.

Therefore, the A / D circuit and the memory circuit as shown in FIG. 7 are not required, and complicated control and time-consuming processing time are not required. When reading data, the difference from the image data of the previous frame can always be read.

As will be understood from the above description, the driving method of the MOS type solid-state imaging device according to another embodiment of the present invention will be described with reference to FIG. The pixel data of the frame obtained by turning off the gate of the second MOS transistor for shutter and turning on the first transistor for shutter and the gate of the first MOS transistor for shutter in the next frame are turned off. By comparing and reading out pixel data obtained by turning on the shutter transistor in the data comparison circuit, comparison image data with the image data of the previous frame is always obtained.

[0074]

As described above, in the solid-state imaging device according to the present invention, the photoelectric conversion cell array arranged in a matrix, and the photoelectric conversion cell array includes a data comparison circuit, a load circuit, and a vertical selection circuit. The circuit and the control circuit are connected, and the data comparison circuit is connected to the horizontal selection circuit, and the horizontal selection circuit is connected to the output amplifier, and the control circuit is connected to the vertical selection circuit, the data comparison circuit, and the horizontal selection circuit. This configuration has an image data processing function compared with the immediately preceding frame data.

Therefore, as shown in the prior art of FIG.
When reading image data of each frame without the need for complicated control and time-consuming processing time without requiring a / D circuit or a memory circuit, the image data of the previous frame is always read. Can be read.

Further, in the present invention, it is not necessary to use an independent memory for each frame as in the prior art, so that the circuit configuration is simplified, and miniaturization is possible. Needless to say, in the present invention, since the elements constituting the solid-state imaging device can be constituted by MOS transistors, the manufacturing process can be simplified and the cost can be reduced.

On the other hand, according to the present invention, when a difference value between the first frame and the second frame is obtained, a determination is made directly using analog information.
Unlike the prior art, the comparison process is not performed after the analog input information is once changed to digital data, so that an improvement in speed and accuracy can be expected.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a specific example of the solid-state imaging device according to the present invention.

FIG. 2 is a diagram illustrating a configuration of a photoelectric conversion cell used in a MOS type solid-state imaging device used in the present invention.

FIG. 3 is a timing chart illustrating a method for driving a MOS solid-state imaging device according to the present invention.

FIG. 4 is a block circuit diagram illustrating an example of a configuration of a conventional MOS solid-state imaging device.

FIG. 5 is a diagram illustrating a configuration of a photoelectric conversion cell of a conventional MOS-type solid-state imaging device.

FIG. 6 is a timing chart illustrating a driving method of a conventional MOS solid-state imaging device.

FIG. 7 is an example of an apparatus for comparing image data using a conventional MOS solid-state imaging device;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 11 ... MOS type solid-state imaging device 13 ... photoelectric conversion cell array 15 ... horizontal selection circuit 17 ... data comparison circuit array 19 ... vertical selection circuit 20 ... load circuit 21 ... control circuit 23 ... output amplifier circuit 25 ... output signal terminal 31 ... photoelectric conversion Cell 33 reset means 39 photoelectric conversion elements 43 and 53 shutter means 51 and 61 selecting means 73 data comparison circuits 91 and 93 image data output lines 95 comparison circuit output lines 111 conventional MOS solid-state imaging device 113: Conventional photoelectric conversion cell array arranged in a matrix 119: Vertical selection circuit 121: Control circuit 123: Output amplifier 115: Horizontal selection circuit 125: Output terminal 131: Photoelectric conversion cell 133: Reset MOS transistor 135: Reset voltage Terminal 137: Reset signal terminal 1 39 ... photodiode 141 ... first parasitic capacitance 143 ... shutter MOS transistor 145 ... shutter signal terminal 147 ... second parasitic capacitance 149 ... amplifier MOS transistor 151 ... selection MOS transistor 157 ... data output terminal 153 ... vertical selection Terminal 155 Ground terminal 183 First memory circuit 185 Second memory circuit 187 Comparison circuit 200 Load circuit

 ────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor Nobuhiro Fueki 1-10-1 Shinsayama, Sayama-shi, Saitama Honda Engineering Co., Ltd. F-term (reference) 5B047 AA07 AB02 BA03 BB04 BC01 CA04 CB18 5C024 AX19 CX54 GY31 HX17 HX29 HX40

Claims (16)

[Claims] 1. A photoelectric conversion cell array in which a plurality of photoelectric conversion cells are arranged in a matrix, and an output amplifier connected to a horizontal selection circuit, a vertical selection circuit, a control circuit, and a horizontal selection circuit connected to the photoelectric conversion cell array. In each of the solid-state imaging devices, the individual photoelectric conversion cells temporarily store the image data in the first frame and the image data in the second frame. A solid-state imaging device configured to output both image data according to a predetermined control signal. 2. The solid-state imaging device according to claim 1, wherein each of the photoelectric conversion cells has at least two image data output lines. 3. The method according to claim 2, wherein
3. The solid-state imaging device according to claim 1, wherein each of the image data output lines is connected to one of a plurality of data comparison circuits connected to the horizontal selection circuit. 4. The photoelectric conversion cell includes one photoelectric conversion element and one reset unit for the photoelectric conversion element.
4. The solid-state imaging device according to claim 1, further comprising a pair of shutter units and a pair of selection units that are alternately driven. 5. The solid-state imaging device according to claim 4, wherein said reset means, shutter means, and selection means are all constituted by MOS transistors. 6. A photoelectric conversion cell array in which a plurality of photoelectric conversion cells are arranged in a matrix, a data comparison circuit, a vertical selection circuit, and a control circuit are connected to the photoelectric conversion cell array. In the solid-state imaging device connected to the horizontal selection circuit, the output amplifier is connected to the horizontal selection circuit, and the control circuit is connected to the vertical selection circuit, the data comparison circuit, and the horizontal selection circuit. Each of them is configured to temporarily store the image data in the first frame and the image data in the second frame, and output both image data in accordance with a predetermined control signal. Characteristic solid-state imaging device. 7. The one photoelectric conversion cell arranged in a matrix includes one photoelectric conversion element and one reset MOS transistor, and includes a set of shutter MOs.
7. The MOS according to claim 1, comprising an S transistor, a set of amplifying MOS transistors, and a set of selecting MOS transistors.
Type solid-state imaging device. 8. One end of the reset MOS transistor controlled by a reset signal at the other end of the photoelectric conversion element whose one end is grounded, and one end of a first shutter MOS transistor controlled by a shutter signal. And the first MOS for the shutter
The other end of the transistor has a first end connected to the first image data output line and a gate connected to the vertical selection line via a suitable amplifier MOS transistor.
The other end of the selection MOS transistor is connected to the other end of the photoelectric conversion element connected to one end of the reset MOS transistor. One end of the MOS transistor is connected, and one end of the second shutter MOS transistor is connected to a second image data output line via an appropriate MOS transistor for an amplifier. 8. The solid-state imaging device according to claim 1, wherein the other end of the second selection MOS transistor whose gate is connected to a vertical selection line is connected. 9. The solid-state imaging device according to claim 1, wherein said photoelectric conversion element is constituted by a photodiode. 10. A terminal between the two terminals of the photoelectric conversion element, a connection between the first shutter MOS transistor and the first selection MOS transistor and a ground, or the second shutter MOS transistor. 2. A portion where at least a part of the charge generated by the photoelectric conversion element is stored between a connection portion with the second selection MOS transistor and a ground portion.
10. The solid-state imaging device according to any one of claims 9 to 9. 11. The solid-state imaging device according to claim 10, wherein a portion in which at least a part of the charge generated by the photoelectric conversion element is stored is a portion recognized as a parasitic capacitance portion. 12. The photoelectric conversion cell according to claim 1, further comprising a MO for resetting.
One end of the photoelectric conversion element, one end of the first parasitic capacitance, the source of the first shutter MOS transistor, and the source of the second shutter MOS transistor are connected to the source of the S transistor. The gate of the first amplifier MOS transistor and one end of the second parasitic capacitance are connected to the drain, and the gate of the second amplifier MOS transistor and the third parasitic capacitor are connected to the drain of the second shutter MOS transistor. One end of the capacitor is connected, the source of the first selecting transistor is connected to the drain of the first amplifier MOS transistor, and the source of the second selecting transistor is connected to the drain of the second amplifier MOS transistor. Are connected,
The gate of the first selection MOS transistor and the gate of the second selection MOS transistor are commonly connected, and the bulk of the reset MOS transistor and the first amplifier M
The source of the OS transistor, the source of the second amplifier MOS transistor, the other terminal of the photoelectric conversion element, the other terminal of the first parasitic capacitance, the other terminal of the second parasitic capacitance, and the third parasitic A MOS-type solid-state imaging device imaging device, comprising a photoelectric conversion cell in which the other terminal of the capacitor is connected in common. 13. The photoelectric conversion cell according to claim 1, wherein
, The drains of the selection MOS transistors are commonly connected as a first output line for each column, the drains of the second selection MOS transistors are commonly connected as a second output line for each column, and the first shutter The gate of the MOS transistor for use as a first shutter line is commonly connected to all photoelectric conversion cells, and the gate of the MOS transistor for second shutter is commonly used as a second shutter line for all photoelectric conversion cells. The gate of the second selection MOS transistor connected to the gate of the selection MOS transistor is commonly connected as an address selection line for each row, and the drain of the reset MOS transistor and the reset MOS transistor are connected.
A MOS type solid-state imaging device, wherein the gates of the transistors are connected in common in all photoelectric conversion cells and arranged in a matrix. 14. The data comparison circuit is composed of the same number of differential amplification circuits as the number of columns of the photoelectric conversion cell array, and two inputs of each differential amplification circuit have the first output described above. 14. The MOS according to claim 1, wherein the first output line and the second output line are connected to each other.
Type individual imaging device. 15. The comparison circuit according to claim 1, wherein each of the pixel data in the first frame and the second frame output from each of the photoelectric conversion cells is compared as analog data. The solid-state imaging device according to claim 1, wherein: 16. The solid-state imaging device according to claim 1, wherein the gate of the second MOS transistor for shutter in each photoelectric conversion cell is turned off, The pixel data of the frame obtained by turning on the shutter transistor of the first and the pixel data obtained by turning off the gate of the first MOS transistor for the next frame and turning on the second transistor for the next frame are the data A method for driving a MOS solid-state imaging device, characterized in that comparison readout by a comparison circuit always obtains comparison image data with image data of a previous frame.