CN213904904U

CN213904904U - LCD driving circuit structure

Info

Publication number: CN213904904U
Application number: CN202023261680.2U
Authority: CN
Inventors: 高庆; 曹旺
Original assignee: CRM ICBG Wuxi Co Ltd
Current assignee: CRM ICBG Wuxi Co Ltd
Priority date: 2020-12-29
Filing date: 2020-12-29
Publication date: 2021-08-06
Anticipated expiration: 2030-12-29

Abstract

The utility model relates to a LCD driving circuit structure, wherein the positive input end of a voltage follower is connected with a reference voltage Vref, the output end is connected with a first port, the reverse input end is connected with a control position, and the control position controls the grounding or the output end of the reverse input end; first clock structure, second clock structure and third clock structure all contain the mode selection control bit, and through revising charge pump clock logic, the third switch and the fourth switch of control second clock structure and the fifth switch and the sixth switch of third clock structure keep off-state or connected state, have adopted the utility model discloses an LCD drive circuit structure can realize that multiple bias voltage selects, adapts to multiple full bias threshold voltage's LCD drive circuit to improve the adaptability to the LCD panel, reduce the BOM cost. The utility model discloses an adaptability is wide, can realize that multiple bias voltage selects, adapts to multiple full partial threshold voltage's LCD drive circuit.

Description

LCD driving circuit structure

Technical Field

The utility model relates to a circuit structure field especially relates to LCD drive field, specifically indicates a LCD drive circuit structure.

Background

Currently, many LCD devices are used, and the LCD panels used for the LCD devices require 1/3 biases, 1/2 biases, and the like, and the full-bias threshold voltages also include 2V, 3V, 4.5V, and the like. Common LCD driving circuits often support only one of the voltage division methods, and the full bias threshold voltage coverage is narrow.

The liquid crystal used in the LCD panel is an organic compound having a regular molecular arrangement, which is a substance between a solid state and a liquid state, and has an electro-optical effect and polarization characteristics. Commonly used liquid crystal display panels are classified into a Twisted Nematic (TN), a Super Twisted Nematic (STN), and a color Thin Film (TFT). The most common liquid crystal panel in small appliances is of the TN type.

When the LCD is driven, an ac voltage is applied to the segment electrodes SEG and the common electrode COM, and a dc voltage is applied only to the electrodes, the liquid crystal itself is deteriorated, and the LCD panel is damaged for a long time. In practical applications, dynamic scan ac driving is generally used, the liquid crystal field is usually divided into 3 segments (1/3duty) or more, and the driving voltage is 1/2bias (1/2bias), 1/3bias (1/3bias), etc. The liquid crystal field is divided into a row-column array by adopting a topological method, the back pole of each bit field is divided into a plurality of groups (for example, the back pole of each bit field is divided into 3 groups by a 3-division method), and the back poles of the fields of all groups are connected to form a row (a public end); the fields are also divided into several groups, each group is connected into columns (SEG ends), and the fields on the same column respectively correspond to different back poles. Different periodic scanning driving signals are respectively applied to the rows and the columns during display, corresponding to 1/3bias voltage, four groups of voltage levels of 0, V1, V2 and V3 are applied to the scanning driving signals every half COM clock period, so that voltage difference of threshold voltage amplitude can be obtained only when fields or dot matrixes at the intersections of the rows and the columns are scanned, corresponding fields or dot matrixes are lightened for display, and the rest voltage difference is smaller than an LCD driving threshold value and cannot be displayed. The COM waveform diagram is shown in fig. 1. Some current LCD driving structure is shown in fig. 2.

The LCD drive is 1/3bias, and the LCD bias is divided into 0, Vref (V1), 2 × Vref (V2), and 3 × Vref (V3). PH1, PH2, and PH3 respectively show 3 clocks with staggered timing and fast switching, as shown in fig. 3. When PH1 is active, S0, S1 are open and other switches are closed; when PH2 is active, S2, S3 are open and other switches are closed; when PH3 is active, S4, S5 are open and the other switches are closed.

As shown in fig. 3, the op-amp forms a voltage follower that causes VP1 to become Vref. When PH1 is active, VCUP1 ═ VP1 ═ VC0, VCUP2 ═ 0, capacitors C1, C0 charge; when PH2 is active, VCUP1 ═ VP2, VCUP2 ═ VP1, the fast-switching switches make the charge of C0 not to bleed in time, resulting in VP2 ═ VP1+ VC0 ═ 2VP1 ═ 2 × Vref, and the charge corresponding to VP2 is stored in C2; when PH3 is active, VCUP1 ═ VP3 and VCUP2 ═ VP2, the fast-switching switches also allow C0 charge to escape in time, resulting in VP3 ═ VP2+ VC0 ═ 3VP1 ═ 3 × Vref, and the charge corresponding to VP3 is stored in C3. This achieves LCD bias voltages of 0, Vref, 2 × Vref, and 3 × Vref.

SUMMERY OF THE UTILITY MODEL

The utility model aims at overcoming the shortcoming of above-mentioned prior art, providing one kind and satisfying adaptability wide, the flexibility good, application scope comparatively extensive LCD drive circuit structure.

In order to achieve the above object, the LCD driving circuit of the present invention has the following structure:

the LCD driving circuit structure is mainly characterized in that the circuit structure comprises a voltage follower, a first clock structure, a second clock structure and a third clock structure, and the circuit structure also comprises a first port, a second port, a third port VP3, a first CUP port and a second CUP port;

the first port is connected with the first CUP port through a first switch, the second CUP port is grounded through a second switch, the second port is connected with the first CUP port through a third switch, the first port is connected with the second CUP port through a fourth switch, the third port is connected with the first CUP port through a fifth switch, and the second port is connected with the second CUP port through a sixth switch; the clock signal output by the first clock structure controls the connection or disconnection state of the first switch and the second switch; the clock signal output by the second clock structure controls the connection or disconnection state of the third switch and the fourth switch; the clock signal output by the third clock structure controls the connection or disconnection state of the fifth switch and the sixth switch;

the voltage output by the second port is the voltage generated by the circuit structure after 2 times of voltage, the voltage output by the third port is the voltage generated by the circuit structure after 3 times of voltage, and the circuit structure is compatible with the situations of 1/3bias and 1/2 bias.

Preferably, the positive input terminal of the voltage follower is connected to the reference voltage Vref, the output terminal is connected to the first port (VP1), the negative input terminal is connected to the control bit, and the control bit controls the negative input terminal to be grounded or connected to the output terminal.

Preferably, in the circuit structure at 1/3bias, if the inverting input terminal of the voltage follower is connected to the output terminal, the voltage output by the first port is the reference voltage Vref, and the voltage after voltage doubling are 2 × Vref and 3 × Vref, respectively; if the reverse input end of the voltage follower is grounded, the voltage output by the first port is high level VDD, and the voltage U is multiplied_VP2Sum voltage U_VP32 x VDD and 3 x VDD, respectively.

Preferably, the circuit structure enables the second clock structure to control the third switch and the fourth switch to keep an open state through the mode selection control bit under the condition of 1/2bias, and the first port and the second port are connected in a short circuit at the periphery.

Preferably, the control bit of the voltage follower switches between connection with the output terminal and ground; if the reverse input end of the voltage follower is connected with the output end, the voltage output by the first port is the reference voltage Vref, and the voltage U is obtained after 2 times of voltage_VP3Is 2 × Vref; if the reverse input end of the voltage follower is grounded, the voltage output by the first port is high level VDD and is subjected to voltage multiplication by 2, namely voltage U_VP3Is 2 × VDD.

Preferably, the circuit structure maintains the fifth switch and the sixth switch of the third clock structure PH3 in an off state through the mode selection control bit under the condition of 1/2bias, and the second port and the third port are short-circuited at the periphery.

Preferably, the control bit of the voltage follower switches between connection with the output terminal and ground; if the reverse input end of the voltage follower is connected with the output end, the voltage output by the first port is the reference voltage Vref, and the voltage U is obtained after 2 times of voltage_VP2Is 2 × Vref; if the inverting input terminal of the voltage follower is grounded, the voltage outputted from the first port VP1 is high level VDDVoltage U after passing 2 times voltage_VP2Is 2 × VDD.

Adopted the utility model discloses a LCD drive circuit structure can realize that multiple bias voltage selects, adapts to multiple full bias threshold voltage's LCD drive circuit to improve the adaptability to the LCD panel, reduce the BOM cost. The utility model discloses an adaptability is wide, can realize that multiple bias voltage selects, adapts to multiple full partial threshold voltage's LCD drive circuit.

Drawings

Fig. 1 is a schematic diagram of a COM waveform of the prior art.

Fig. 2 is a schematic diagram of a related art LCD driving structure.

Fig. 3 is a waveform diagram illustrating a driving structure of a related art LCD.

Fig. 4 is a schematic circuit diagram of 1/3bias of the LCD driving circuit structure according to the present invention.

Fig. 5 is a waveform diagram of 1/2bias of the LCD driving circuit structure according to the present invention.

Fig. 6 is a schematic circuit diagram of 1/2bias of the LCD driving circuit structure according to the present invention.

Detailed Description

In order to more clearly describe the technical content of the present invention, the following further description is given with reference to specific embodiments.

The utility model discloses a this LCD drive circuit structure, the utility model provides a select, adapt to multiple full partial threshold voltage's circuit to multiple biasing voltage. To be compatible with 1/2bias or 1/3bias, and VDD or Vref may be scaled by 2 or 3. This can be achieved by modifying the voltage doubler circuit. The utility model discloses an optional VDD of voltage doubling voltage source or reference voltage Vref. COM may alternatively use 1/3bias or 1/2 bias. The above components can be combined arbitrarily to adapt to various LCD panels of 2V-4.5V.

The circuit structure comprises a voltage follower, a first clock structure PH1, a second clock structure PH2 and a third clock structure PH3, and further comprises a first port VP1, a second port VP2, a third port VP3, a first CUP port and a second CUP port;

the first port VP1 is connected to the first CUP port CPU1 through a first switch S0, the second CUP port CPU2 is connected to ground through a second switch S1, the second port VP2 is connected to the first CUP port CPU1 through a third switch S2, the first port VP1 is connected to the second CUP port CPU2 through a fourth switch S3, the third port VP3 is connected to the first CUP port CPU1 through a fifth switch S4, and the second port VP2 is connected to the second CUP port CPU2 through a sixth switch S5; the clock signal output by the first clock structure PH1 controls the connection or disconnection state of the first switch S0 and the second switch S1; the clock signal output by the second clock structure PH2 controls the connection or disconnection state of the third switch S2 and the fourth switch S3; the clock signal output by the third clock structure PH3 controls the connection or disconnection state of the fifth switch S4 and the sixth switch S5;

the positive input end of the voltage follower is connected with a reference voltage Vref, the output end of the voltage follower is connected with the first port VP1, the reverse input end of the voltage follower is connected with a control bit, and the control bit controls the reverse input end to be grounded or connected with the output end.

The voltage output by the second port VP2 is the voltage U generated by the circuit structure after 2 times voltage_VP2The voltage output by the third port VP3 is a voltage U generated by 3 times the voltage of the circuit structure_VP3The circuit structure is compatible with the situations of 1/3bias and 1/2 bias.

1/3bias modification principle As shown in FIG. 4, the original circuit generates Vref reference voltage internally, and generates voltage U with Vref via voltage follower_VP1Then carrying out 2-time voltage and 3-time voltage by a charge pump to generate U with 2 XVref and 3 XVref voltages_VP2And U_VP3. While by grounding the inverting input of the voltage follower (via the register bit LCD)<0>Control), the voltage follower VP1 outputs high level VDD, and the structure of the charge pump does not need to be changed to generate 2 × VDD and 3 × VDD voltages.

In a preferred embodiment of the present invention, the circuit structure is 1/3bias, if the reverse input terminal of the voltage follower is connected to the output terminal, the voltage outputted from the first port VP1 is the reference voltage Vref, and the voltage U is multiplied by the voltage_VP2

Sum voltage U

_VP32 × Vref and 3 × Vref, respectively; if the inverse of the voltage followerThe voltage output to the first port VP1 is high level VDD and voltage U after voltage multiplication_VP2Sum voltage U_VP32 x VDD and 3 x VDD, respectively.

1/2bias modification principle As shown in FIG. 5, the voltage follower modification is consistent with 1/3bias, and the voltage source of VP1 is selected to be VDD or Vref by LCD <0 >.

The charge pump part continuously disables PH2 in the figure through the selection bit of the register bit LCD <1>, the period VP2 and CUP1, VP1 and CUP2 keep the off state, VP1 and VP2 are short-circuited at the periphery, and the boosting period PH1 and PH3 are alternately enabled as shown in FIG. 6. The voltage-doubling capacitors are continuously switched between VP1(VP2) and GND, VP3 and VP1(VP2), and the voltage value of VP3 is 2 × VDD (or 2 × Vref).

The mode select control bit is added to keep S2 and S3 turned off by modifying the charge pump clock logic. The periphery short-circuits VP2 and VP1, and the capacitor C1 can be omitted according to the practical application requirement. The control bit is added to ground the inverting input of the op-amp, and VP1 equals VDD. Wherein VOL <1 >: 1 is 1/2bisa and 0 is 1/3 bisa. Modifying the time sequence of the gating clock, selecting 1/3bisa, and keeping the original 3-phase clock at PH1, PH2 and PH 3; the choice of 1/2bisa at PH1 and PH3 uses a 2-phase clock.

The switch in the ring is realized by adopting logic circuits such as a transmission gate, a multiplexer and the like in an actual circuit, and the value of the register is converted into the control of a switch signal thereof by utilizing combination and sequential logic to complete a preset function.

With the above modifications, the LCD can implement the following functions:

LCD<1:0>value taking	Partial pressure type	Output bias voltage
			00	1/3	Vref、2×Vref、3×Vref
01	1/3	VDD、2×VDD、3×VDD
			10	1/2	Vref、2×Vref
11	1/2	VDD、2×VDD

This greatly increases the flexibility of the LCD driving structure with only minor modifications.

In the preferred embodiment of the present invention, the circuit structure is 1/2bias, and the second clock structure PH2 controls the third switch S2 and the fourth switch S3 to maintain the open state through the mode selection control bit, and the first port VP1 and the second port VP2 are connected in short circuit at the periphery.

The control bit of the voltage follower is switched between being connected with the output end and being grounded, if the reverse input end of the voltage follower is connected with the output end, the voltage output by the first port VP1 is the reference voltage Vref, and the voltage U is obtained by 2 times of the voltage_VP3Is 2 × Vref; if the inverting input terminal of the voltage follower is grounded, the voltage output from the first port VP1 is high level VDD, and the voltage U is obtained after 2 times of the voltage_VP3Is 2 × VDD.

In a preferred embodiment of the present invention, the circuit configuration is configured to maintain the fifth switch S4 and the sixth switch S5 of the third clock configuration PH3 in an off state through the mode selection control bit under 1/2bias, and the second port VP2 and the third port VP3 are connected in a short circuit at the periphery.

The control bit of the voltage follower is switched between connection with the output end and grounding; if the inverting input terminal of the voltage follower is connected to the output terminal, the voltage output from the first port VP1 is the reference voltage Vref, and the voltage U is obtained by multiplying the voltage by 2_VP2 Is 2 × Vref; if the reverse input end of the voltage follower is grounded, the first port U_VP1The output voltage is high level VDD and voltage U after 2 times of voltage_VP2Is 2 × VDD.

In the embodiment of the present invention, the charge pump part can also make PH3 in the figure continuously invalid through the register bit LCD <1> selection bit, during which VP3 and CUP1, VP2 and CUP2 remain off, and VP2 and VP3 are shorted at the periphery, and PH1 and PH2 are alternately valid during the boosting period. The voltage-doubling capacitor is continuously switched between VP1 and GND, VP2 and VP1, and the voltage value of VP2 is 2 × VDD (or 2 × Vref).

In this specification, the invention has been described with reference to specific embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the invention. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.

Claims

1. An LCD driving circuit structure is characterized in that the circuit structure comprises a voltage follower, a first clock structure PH1), a second clock structure PH2 and a third clock structure PH3, and the circuit structure further comprises a first port VP1, a second port VP2, a third port VP3, a first CUP port CPU1 and a second CUP port CPU 2;

2. The LCD driving circuit structure of claim 1, wherein the voltage follower has a positive input terminal connected to a reference voltage Vref, an output terminal connected to the first port VP1, and a negative input terminal connected to a control bit, the control bit controlling the negative input terminal to be grounded or connected to the output terminal.

3. The LCD driving circuit structure of claim 2, wherein in the case of 1/3bias, if the inverting input terminal of the voltage follower is connected to the output terminal, the voltage outputted from the first port VP1 is the reference voltage Vref, and the voltage VP2 and the voltage VP3 after voltage doubling are 2 × Vref and 3 × Vref, respectively; if the inverting input terminal of the voltage follower is grounded, the voltage output from the first port VP1 is high level VDD, and the voltage U is multiplied_VP2Sum voltage U_VP32 x VDD and 3 x VDD, respectively.

4. The LCD driving circuit structure according to claim 1 or 2, wherein the circuit structure is configured to keep the third switch S2 and the fourth switch S3 in an off state by the second clock structure PH2 via the mode selection control bit under 1/2bias, and the first port VP1 and the second port VP2 are connected in a short circuit at the periphery.

5. The LCD driver circuit structure of claim 4, wherein the control bit of the voltage follower switches between connection to the output terminal and ground; if the inverting input terminal of the voltage follower is connected to the output terminal, the voltage output from the first port VP1 is the reference voltage Vref, and the voltage U is obtained by multiplying the voltage by 2_VP3Is 2 × Vref; if the inverting input terminal of the voltage follower is grounded, the voltage output from the first port VP1 is high level VDD, and the voltage U is obtained after 2 times of the voltage_VP3Is 2 × VDD.

6. The LCD driving circuit structure of claim 1 or 2, wherein the circuit structure maintains the fifth switch S4 and the sixth switch S5 of the third clock structure PH3 in an off state by the mode selection control bit under 1/2bias, and the second port VP2 and the third port VP3 are short-circuited at the periphery.

7. The LCD driver circuit structure of claim 6, wherein the control bit of the voltage follower switches between connection to the output terminal and ground; if the inverting input terminal of the voltage follower is connected to the output terminal, the voltage output from the first port VP1 is the reference voltage Vref, and the voltage U is obtained by multiplying the voltage by 2_VP2Is 2 × Vref; if the inverting input terminal of the voltage follower is grounded, the voltage output from the first port VP1 is high level VDD, and the voltage U is obtained after 2 times of the voltage_VP2Is 2 × VDD.