CN217588405U - Liquid crystal display device and control circuit thereof - Google Patents
Liquid crystal display device and control circuit thereof Download PDFInfo
- Publication number
- CN217588405U CN217588405U CN202221273623.2U CN202221273623U CN217588405U CN 217588405 U CN217588405 U CN 217588405U CN 202221273623 U CN202221273623 U CN 202221273623U CN 217588405 U CN217588405 U CN 217588405U
- Authority
- CN
- China
- Prior art keywords
- signal
- terminal
- transistor
- coupled
- control signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Landscapes
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
The utility model discloses a liquid crystal display device and control circuit thereof, liquid crystal display device include display panel and provide drive signal's drive circuit to display panel, and control circuit includes: a power unit providing a first level signal; the time sequence control unit is coupled with the power unit and provides a time sequence control signal; the level shifting unit is coupled with the power unit and the time sequence control unit and generates an original grid control signal and a first grid control signal according to the time sequence control signal; the time sequence regulation and control unit is coupled with the power unit and the level shift unit, receives the original grid control signal and the first level signal, and provides one of the original grid control signal and the second level signal as a second grid control signal to the driving circuit according to the effective state of the first level signal; when the liquid crystal display device is turned off, the power-down speed of the second level signal is slower than that of the original grid control signal.
Description
Technical Field
The utility model relates to a display device technical field, in particular to liquid crystal display device and control circuit thereof.
Background
A Liquid Crystal Display (LCD) is a Display device that changes the light transmittance of a light source by utilizing the phenomenon that the alignment direction of Liquid Crystal molecules changes under the action of an electric field. Due to the advantages of good display quality, small size, and low power consumption, liquid crystal display devices have been widely used in electronic devices such as high definition digital televisions, desktop computers, notebook computers, tablet computers, mobile phones, digital cameras, and so on.
With the development of display technologies, display panels tend to have high integration and low cost. In the related art, a Gate-driver in Array (GIA) circuit is directly integrated on an Array substrate of a display panel, and the GIA circuit generally includes a plurality of cascaded Gate driving units, each corresponding to one or more rows of pixels corresponding to a scan line, so as to implement a scan driver for the display panel. The integration technology can save the area occupied by the gate driving circuit so as to realize the narrow frame of the display panel. However, in the liquid crystal display device using the metal oxide thin film transistor, there is a special requirement for the on/off timing of the GIA signal in order to ensure the safety of the internal circuit and the good display effect. For example, when the liquid crystal display device is turned off, the clock signal CLK follows the level signal VGH1, and the timing signal V1 follows the level signal VGH2, at this time, the clock signal CLK and the timing signal V1 are required to have different power-down speeds, that is, the level signal VGH1 and the level signal VGH2 have different power-down speeds.
Accordingly, an improved liquid crystal display device and a control circuit thereof are desired, which can solve the above-mentioned problems.
SUMMERY OF THE UTILITY MODEL
In view of the above, an object of the present invention is to provide a liquid crystal display device and a control circuit thereof, which can meet the shutdown timing requirement of the liquid crystal display device for the GIA signal.
The utility model provides a liquid crystal display device's control circuit, liquid crystal display device include display panel and to display panel provides drive signal's drive circuit, wherein, control circuit includes:
a power unit providing a first level signal;
the time sequence control unit is coupled with the power unit and provides a time sequence control signal;
the level shifting unit is coupled with the power unit and the time sequence control unit and generates an original grid control signal and a first grid control signal according to the time sequence control signal;
a timing control unit, coupled to the power unit and the level shift unit, for receiving the original gate control signal and the first level signal, and providing one of the original gate control signal and the second level signal as a second gate control signal to the driving circuit according to an effective state of the first level signal; wherein
When the liquid crystal display device is shut down, the power-down speed of the second level signal is slower than that of the original grid control signal.
Further, the timing control unit includes a first input terminal for receiving the first level signal, a second input terminal for receiving the original gate control signal, and an output terminal for providing the second gate control signal, and the timing control unit includes:
a capacitor coupled between the first input terminal and ground;
a first transistor, a control terminal of the first transistor is coupled to the first input terminal, a first terminal is coupled to a first terminal of the capacitor, a second terminal is used as an output terminal of the timing adjustment unit,
a second transistor, wherein a control terminal of the second transistor is coupled to the first input terminal, a first terminal of the second transistor is coupled to the second input terminal, and a second terminal of the second transistor is coupled to a second terminal of the first transistor; wherein, the first and the second end of the pipe are connected with each other,
the first end of the capacitor provides the second level signal.
Further, the timing adjustment unit is configured to:
when a first level signal of a first state is received, outputting the original grid control signal as the second grid control signal;
and when receiving the first level signal in the second state, outputting the second level signal as the second grid control signal.
Further, when the first level signal is in the first state,
the first transistor is turned off, the second transistor is turned on, and the time sequence regulation and control unit outputs the original grid control signal as the second grid control signal; wherein the content of the first and second substances,
the first level signal charges the capacitor.
Further, when the first level signal is in the second state,
the first transistor is turned on, the second transistor is turned off, and the timing sequence regulation and control unit outputs the second level signal as the second grid control signal; wherein, the first and the second end of the pipe are connected with each other,
the first transistor being turned on provides a current path for charge stored in the capacitor;
the electric charge released by the capacitor is superposed with the first level signal so as to slow down the power-down speed of the second level signal.
Further, the capacitance value of the capacitor is adjusted, and the power-down speed of the second level signal is changed.
Further, the first gate control signal is selected from any one or a combination of two of a start signal and a clock signal;
the original gate control signal is selected from a first original timing signal and a second original timing signal.
Further, the timing adjustment unit further includes:
a diode having a first terminal coupled to the first input terminal and a second terminal coupled to the first terminal of the capacitor.
Further, the first transistor comprises a first body diode, a first terminal of the first body diode is coupled to the first terminal of the first transistor, and a second terminal of the first body diode is coupled to the second terminal of the first transistor;
the second transistor comprises a second body diode, a first terminal of the second body diode is coupled to a first terminal of the second transistor, and a second terminal of the second body diode is coupled to a second terminal of the second transistor.
The utility model also provides a liquid crystal display device, wherein, liquid crystal display device includes:
the display device comprises a display panel and a grid driving circuit for providing a grid driving signal to the display panel; and (c) a second step of,
the control circuit as described above, coupled to the gate driving circuit, and providing a first gate control signal and a second gate control signal to the gate driving circuit; wherein, the first and the second end of the pipe are connected with each other,
the gate driving circuit is integrated on the display panel.
To sum up, the liquid crystal display device according to the embodiment of the present application can achieve different requirements of the GIA signal on the shutdown timing sequence only by using one level shift unit, so that the power-down speed of the second gate control signal is slower than that of the first gate control signal, and the electric charges in the display panel can be fully released when the display device is shutdown, thereby effectively improving the shutdown flicker phenomenon, and reducing the production and development costs.
Optionally, the timing sequence adjusting and controlling unit of the embodiment of the present application includes two transistors, a capacitor and a diode, and the circuit structure is simple.
Optionally, the control logic of the timing control unit in the embodiment of the present application is simple, the first level signal and the original gate control signal are not only output signals at different stages or output signals generated indirectly, but also are used as control signals for selecting which path of output signal to output to control the on and off of the first transistor and the second transistor, the input and output signals are fewer, the number of signal lines to be added is also fewer, the circuit area is further saved, and the production cost is reduced.
In a feasible embodiment, the power-down speed of the second level signal can be changed by adjusting the capacitance value of the capacitor, so that the power-down time of the second level signal can be changed, and the timing sequence regulation and control circuit in the embodiment of the application can be suitable for various application scenarios.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:
FIG. 1 is a timing diagram illustrating a shutdown of signals in a portion of a liquid crystal display device;
fig. 2 is a schematic structural diagram of a liquid crystal display device according to an embodiment of the present invention;
FIG. 3 is a circuit diagram of the timing adjustment unit of FIG. 2;
FIG. 4 illustrates a timing diagram of the timing regulation unit of FIG. 3;
fig. 5 is a graph showing a waveform comparison of timing signals in different liquid crystal display devices.
Detailed Description
Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. In the various figures, identical elements or modules are denoted by the same or similar reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale.
It should be understood that in the following description, "circuitry" may comprise singly or in combination hardware circuitry, programmable circuitry, state machine circuitry, and/or elements capable of storing instructions executed by programmable circuitry. When an element or circuit is referred to as being "connected to" another element or circuit is referred to as being "connected between" two nodes, it may be directly coupled or connected to the other element or intervening elements may be present, and the connection between the elements may be physical, logical, or a combination thereof. In contrast, when an element is referred to as being "directly coupled" or "directly connected" to another element, it is intended that there are no intervening elements present.
Also, certain terms are used throughout the description and claims to refer to particular components. As one of ordinary skill in the art will appreciate, manufacturers may refer to a component by different names. This patent specification and claims do not intend to distinguish between components that differ in name but not function.
In this application, the transistor may include one selected from a bipolar transistor or a field effect transistor, the first terminal and the second terminal of the transistor are a high potential terminal and a low potential terminal, respectively, on the current path, and the control terminal is configured to receive a control signal to control the transistor to be turned on and off. A MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) includes a first terminal, a second terminal, and a control terminal, and a current flows from the first terminal to the second terminal in an on state of the MOSFET. The first end, the second end and the control end of the P-type MOSFET are respectively a source electrode, a drain electrode and a grid electrode, and the first end, the second end and the control end of the N-type MOSFET are respectively a drain electrode, a source electrode and a grid electrode. In the following description, numerous specific details of the invention, such as types of components, coupling relationships, structures, materials, dimensions, processing techniques and technologies, are described in order to provide a more thorough understanding of the invention. However, as will be understood by those skilled in the art, the present invention may be practiced without these specific details.
Moreover, it should be further noted that, in this document, relational terms such as first and second are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrases "comprising one of 8230; \8230;" 8230; "does not exclude the presence of additional like elements in a process, method, article, or apparatus that comprises the element.
Fig. 1 shows a timing diagram of shutdown of signals of a part of a liquid crystal display device. The liquid crystal display device includes a display panel, a control circuit, and a driving circuit. The display panel comprises a plurality of grid scanning lines and a plurality of source data lines which are intersected with each other, a pixel unit is formed at the intersection position of the grid scanning lines and the source data lines, and each pixel unit at least comprises a Thin Film Transistor (TFT). The control circuit comprises a power unit, a time sequence control unit and a level shifting unit, wherein the power unit provides signals such as working voltage for other units, the time sequence control unit provides time sequence control signals for the level shifting unit, and the level shifting unit generates corresponding GIA signals according to the time sequence control signals and provides the GIA signals to the driving circuit. The driving circuit comprises an integrated grid driving unit and a source driving unit, wherein in each frame period, the integrated grid driving unit sequentially scans a plurality of grid scanning lines, the thin film transistors are gated through the grid scanning lines, then the source driving unit applies voltages corresponding to gray scales to the pixel units through source data lines, so that the orientation of liquid crystal molecules is changed, and the light transmittance of the pixel units is correspondingly changed due to the orientation change of the liquid crystal molecules.
In fig. 1, the start signal STV, the clock signal CLK, the timing signal V1 and the level signal VGL are shown from top to bottom. It should be understood that fig. 1 shows only one of each type of signal, which has the same or similar period, amplitude, and duty cycle during the operational phase, and the same or similar power down timing after shutdown. In practical applications, each type of signal may include a plurality of signals, and for example, the liquid crystal display device includes a start signal STV1, a start signal STV2, a clock signal CLK1, a clock signal CLK2, a clock signal CLK3, a clock signal CLK4, a timing signal V1, a timing signal V2, a level signal VGL, a level signal VSQ, and the like.
As can be seen from fig. 1, at time t0, the lcd device is turned off, the start signal STV, the clock signal CLK and the level signal VGL are pulled up to the predetermined voltage Vpre1, and the timing signal V1 is pulled up to the predetermined voltage Vpre2. The power-down speed of the start signal STV, the clock signal CLK and the level signal VGL is fast, and all the power-down speed is reduced to 0V at the time t1, and the potential of the timing signal V1 is required to be greater than the preset voltage Vpre3. Until time t2, the potential of the timing signal V1 does not drop to 0V.
After time t0, the start signal STV, the clock signal CLK, and the level signal VGL follow the level signal VGH1 (not shown), the timing signal V1 follows the level signal VGH2 (not shown), and the shutdown timing of the GIA signal requires that the level signal VGH1 and the level signal VGH2 have the same voltage and different power-down speeds. In some technical solutions, two level shift units are adopted, one of the two level shift units is used for providing a start signal STV, a clock signal CLK and a level signal VGL, and the other level shift unit is used for providing a timing signal V1, so that the shutdown timing requirement of the liquid crystal display device is realized.
In view of the above, the present application provides an improved liquid crystal display device and a control circuit thereof, as shown in fig. 2. The liquid crystal display device 200 includes a display panel 210, a driving circuit 220, and a control circuit 230.
The display panel 210 includes a plurality of pixel units arranged in an array, and each pixel unit mainly includes a thin film transistor, a storage capacitor, and a liquid crystal capacitor. Each pixel unit is coupled to a driving circuit through a gate line and a source line. In response to a gate driving signal provided through the gate line, the pixel unit may receive a data signal via the source line, apply a voltage corresponding to a gray scale to the pixel unit, and thereby change the orientation of the liquid crystal molecules, which causes a corresponding change in light transmittance of the pixel unit, thereby displaying luminance corresponding to the data signal.
The driving circuit 220 is coupled to the control circuit 230, generates a driving signal according to a control signal provided by the control circuit 230, and provides the driving signal to the display panel 210. The driving signals include, for example, gate driving signals and source data signals.
The driving circuit 220 includes an integrated gate driving unit 221 and a source driving unit 222. The integrated gate driving unit 221 is, for example, integrated on the display panel, receives a gate control signal, generates a gate driving signal based on the gate control signal, and supplies the gate driving signal to a corresponding gate line. The gate control signal includes, for example, a first gate control signal and a second gate control signal.
The source driving unit 222 receives the source signal, generates a corresponding data signal according to the source signal, and provides the data signal to a corresponding data line. The source signal includes, for example, a source control signal and frame data.
The control circuit 230 is used for providing control signals such as a gate control signal (e.g., a GIA signal), a source signal (not shown), etc. to the driving circuit 220. The control circuit 230 includes a power unit 231, a timing control unit 232, a level shift unit 233, and a timing adjustment unit 234.
The Timing Controller 232 is coupled to the POWER unit (POWER IC) 231, and receives signals such as operating voltage and generates a Timing control signal.
The Level Shift unit (Level Shift) 233 is coupled to the power unit 231, receives signals such as the Level signal VGL, the Level signal VGH, and the Level signal VSQ, and is further coupled to the timing control unit 232, receives the timing control signal, generates a corresponding gate control signal according to the timing control signal, and provides the gate control signal to the driving circuit 220. For example, the level shift unit 233 generates the start signal STV, the clock signal CLK, the timing signal V1in and the timing signal V2in, provides the start signal STV and the clock signal CLK to the integrated gate driving unit 221, and provides the timing signal V1in and the timing signal V2in to the timing adjustment unit 234. The first gate control signal includes a start signal STV and a clock signal CLK, and the original gate control signal includes a timing signal V1in and a timing signal V2in.
It should be understood that for ease of description, only one of each type of signal may be shown, with the same or similar period, amplitude, and duty cycle during the operational phase, and the same or similar power down timing after shutdown. In practical applications, each type of signal may include a plurality of signals, and for example, the liquid crystal display device includes a start signal STV1, a start signal STV2, a clock signal CLK1, a clock signal CLK2, a clock signal CLK3, a clock signal CLK4, a timing signal V1, and a timing signal V2, and may further include signals such as a level signal VGL and a level signal VSQ.
The timing adjustment unit 234 includes a first input terminal, a second input terminal, and an output terminal. The first input terminal is coupled to the power unit 231, receives the level signal VGH1, the second input terminal is coupled to the level shift unit 233, receives the timing signal V1in and the timing signal V2in, and the output terminal provides the timing signal V1out and the timing signal V2out to the integrated gate driving unit 221. The timing signals V1out and V2out are, for example, second gate control signals.
When the level signal VGH1 is in an active state, the timing adjustment and control unit 234 provides the timing signal V1in and the timing signal V2in as the timing signal V1out and the timing signal V2out to the integrated gate driving unit 221. When the level signal VGH1 is powered down, the timing control unit 234 provides the level signal VGH2 to the integrated gate driving unit as the timing signal V1out and the timing signal V2out. The power-down speed of the level signal VGH2 is slower than that of the level signal VGH1, but the potentials of the level signal VGH2 and the level signal VGH1 are the same when the level signal VGH and the level signal are in a high level state.
The liquid crystal display device of the embodiment of the application can realize different requirements of the GIA signal on the shutdown time sequence only by using one level shifting unit, so that the power failure speed of the time sequence signal V1out and the time sequence signal V2out is slower than that of the start signal STV and the clock signal CLK, the charges in the display panel can be fully released when the display device is shut down, and the shutdown flicker phenomenon is effectively improved.
Further, referring to fig. 3 and 4, fig. 3 illustrates a circuit structure diagram of the timing adjustment unit in fig. 2, and fig. 4 illustrates a timing diagram of the timing adjustment unit in fig. 3. The timing adjustment unit 234 includes a transistor Q1, a transistor Q2, a diode D1, and a capacitor C1.
The first terminal of the diode D1 is the first input terminal of the timing control unit 234, and receives the level signal VGH1, the first terminal of the capacitor C1 is coupled to the second terminal of the diode D1, and the second terminal is grounded. The first terminal of the transistor Q1 is coupled to the first terminal of the capacitor C1, and the second terminal thereof is used as the output terminal of the timing adjusting unit 234 to provide the timing signal V1out and the timing signal V2out. The first terminal of the transistor Q2 is a second input terminal of the timing control unit 234, and receives the timing signal V1in and the timing signal V2in, and the second terminal is coupled to the second terminal of the transistor Q1. The control terminals of the transistors Q1 and Q2 are coupled to the first terminal of the diode D1, and receive the level signal VGH1.
In this embodiment, the transistor Q1 further includes a body diode D3, a first terminal of the body diode D3 is coupled to the second terminal of the transistor Q1, and a second terminal is coupled to the first terminal of the transistor Q1. The transistor Q2 further includes a body diode D2, wherein a first terminal of the body diode D2 is coupled to the first terminal of the transistor Q2, and a second terminal of the body diode D2 is coupled to the second terminal of the transistor Q2. Illustratively, the transistor Q1 is selected from a P-type fet and the transistor Q2 is selected from an N-type fet.
Referring to fig. 4, before time t0, i.e. the operation stage of the liquid crystal display device 200, the level signal VGH1 is in a high state, the capacitor C1 stores charges, and the level signal VGH2 at the first end thereof is also in a high state. At this time, the control terminal of the transistor Q1 is equal to the first terminal voltage, and the transistor Q1 is turned off.
The timing signal V1in and the timing signal V2in are, for example, square wave signals, when the timing signal V1in and the timing signal V2in are in a low level state, the first terminal of the transistor Q2 is at a low level, the control terminal voltage VGH1 is at a high level, the transistor Q2 is turned on, and the timing signal V1out and the timing signal V2out are also at a low level. When the timing signal V1in and the timing signal V2in are inverted to the high state, the body diode D2 of the transistor Q2 is turned on, and the timing signal V1out and the timing signal V2out are also at the high level.
Therefore, when the liquid crystal display device 200 is in the working phase, the transistor Q1 is turned off, and the timing adjustment and control unit 234 outputs the timing signal V1in and the timing signal V2in as the timing signal V1out and the timing signal V2out.
At time t0, the lcd device 200 is turned off, and the level signal VGH1, the level signal VGH2, the timing signal V1in, the timing signal V2in, the timing signal V1out, and the timing signal V2out are all turned off. The timing signal V1in and the timing signal V2in are generated by the level shift unit 233, and the power-down speed thereof is the same as the level signal VGH1, that is, the control terminal of the transistor Q2 is the same as the first terminal voltage, so as to turn off the transistor Q2.
The level signal VGH1 is powered down, the voltage of the control terminal of the transistor Q1 is reduced, the absolute value of the difference between the level signal VGH1 and the level signal VGH2 is greater than the threshold voltage of the transistor Q1, the transistor Q1 is turned on, the level signal VGH2 is provided to the output end through the transistor Q1, and the level signal VGH2 is output as the timing signal V1out and the timing signal V2out.
Meanwhile, the transistor Q1 is turned on to provide a current path for the charges stored in the capacitor C1, and the stored charges released by the capacitor C1 are overlapped with the level signal VGH1, so that the power-down speed of the level signal VGH2 is slowed down. It can be seen that the potential of the level signal VGH1 has dropped to 0V at time t1, and the potential of the level signal VGH2 has not dropped to 0V until time t2, so that the power-down speeds of the timing signal V1out and the timing signal V2out are slower than the clock signal CLK and the start signal STV, and the requirement of the liquid crystal display device 200 on the shutdown timing is satisfied.
The time sequence regulation and control unit of the embodiment of the application comprises two transistors, one capacitor and one diode, the circuit structure is simple, and compared with the mode that one level shifting unit is additionally arranged, the occupied area is smaller, and the production cost is reduced.
Optionally, in the timing adjustment and control unit in the embodiment of the application, the control logic is simple, the level signal VGH1, the timing signal V1in, and the timing signal V2in are output signals at different stages or generate output signals indirectly, and are used as control signals for selecting which signal to output to control the on and off of the transistor Q1 and the transistor Q2, so that the input and output signals are fewer, the number of signal lines to be added is also fewer, the circuit area is further saved, and the production cost is reduced.
In a possible embodiment, the power-down speed of the level signal VGH2 can be further changed by adjusting the capacitance value of the capacitor C1, so as to change the power-down time t2 of the level signal VGH2 and the potential of the level signal VGH2 at the time t 1. Thereby changing the power-down timings of the start signal STV, the clock signal CLK associated with the level signal VGH1, and the timing signals V1out and V2out associated with the level signal VGH2 when the liquid crystal display device 200 is turned off. The time sequence regulation and control circuit can be suitable for various application scenes.
As can be seen from fig. 4, after the time t0, the voltage of the level signal VGH2 is always greater than the timing signal V1in and the timing signal V2in, so the potential of the second terminal of the body diode D2 is always greater than the potential of the first terminal, and the body diode D2 is not turned on. The timing signal V1in and the timing signal V2in will not leak to the output end, which will cause adverse effects to the timing signal V1out and the timing signal V2out.
It should be understood that after time t0, the level signal VGH1 and the level signal VGH2 start to fall from the same potential, and the absolute value of the difference between the two signals needs to be greater than the threshold voltage of the transistor Q1 after a predetermined time, so as to turn on the transistor Q1, and the predetermined time is negligible short in this embodiment, and thus is not shown in fig. 4.
Fig. 5 shows a comparison of waveforms of timing signals in different lcd devices, which are, from top to bottom, a waveform of a timing signal Vls1 of an lcd device having a control circuit including only one level shift unit, a waveform of a timing signal Vls2 of an lcd device having a control circuit including two level shift units, and a waveform of a timing signal Vls3 of an lcd device using a control circuit according to an embodiment of the present application.
Before the time t0, the liquid crystal display device is in a working stage, and the timing signals are square wave signals, for example.
At the time t0, the liquid crystal display device is turned off, the power-down speed of the time sequence signal Vls1 is high, the potential of the time sequence signal Vls1 at the time t4 is already reduced to the preset voltage Vref, the power-down speed of the time sequence signal Vls2 is low, the potential of the time sequence signal Vls3 at the time t5 is reduced to the preset voltage Vref, the power-down speed of the time sequence signal Vls3 is also low, the potential of the time sequence signal Vls 6 at the time t6 is reduced to the preset voltage Vref, and it can be seen in FIG. 5 that the time t5 is coincident with the time t6, which indicates that the power-down time sequence of the time sequence signal Vls3 of the liquid crystal display device adopting the control circuit of the embodiment of the application can achieve the effect that the time sequence signal Vls2 of the liquid crystal display device with two level shifting units in the control circuit is basically the same, and can meet the requirement of the power-down time sequence when the liquid crystal display device is turned off.
Further, by adjusting the capacitance of the capacitor in the timing control circuit, the time for the potential of the timing signal Vls3 to fall to the predetermined voltage Vref can be changed, for example, the time period from t0 to t4 is about 30ms, the time period from t0 to t5 is about 76ms, and the time period from t0 to t6 is about 148ms.
To sum up, the liquid crystal display device according to the embodiment of the present application can achieve different requirements of the GIA signal on the shutdown timing by using only one level shift unit, so that the power-down speeds of the timing signal V1out and the timing signal V2out are slower than the start signal STV and the clock signal CLK, and charges in the display panel can be fully released when the display device is shutdown, thereby effectively improving the shutdown flicker phenomenon, and reducing the production and development costs.
Optionally, the timing sequence adjusting unit of the embodiment of the application includes two transistors, a capacitor and a diode, the circuit structure is simple, and compared with the case that a level shift unit is added, the occupied area is smaller, and the production cost is effectively reduced.
Optionally, the control logic of the timing sequence regulation and control unit in the embodiment of the present application is simple, the level signal VGH1, the timing sequence signal V1in, and the timing sequence signal V2in are output signals at different stages or generate output signals indirectly, and are used as control signals for selecting which signal to output to control the on and off of the transistor Q1 and the transistor Q2, so that the input and output signals are fewer, the number of signal lines to be added is also fewer, the circuit area is further saved, and the production cost is reduced.
In a feasible embodiment, the power-down speed of the level signal VGH2 can be changed by adjusting the capacitance value of the capacitor C1, so as to change the power-down time t2 of the level signal VGH2 and the potential of the level signal VGH2 at the time t1, so that the timing sequence regulation and control circuit in the embodiment of the application can be applied to various application scenarios.
It should be noted that the words "during", "when" and "when 8230; \8230when" as used herein in relation to the operation of a circuit are not strict terms indicating an action that occurs immediately upon the start of a start action, but rather there may be some small but reasonable delay or delays, such as various transmission delays, between it and the reaction action (action) initiated by the start action. The words "about" or "substantially" are used herein to mean that the value of an element (element) has a parameter that is expected to be close to the stated value or position. When used in conjunction with a signal state, the actual voltage value or logic state (e.g., "1" or "0") of the signal depends on whether positive or negative logic is used.
In accordance with the present invention, as set forth above, these embodiments do not set forth all of the details nor limit the invention to the specific embodiments described. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and its practical application, to thereby enable others skilled in the art to best utilize the invention and its various embodiments with various modifications as are suited to the particular use contemplated. The scope of the present invention should be determined by the appended claims and their equivalents.
Claims (10)
1. A control circuit of a liquid crystal display device including a display panel and a drive circuit which supplies a drive signal to the display panel, the control circuit comprising:
a power unit providing a first level signal;
the time sequence control unit is coupled with the power unit and provides a time sequence control signal;
the level shifting unit is coupled with the power unit and the time sequence control unit and generates an original grid control signal and a first grid control signal according to the time sequence control signal;
a timing control unit coupled to the power unit and the level shift unit, receiving the original gate control signal and the first level signal, and providing one of the original gate control signal and the second level signal as a second gate control signal to the driving circuit according to an effective state of the first level signal; wherein
When the liquid crystal display device is shut down, the power-down speed of the second level signal is slower than that of the original grid control signal.
2. The control circuit of claim 1, wherein the timing adjustment unit comprises a first input receiving the first level signal, a second input receiving the original gate control signal, and an output providing the second gate control signal, the timing adjustment unit comprising:
a capacitor coupled between the first input terminal and ground;
a first transistor, a control terminal of the first transistor is coupled to the first input terminal, a first terminal is coupled to a first terminal of the capacitor, a second terminal is used as an output terminal of the timing adjustment unit,
a second transistor, a control terminal of the second transistor being coupled to the first input terminal, a first terminal being coupled to the second input terminal, and a second terminal being coupled to a second terminal of the first transistor; wherein the content of the first and second substances,
the first end of the capacitor provides the second level signal.
3. The control circuit of claim 2, wherein the timing adjustment unit is configured to:
when a first level signal in a first state is received, outputting the original grid control signal as the second grid control signal;
and when the first level signal in the second state is received, outputting the second level signal as the second grid control signal.
4. The control circuit of claim 3, wherein when the first level signal is in a first state,
the first transistor is turned off, the second transistor is turned on, and the time sequence regulation and control unit outputs the original grid control signal as the second grid control signal; wherein the content of the first and second substances,
the first level signal charges the capacitor.
5. The control circuit of claim 3, wherein when the first level signal is in the second state,
the first transistor is turned on, the second transistor is turned off, and the timing sequence regulation and control unit outputs the second level signal as the second grid control signal; wherein, the first and the second end of the pipe are connected with each other,
the first transistor being turned on provides a current path for charge stored in the capacitor;
the electric charge released by the capacitor is superposed with the first level signal so as to slow down the power-down speed of the second level signal.
6. The control circuit of claim 5, wherein adjusting the capacitance of the capacitor changes the power-down speed of the second level signal.
7. The control circuit of claim 1,
the first gate control signal is selected from any one or combination of a start signal and a clock signal;
the original gate control signal is selected from a first original timing signal and a second original timing signal.
8. The control circuit of claim 2, wherein the timing adjustment unit further comprises:
a diode having a first terminal coupled to the first input terminal and a second terminal coupled to the first terminal of the capacitor.
9. The control circuit of claim 2,
the first transistor comprises a first body diode, a first end of the first body diode is coupled to a first end of the first transistor, and a second end of the first body diode is coupled to a second end of the first transistor;
the second transistor comprises a second body diode, a first terminal of the second body diode is coupled to a first terminal of the second transistor, and a second terminal of the second body diode is coupled to a second terminal of the second transistor.
10. A liquid crystal display device, characterized in that the liquid crystal display device comprises:
the display device comprises a display panel and a grid driving circuit for providing a grid driving signal to the display panel; and (c) a second step of,
the control circuit of any of claims 1-9, coupled to the gate drive circuit and providing a first gate control signal and a second gate control signal to the gate drive circuit; wherein, the first and the second end of the pipe are connected with each other,
the gate driving circuit is integrated on the display panel.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202221273623.2U CN217588405U (en) | 2022-05-25 | 2022-05-25 | Liquid crystal display device and control circuit thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202221273623.2U CN217588405U (en) | 2022-05-25 | 2022-05-25 | Liquid crystal display device and control circuit thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN217588405U true CN217588405U (en) | 2022-10-14 |
Family
ID=83553992
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202221273623.2U Active CN217588405U (en) | 2022-05-25 | 2022-05-25 | Liquid crystal display device and control circuit thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN217588405U (en) |
-
2022
- 2022-05-25 CN CN202221273623.2U patent/CN217588405U/en active Active
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US11127478B2 (en) | Shift register unit and driving method thereof, gate driving circuit, and display device | |
| US9865211B2 (en) | Shift register unit, gate driving circuit and display device | |
| US10950323B2 (en) | Shift register unit, control method thereof, gate driving device, display device | |
| US11227524B2 (en) | Shift register unit and driving method thereof, gate driving circuit and driving method thereof, and display device | |
| US11263951B2 (en) | Shift register unit and driving method thereof, gate driving circuit, and display device | |
| CN108962154B (en) | Shifting register unit, array substrate grid driving circuit, display and grid driving method | |
| WO2018209937A1 (en) | Shift register, drive method thereof, gate drive circuit, and display device | |
| US11443684B2 (en) | Shift register, gate drive circuit, display panel and driving method | |
| CN109243351B (en) | Shifting register unit and driving method thereof, grid driving circuit and display device | |
| CN110264948B (en) | Shifting register unit, driving method, grid driving circuit and display device | |
| US10319324B2 (en) | Shift registers, driving methods, gate driving circuits and display apparatuses with reduced shift register output signal voltage switching time | |
| CN108320708B (en) | Shifting register and driving method thereof, grid driving circuit and display device | |
| US10796780B2 (en) | Shift register unit and driving method thereof, gate driving circuit and display apparatus | |
| US10685615B2 (en) | Shift register and driving method thereof, gate driving circuit, and display device | |
| US11107381B2 (en) | Shift register and method for driving the same, gate driving circuit and display device | |
| KR20080011896A (en) | Gate on voltage generation circuit and gate off voltage generation circuit and liquid crystal display having the same | |
| US20210225312A1 (en) | Shift register unit and driving method thereof, gate driving circuit and display device | |
| CN106991958B (en) | Shifting register unit and driving method thereof, grid driving circuit and display device | |
| US20210225249A1 (en) | Scan shift circuit, touch shift circuit, driving method and related apparatus | |
| US11423823B2 (en) | Shift register and driving method thereof, gate driving circuit and display device capabling reset the output terminal | |
| CN106683617B (en) | Shifting register unit, array substrate and display device | |
| CN114999557A (en) | Shift register, driving method thereof and grid driving circuit | |
| CN214587964U (en) | Liquid crystal display device with a light guide plate | |
| CN214175660U (en) | Liquid crystal display device having a plurality of pixel electrodes | |
| CN217588405U (en) | Liquid crystal display device and control circuit thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant |