KR20050069871A - Common voltage regulator for lcd - Google Patents

Abstract

The present invention relates to a liquid crystal display device, and more particularly, to a common voltage generation circuit capable of improving image quality.

This adds an additional resistance to the common voltage steady-state filling time delay phenomenon caused by the load of a capacitor and a resistor configured to prevent noise in the common voltage generating circuit for the common voltage swing output. The filling time is shortened by adjusting the gain output by changing the resistance value.

Such an overdriving method improves the quality of image quality because the normal driving time of the video data input in accordance with the frame driving timing can be improved by improving the delay of the filling time in the steady state in the swing-type common voltage application driving.

Description

Common Voltage Regulator Circuit {common voltage regulator for LCD}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display, and more particularly, to provide a common voltage generation circuit capable of improving block dim and wave noise by reducing delay time in swing driving of a common voltage.

A TFT-LCD is a display device that obtains a desired image signal by applying an electric field to a liquid crystal material having an anisotropic dielectric constant injected between two substrates, and controlling the amount of light transmitted through the substrate by adjusting the intensity of the electric field.

On the substrate of such a TFT-LCD, a plurality of gate lines parallel to each other and a plurality of data lines insulated from and intersecting the gate lines are formed, and an area surrounded by the gate lines and the data lines defines one pixel. TFTs are formed at portions where the gate lines and the data lines of each pixel cross each other.

In order to drive such a TFT-LCD, a gate line is sequentially driven and a data voltage to be applied to a source terminal of a TFT connected to the driving gate line is applied through the data line. At this time, in order to prevent deterioration of the liquid crystal generated as the electric field in the direction is continuously applied to the pixels formed in the TFT, the polarity of the data voltage is inverted with respect to the common voltage every frame. The TFT-LCD driving method for inverting the polarity of the data voltage is called an inversion driving method.

FIG. 1 is a diagram illustrating a conventional active matrix liquid crystal display device, in which a liquid crystal cell is arranged in a matrix form between two transparent substrates, and gate lines GL1 of the liquid crystal panel 2. Gamma voltage generator 8 connected to gate driver 6 connected to GLm), data driver 4 connected to data lines DL1 to DLn of liquid crystal panel 2, and data driver 4; ).

A thin film transistor (hereinafter referred to as "TFT") is provided as a switching element at an intersection of the m gate lines GL1 to GLm and the n data lines DL1 to DLn. The gate driver 6 sequentially supplies the scanning signals to the m gate lines GL1 to GLm to drive the TFTs connected to the corresponding gate lines.

Among the liquid crystal display devices having the above structure, in particular, the IPS mode liquid crystal display device has a common voltage generating circuit as shown in FIG. 2 for the level swing of the common voltage. Such a common voltage generating circuit has a square wave control signal as shown in FIG. When (CNT) is input, the common voltage output by the principle of the inverting amplifier is as shown in Equation (1).

Formula (1)

Where (VLCD) is the liquid crystal driving voltage.

As shown in the signal output waveform diagram of FIG. 4, the following equation {(RF // R1) is applied by the resistor RF and the capacitor CF configured to prevent the inflow of noise into the inverting amplifier in the circuit structure of FIG. The time delay D occurs when the common voltage Vcom signal rises or falls due to the load represented by x CF} and the load parasitic on the liquid crystal panel line itself. Here, (RF // R1) refers to the combined resistance by the parallel connection between the resistor (RF) and the resistor (R1).

This is because the swing time through rising and falling of the common voltage Vcom reaches a steady state before the interval time between frame driving ends. If the common voltage Vcom does not reach a steady state in the signal timing to which data is applied, image quality defects such as luminance degradation may occur.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object thereof is to further increase the charging speed of a common voltage that should be charged to a steady state level before a data signal is applied, thereby eliminating the cause of image quality defects.

To this end, another object of the present invention is to propose a common voltage generating circuit having no delay in charging time in a swing of a common voltage alternately repeating rising and falling.

In order to achieve the above object, the present invention provides a first embodiment, comprising: a computing device having an inverting input terminal, a non-inverting input terminal, and an output terminal; A push-pull circuit unit which is driven by receiving an output of the operation element and outputs a common voltage through a common voltage output terminal; A capacitor configured between an inverting input terminal of said computing element and a common voltage output terminal of said push-pull circuit portion; A first resistor configured between the inverting input terminal of the computing element and the common voltage output terminal of the push-pull circuit portion; A second resistor having one end connected to the inverting input terminal of the operation element; A first switching transistor connected to the other end of the second resistor and the common voltage output terminal of the push-pull circuit unit and driven by receiving a first switching signal; A third resistor having one end connected to a non-inverting input terminal of the operation element and a driving voltage input to the other end; A fourth resistor configured between a ground terminal and a non-inverting input terminal of the computing element; A fifth resistor whose one end is connected to the non-inverting input terminal of the computing element; A second switching transistor configured between the other end of the fifth resistor and the ground terminal and driven by receiving a second switching signal; A common voltage generating circuit including a sixth resistor having one end connected to an inverting input terminal of the operation element and a control signal input to the other end thereof is proposed.

The present invention also provides a second embodiment, comprising: a computing element having an inverting input terminal, a non-inverting input terminal, and an output terminal; A push-pull circuit unit which receives and drives an output of the operation element and outputs a common voltage through a common voltage output terminal; A capacitor configured between an inverting input terminal of said computing element and a common voltage output terminal of said push-pull circuit portion; A first resistor having one end connected to the inverting input terminal of the operation element; A second resistor having one end connected in series with the first resistor and the other end connected with the common voltage output terminal; A first switching transistor configured between both ends of the second resistor and driven by receiving a first switching signal; A third resistor having one end connected to a non-inverting input terminal of the operation element and a driving voltage input to the other end; A fourth resistor configured between a ground terminal and a non-inverting input terminal of the computing element; A fifth resistor whose one end is connected to the non-inverting input terminal of the computing element; A second switching transistor configured between the other end of the fifth resistor and the ground terminal and driven by receiving a second switching signal; A common voltage generating circuit including a sixth resistor having one end connected to an inverting input terminal of the operation element and a control signal input to the other end thereof.

In addition, the present invention provides a third embodiment of the present invention, comprising: an operation element having an inverting input terminal, a non-inverting input terminal, and an output terminal; A push-pull circuit unit which is driven by receiving an output of the operation element and outputs a common voltage through a common voltage output terminal; A capacitor configured between an inverting input terminal of said computing element and a common voltage output terminal of said push-pull circuit portion; A first resistor configured between the inverting input terminal of the computing element and the common voltage output terminal of the push-pull circuit portion; A second resistor having one end connected to an inverting input terminal of the operation element and a control signal input to the other end; A third resistor having one end connected to a non-inverting input terminal of the operation element and a driving voltage input to the other end; A fourth resistor configured between a ground terminal and a non-inverting input terminal of the computing element; A fifth resistor to which the driving voltage is input; A first switching transistor configured between the other end of the fifth resistor and the non-inverting input end of the arithmetic element and driven by receiving a first switching signal; A sixth resistor having one end connected to the non-inverting input terminal of the operation element; A common voltage generation circuit including a second switching transistor configured between the other end of the sixth resistor and a ground terminal and driven by receiving a second switching signal is provided.

As features to be applied to each of the above embodiments,

The operational element is characterized in that the operational amplifier.

The push-pull circuit portion may be composed of one or more transistors.

The push-pull circuit part may receive a driving voltage and be connected to a ground terminal.

The fourth resistor is a variable resistor.

The control signal is characterized in that the square wave.

The control signal is characterized in that the half period is 16.7ms.

The first switching signal may change an operating state of the first switching transistor when the control signal rises.

The second switching signal may change an operating state of the second switching transistor at the time when the control signal falls.

Each switching transistor is characterized in that the P-type or N-type transistor.

Hereinafter, a common voltage generating circuit and its features according to embodiments of the present invention will be described with reference to the accompanying drawings.

First embodiment

FIG. 5 is a circuit diagram showing a first embodiment of a common voltage generating circuit according to the present invention, in which an inverting amplifier (AMP), a push-pull circuit section (P / P), a P-type and an N-type are used as operational elements. A common voltage generation circuit composed of transistors TR1 and TR2, a plurality of resistors R1 to R6, and a capacitor CF is shown.

Here, the operation element AMP performs an inverted amplification, and is an operational amplifier OP-AMP having an inverting input terminal (-), a non-inverting input terminal (+), and an output terminal, and controls for a swing output of a common voltage. It receives a signal CNT.

The push-pull circuit unit P / P receives a liquid crystal driving voltage VLCD and further increases the swing speed of the common voltage Vcom. The push-pull circuit unit P / P is combined with one or more transistors and further includes a ground terminal GND. It is a connected configuration.

In addition, the fourth resistor R4, which is preferably constituted by variable resistance, is configured to adjust a block dim or the like appearing in the image by adjusting the resistance value.

The capacitor CF and the first resistor R1 are for preventing noise or a ripple voltage from being fed back and amplified by the input terminal of the operational element AMP, and being fed back to the input terminal of the operational element AMP. This is because the wave enters the panel and causes wave noise in the entire screen.

The control signal CNT is a square wave input to the inverting input terminal (-) of the inverting amplifier AMP with a half cycle of 16.7 ms, and has a level such that the common voltage Vcom output through the circuit has a change in level. Swing will be performed. The voltage difference between the high level and the low level of the control signal CNT is about 3.3V.

The first switching signal SW1 and the second switching signal SW2 are square waves, and voltage signals for driving each switching transistor are applied at the time when the control signal CNT rises and falls, respectively. According to the resistance synthesis relationship between the first resistor (R1), the second resistor (R2), the sixth resistor (R6) and the resistance between the third resistor (R3), fourth resistor (R4), fifth resistor (R5) The conversion of the composite relationship is performed to control the steady state response time according to the swing of the common voltage.

Hereinafter, the driving of the common voltage generating circuit and its effect will be described with reference to the driving timing diagram of FIG. 6 and the output graph of FIG. 7.

First, when the first switching transistor TR1 is P-type, when the first switching signal SW1 is at a high level, the first switching signal TR1 is turned off and the first switching signal SW1 is low. On at the level. In addition, when the second switching transistor TR2 is N-type, the second switching signal SW2 is turned on when the high level is high and the second switching signal SW2 is turned low. Off at low level.

Referring to the timing diagram, when the first switching signal SW1 is changed from the high level to the low level, that is, the output gain in the period in which the P-type first switching transistor TR1 is kept in the on state is ( -Rt / R6). At this time, Rt = (R2 // R1) = (R2 × R1) / (R2 + R1).

Subsequently, when the first switching signal SW1 is switched from the low level to the high level, the first switching transistor TR1 is turned off to amplify the signal input to the inverting input terminal (−) of the inverting amplifier AMP. Gain is switched to (-R1 / R6).

That is, in a section in which the first switching transistor TR1 is turned off by the first switching signal SW1, the first resistor R1 having a larger synthetic resistance for amplification gain is greater than R2 // R1. Since the output gain is increased by the inverting amplifier AMP at the time of the common voltage rising, the overdrive is overdriven when the common voltage is raised by the increased output gain (T). As a result, the charging time reduction effect is obtained.

Next, the common electrode DC level of the liquid crystal driving voltage VLCD input to the non-inverting input terminal (+) of the inverting amplifier AMP may change the second switching signal SW2 from a low level to a high level. When (R4 x VLCD) / (R3 + R4) is changed to (Rb x VLCD) / (R3 + Rb), where Rb = (R4 / / R5) = (R4 × R5) / (R4 + R5) to be.

That is, when the N-type second switching transistor TR2 is turned on, the value of the fourth resistor R4 that the second switching transistor TR2 has in the off period is (R4 × R5) / (R4 + As the resistance value decreases because it is replaced by the value of R5), overdriving occurs that the applied DC level drops rapidly, and thus, the charging time to the normal level of the inverted state is reduced by (T) time when the common voltage falls. You get an effect.

Thereafter, the DC level is increased again when the second switching signal SW2 is changed from a high level to a low level.

In the above-described first embodiment circuit according to the present invention, the first and second switching transistors TR1 and TR2 are configured as P-type and N-type, respectively, to change the synthesis resistance according to the switching driving thereof. Although the configuration induced by the second switching signal is illustrated, the transistors of different types or all of the same type except for the illustrated circuit may be configured, and accordingly, each switching signal for on / off control of each switching transistor. It should be obvious that the signal must be changed to an appropriate signal so that overdriving can be performed in the above-described manner.

Second embodiment

FIG. 8 is a circuit diagram showing a second embodiment of a common voltage generating circuit according to the present invention, in which an inverting amplifier AMP, a push-pull circuit section P / P, and first and second switching transistors are used as operational elements. A common voltage generation circuit composed of (TR1) (TR2), a plurality of resistors R1 to R6, and a capacitor CF is shown.

Here, the operation element AMP performs an inverted amplification, and is an operational amplifier OP-AMP having an inverting input terminal (-), a non-inverting input terminal (+), and an output terminal, and controls for a swing output of a common voltage. It receives a signal CNT.

The push-pull circuit part P / P is configured to receive a driving voltage VLCD and further increase a swing speed of the common voltage Vcom. One or more transistors are combined and further connected to the ground terminal GND. It is a configuration.

In addition, the fourth resistor R4, which is preferably composed of variable resistance, is configured to adjust a block dim appearing in the image by adjusting the resistance value.

The capacitor CF is to prevent the noise or the ripple voltage from being fed back to the input terminal of the arithmetic element AMP and amplified. This is because wave noise is generated.

The control signal CNT is a square wave input to the inverting input terminal (-) of the inverting amplifier AMP with a half cycle of 16.7 ms, and has a level such that the common voltage Vcom output through the circuit has a change in level. Swing will be performed. The voltage difference between the high level and the low level of the control signal CNT is about 3.3V.

The first switching signal SW1 and the second switching signal SW2 are square waves, and voltage signals for driving each switching transistor are applied at the time when the control signal CNT rises and falls, respectively. According to the resistance synthesis relationship between the first resistor (R1), the second resistor (R2), the sixth resistor (R6) and the resistance between the third resistor (R3), fourth resistor (R4), fifth resistor (R5) The conversion of the composite relationship is performed to control the steady state response time according to the swing of the common voltage.

Hereinafter, the driving and effects of the common voltage generation circuit according to the second embodiment of the present invention will be described with reference to the driving timing diagram of FIG. 6 and the output graph of FIG. 7 again. Is the same as the first embodiment described above.

First, when the first switching transistor TR1 is P-type, when the first switching signal SW1 is at a high level, the first switching signal TR1 is turned off and the first switching signal SW1 is low. On at the level. In addition, when the second switching transistor TR2 is N-type, the second switching signal SW2 is turned on when the high level is high and the second switching signal SW2 is turned low. Off at low level.

Referring to the timing diagram, when the first switching signal SW1 is changed from the high level to the low level, that is, the output gain in the period in which the P-type first switching transistor TR1 is kept in the on state is ( -R1 / R6).

Subsequently, when the first switching signal SW1 is switched from the low level to the high level, the first switching transistor TR1 is turned off to amplify the signal input to the inverting input terminal (−) of the inverting amplifier AMP. The gain is switched to-(R1 + R2) / (R6).

That is, in the period in which the first switching transistor TR1 is turned off by the first switching signal SW1, the synthesis resistance for amplification gain is changed to (R1 + R2) larger than that of (R1). The output gain of the inverting amplifier AMP is increased when the common voltage rises, and the driving gain is overdriven when the common voltage is raised by the increased output gain, thereby charging for (T) hours. The time reduction effect is obtained.

Next, the common electrode DC level of the liquid crystal driving voltage VLCD input to the non-inverting input terminal (+) of the inverting amplifier AMP may change the second switching signal SW2 from a low level to a high level. Is changed from {R4 × VLCD / (R3 + R4)} to {Rb × VLCD / (R3 + Rb)}, where Rb = (R4 × R5) / (R4 + R5).

That is, when the N-type second switching transistor TR2 is turned on, the value of the fourth resistor R4 that the second switching transistor TR2 has in the off period is (R4 × R5) / (R4 + As the resistance value decreases because it is replaced by the value of R5), overdriving occurs that the applied DC level drops rapidly, and thus, the charging time to the normal level of the inverted state is reduced by (T) time when the common voltage falls. You get an effect.

Thereafter, the DC level is increased again when the second switching signal SW2 is changed from a high level to a low level. As a result, as shown in FIG. 7, the overdriven common voltage swing output may be obtained.

The circuit of the above-described second embodiment may also use different types of transistors or transistors of the same type as the switching transistor configuration. Accordingly, each switching signal for on / off control of each switching transistor is also overdriven in the above-described manner. Naturally, the timing diagram of FIG. 9 is an example of an N-type transistor as the first switching transistor TR1 in the above-described first and second embodiments. Illustrates first and second switching signals that are appropriately changed and input when a P-type transistor is configured as the second switching transistor.

Third embodiment

Fig. 10 is an equivalent circuit diagram showing a third embodiment of a common voltage generating circuit according to the present invention, in which an inverting amplifier AMP, a push-pull circuit section P / P, and a first type of the same type are used as operational elements. A common voltage generation circuit including a second switching transistor TR1 (TR2), a plurality of resistors R1 to R6, and a capacitor CF is shown.

Here, the operation element AMP performs an inverted amplification, and is an operational amplifier OP-AMP having an inverting input terminal (-), a non-inverting input terminal (+), and an output terminal, and controls for a swing output of a common voltage. It receives a signal CNT.

The push-pull circuit part P / P is configured to receive a driving voltage VLCD and further increase a swing speed of the common voltage Vcom. One or more transistors are combined and further connected to the ground terminal GND. It is a configuration.

In addition, the fourth resistor R4, which is preferably composed of variable resistance, is configured to adjust a block dim appearing in the image by adjusting the resistance value.

The capacitor CF is to prevent the noise or the ripple voltage from being fed back to the input terminal of the operational element AMP and then amplified. The noise fed back to the input terminal of the operational element AMP flows into the panel to provide the entire screen. This is because wave noise is generated.

The control signal CNT is a square wave input to the inverting input terminal (-) of the inverting amplifier AMP with a half cycle of 16.7 ms, and has a level such that the common voltage Vcom output through the circuit has a change in level. Swing will be performed. The voltage difference between the high level and the low level of the control signal CNT is about 3.3V.

The first switching signal SW1 and the second switching signal SW2 are square waves, and voltage signals for driving each switching transistor are applied at the time when the control signal CNT rises and falls, respectively. In accordance with the above, the conversion of the resistance synthesis relationship between the third resistor R3, the fourth resistor R4, the fifth resistor R5, and the sixth resistor R6 is performed to obtain a steady state response time according to the swing of the common voltage. To control.

Hereinafter, the driving and effects of the common voltage generation circuit according to the third embodiment of the present invention will be described with reference to the driving timing diagram of FIG. 6 and the output graph of FIG. 7. The same as the first and second embodiments described above, except that the common voltage level swing is performed through the DC level conversion of the driving voltage input to the non-inverting input terminal of the operation element.

First, when the first switching transistor TR1 and the second switching transistor TR2 configured in the circuit are the same type, for example, all of them are N-types as shown, the control signal and the switching signal timing as shown in FIG. It is driven through and is turned on when each switching signal SW1 (SW2) is at a high level, and turned off when each switching signal SW1 (SW2) is at a low level.

Referring to the timing diagram, in the section in which the first switching signal SW1 is in the low level state, the output level is (R4 x VLCD) / in the section in which the N-type first switching transistor TR1 is in the off state. It is represented by (R3 + R4).

Subsequently, when the first switching signal SW1 is switched to the high level, the first switching transistor TR1 is turned on and the DC level input to the non-inverting input terminal (+) of the inverting amplifier AMP is (R4). × VLCD) / (Rh + R4) {where Rh = (R3 // R5), i.e. Rh = (R3 × R5) / (R3 + R5)}, to achieve high DC level input and increase The output is overdried when the common voltage rises, thereby reducing the charging time by (T) time.

Subsequently, when the first switching signal SW1 is switched to the low level again, the DC level becomes low.

Next, in the section in which the second switching signal SW2 is in the low state, the output level is (R4 × VLCD) / (R3 + because the N-type second switching transistor TR2 is in the off state. R4).

Thereafter, when the second switching signal SW2 is switched to the high level, the second switching transistor TR2 is turned on and the DC level input to the non-inverting input terminal (+) of the inverting amplifier AMP is (Rm). × VLCD) / (R3 + Rm), {where Rm = (R4 // R6), that is, Rh = (R4 × R6) / (R4 + R6)}, resulting in a low DC level due to the resistance-voltage distribution relationship. The lowered DC level is input to the non-inverting input terminal, so that the driving time is reduced by over driving when the common voltage falls.

Thereafter, when the second switching signal SW2 is switched to the low level again, the DC level becomes high. As a result, as shown in FIG. 7, the overdriven common voltage swing output may be obtained.

In the above-described third embodiment, the switching transistors may be configured as all P-type transistors. Accordingly, each switching signal for on / off control of each switching transistor may also be overdriven by the above-described method. Naturally, it should be changed as shown in the timing diagram of FIG.

The common voltage generation circuit according to the present invention as described above further adds a separate resistance to the charge time delay phenomenon in the common voltage swing generated by a load of a capacitor and a resistor configured to prevent a conventional noise input, and the switching connection thereof. The delay time is reduced by controlling the gain that is inverted and amplified by changing the resistance value.

In this method, since there is no delay of the charging time in the steady state in the swing type common voltage application driving, the data can be positively driven, thereby improving the quality of image quality.

1 is a view showing a conventional active matrix liquid crystal display device

2 is an equivalent circuit diagram showing a conventional common voltage generating circuit.

3 is a diagram illustrating a swing control signal waveform in a common voltage generation circuit of a conventional swing method.

4 is a diagram illustrating a common voltage swing waveform output from the common voltage generator of FIG. 2.

5 is an equivalent circuit diagram showing a circuit of a first embodiment of a common voltage generating circuit according to the present invention.

6 is a signal waveform diagram showing a signal applied to a common voltage generation circuit according to a first embodiment of the present invention;

7 is a diagram illustrating a common voltage swing waveform output through a common voltage generation circuit according to a first embodiment of the present invention.

8 is an equivalent circuit diagram showing a circuit of a second embodiment of a common voltage generating circuit according to the present invention.

9 is a control and switching signal timing diagram for driving when the N-type first switching transistor and the P-type second switching transistor are configured in the first and second embodiments of the common voltage generation circuit according to the present invention.

10 is an equivalent circuit diagram showing a circuit of a third embodiment of a common voltage generating circuit according to the present invention.

<Brief description of the main parts of the drawing>

VLCD: Liquid Crystal Driving Voltage Vcom: Common Voltage

AMP: Inverting amplifier CNT: Control signal

SW1, SW2: first and second switching signals

TR1, TR2: first and second switching transistors

Claims (30)

A computing element having an inverting input terminal, a non-inverting input terminal, and an output terminal; A push-pull circuit unit which is driven by receiving an output of the operation element and outputs a common voltage through a common voltage output terminal; A capacitor configured between an inverting input terminal of said computing element and a common voltage output terminal of said push-pull circuit portion; A first resistor configured between the inverting input terminal of the computing element and the common voltage output terminal of the push-pull circuit portion; A second resistor having one end connected to the inverting input terminal of the operation element; A first switching transistor connected to the other end of the second resistor and the common voltage output terminal of the push-pull circuit unit and driven by receiving a first switching signal; A third resistor having one end connected to a non-inverting input terminal of the operation element and a driving voltage input to the other end; A fourth resistor configured between a ground terminal and a non-inverting input terminal of the computing element; A fifth resistor whose one end is connected to the non-inverting input terminal of the computing element; A second switching transistor configured between the other end of the fifth resistor and the ground terminal and driven by receiving a second switching signal; A sixth resistor having one end connected to the inverting input terminal of the operation element and a control signal inputted to the other end Common voltage generating circuit including The method according to claim 1, The operational element is a common voltage generator, characterized in that the operational amplifier The method according to claim 1, The push-pull circuit part includes a common voltage generation circuit comprising one or more transistors. The method according to claim 1, The push-pull circuit part receives a driving voltage and is connected to a ground terminal. The method according to claim 1, The fourth resistor is a common resistor, characterized in that the variable resistor The method according to claim 1, The control signal is a square wave, characterized in that the common voltage generating circuit The method according to claim 1 or 6, The control signal has a half period of 16.7 ms, the common voltage generating circuit The method according to claim 1, Wherein the first switching signal switches an operating state of the first switching transistor at the time when the control signal rises. The method according to claim 1, The second switching signal is a common voltage generation circuit, characterized in that for switching the operation state of the second switching transistor at the time of falling of the control signal. The method according to claim 1, Each switching transistor is a P-type or N-type transistor, characterized in that the common voltage generating circuit A computing element having an inverting input terminal, a non-inverting input terminal, and an output terminal; A push-pull circuit unit which receives and drives an output of the operation element and outputs a common voltage through a common voltage output terminal; A capacitor configured between an inverting input terminal of said computing element and a common voltage output terminal of said push-pull circuit portion; A first resistor having one end connected to the inverting input terminal of the operation element; A second resistor having one end connected in series with the first resistor and the other end connected with the common voltage output terminal; A first switching transistor configured between both ends of the second resistor and driven by receiving a first switching signal; A third resistor having one end connected to a non-inverting input terminal of the operation element and a driving voltage input to the other end; A fourth resistor configured between a ground terminal and a non-inverting input terminal of the computing element; A fifth resistor whose one end is connected to the non-inverting input terminal of the computing element; A second switching transistor configured between the other end of the fifth resistor and the ground terminal and driven by receiving a second switching signal; A sixth resistor having one end connected to the inverting input terminal of the operation element and a control signal inputted to the other end Common voltage generating circuit including The method of claim 11, The operational element is a common voltage generator, characterized in that the operational amplifier The method of claim 11, The push-pull circuit part includes a common voltage generation circuit comprising one or more transistors. The method of claim 11, The push-pull circuit part receives a driving voltage and is connected to a ground terminal. The method of claim 11, The fourth resistor is a common resistor, characterized in that the variable resistor The method of claim 11, The control signal is a square wave, characterized in that the common voltage generating circuit The method according to claim 11 or 16, The control signal has a half period of 16.7 ms, the common voltage generating circuit The method of claim 11, The first switching signal converts an operating state of the first switching transistor at the time when the control signal rises. The method of claim 11, The second switching signal is a common voltage generation circuit, characterized in that for switching the operation state of the second switching transistor at the time of falling of the control signal. The method of claim 11, Each switching transistor is a P-type or N-type transistor, characterized in that the common voltage generating circuit A computing element having an inverting input terminal, a non-inverting input terminal, and an output terminal; A push-pull circuit unit which is driven by receiving an output of the operation element and outputs a common voltage through a common voltage output terminal; A capacitor configured between an inverting input terminal of said computing element and a common voltage output terminal of said push-pull circuit portion; A first resistor configured between the inverting input terminal of the computing element and the common voltage output terminal of the push-pull circuit portion; A second resistor having one end connected to an inverting input terminal of the operation element and a control signal input to the other end; A third resistor having one end connected to a non-inverting input terminal of the operation element and a driving voltage input to the other end; A fourth resistor configured between a ground terminal and a non-inverting input terminal of the computing element; A fifth resistor to which the driving voltage is input; A first switching transistor configured between the other end of the fifth resistor and the non-inverting input end of the arithmetic element and driven by receiving a first switching signal; A sixth resistor having one end connected to the non-inverting input terminal of the operation element; A second switching transistor configured between the other end of the sixth resistor and a ground terminal and driven by receiving a second switching signal; Common voltage generation circuit including The method of claim 21, The operational element is a common voltage generator, characterized in that the operational amplifier The method of claim 21, The push-pull circuit part includes a common voltage generation circuit comprising one or more transistors. The method of claim 21, The push-pull circuit part receives a driving voltage and is connected to a ground terminal. The method of claim 21, The fourth resistor is a common resistor, characterized in that the variable resistor The method of claim 21, The control signal is a square wave, characterized in that the common voltage generating circuit The method of claim 21 or 26, The control signal has a half period of 16.7 ms, the common voltage generating circuit The method of claim 21, The first switching signal switches the operating state of the first switching transistor at the time when the control signal rises. The method of claim 21, The second switching signal is a common voltage generation circuit, characterized in that for switching the operation state of the second switching transistor at the time of falling of the control signal. The method of claim 21, Each switching transistor is a P-type or N-type transistor, characterized in that the common voltage generating circuit