CN213879264U

CN213879264U - Overvoltage protection circuit

Info

Publication number: CN213879264U
Application number: CN202022746956.XU
Authority: CN
Inventors: 宋永辉
Original assignee: CIG Shanghai Co Ltd
Current assignee: CIG Shanghai Co Ltd
Priority date: 2020-11-24
Filing date: 2020-11-24
Publication date: 2021-08-03
Anticipated expiration: 2030-11-24

Abstract

The utility model discloses an overvoltage crowbar, including resistance R1, resistance R2, resistance R3 and three-terminal shunt regulator U1, resistance R1's one end is connected with the power, the other end with three-terminal shunt regulator U1's reference pole is connected, resistance R2's one end with three-terminal shunt regulator U1's reference pole is connected, other end ground connection, resistance R3's one end and power are connected, the other end with three-terminal shunt regulator U1's negative pole is connected, three-terminal shunt regulator U1's positive pole ground connection, three-terminal shunt regulator U1's negative pole is connected with resistance R4, resistance R4's the parallelly connected MOS pipe Q1's of the other end grid and resistance R5, resistance R5's other end ground connection. After the monitored voltage is compared with the reference voltage through the three-terminal parallel voltage regulator, a high and low level is generated, the on-off of the monitored voltage is carried out in a no-load mode through the high and low level, and a universal electronic device is adopted, so that the operation is stable, the precision is high, and the cost is low.

Description

Overvoltage protection circuit

Technical Field

The utility model relates to an overvoltage protection technical field especially relates to an overvoltage crowbar.

Background

Because the input power of some products requires overvoltage protection and certain precision requirement, the precision is not high although the voltage regulator tube is low in price, and the requirement cannot be met. Therefore, it is necessary to provide a further solution to the above problems.

SUMMERY OF THE UTILITY MODEL

The utility model aims at providing an overvoltage crowbar to overcome the not enough that exists among the prior art.

In order to solve the technical problem, the technical scheme of the utility model is that:

the utility model provides an overvoltage crowbar, includes resistance R1, resistance R2, resistance R3 and three-terminal shunt regulator U1, resistance R1's one end is connected with the power, the other end with three-terminal shunt regulator U1's reference pole is connected, resistance R2's one end with three-terminal shunt regulator U1's reference pole is connected, and the other end ground connection, resistance R3's one end is connected with the power, the other end with three-terminal shunt regulator U1's negative pole is connected, three-terminal shunt regulator U1's positive pole ground connection, three-terminal shunt regulator U1's negative pole is connected with resistance R4, resistance R4's the grid and the resistance R5 of the parallelly connected MOS pipe Q1 of the other end, resistance R5's the other end ground connection.

In a preferred embodiment of the present invention, the model number of the three-terminal shunt regulator U1 is TLV 431.

In a preferred embodiment of the present invention, the MOS transistor Q1 is an NMOS transistor.

In a preferred embodiment of the present invention, a capacitor C4 is connected between the resistor R1 and the resistor R3.

The utility model discloses a preferred embodiment still includes zener diode D1, zener diode D1's negative pole with three terminal shunt regulator U1's reference pole is connected, and the positive pole ground connection.

The utility model discloses a preferred embodiment still includes zener diode D2, zener diode D2's negative pole connect the negative pole of three terminal shunt regulator U1 with resistance R4, positive ground.

In a preferred embodiment of the present invention, the device further comprises a MOS transistor Q2, the source and the gate of the MOS transistor Q2 are connected to the drain of the MOS transistor Q1, and the drain of the MOS transistor Q2 is grounded.

In a preferred embodiment of the present invention, the three-terminal shunt regulator U1 has a model number TLV 431B.

In a preferred embodiment of the present invention, a resistor R7 and a resistor R6 are connected in series between the source of the MOS transistor Q2 and the drain of the MOS transistor Q1.

In a preferred embodiment of the present invention, a resistor R8 and a resistor R9 are connected in series between the gate of the MOS transistor Q2 and the drain of the MOS transistor Q1.

Compared with the prior art, the beneficial effects of the utility model are that:

the utility model discloses a three-terminal shunt regulator's voltage reference comparison function is compared the back by monitoring voltage rather than reference voltage, and three-terminal shunt regulator produces a high-low level, comes the no-load break-make by monitoring voltage through this high-low level, adopts general electron device, and the operation is stable, and the precision is high, and is with low costs.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments described in the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

Fig. 1 is a circuit diagram of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, but the present invention may be practiced in other ways than those specifically described herein, and therefore the scope of the present invention is not limited by the specific embodiments disclosed below.

In the description of the present invention, it is to be understood that the terms "center", "longitudinal", "lateral", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like indicate orientations or positional relationships based on those shown in the drawings, and are used only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore, should not be construed as limiting the scope of the invention. Furthermore, the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first," "second," etc. may explicitly or implicitly include one or more of that feature. In the description of the invention, unless otherwise specified, "a plurality" means two or more.

In the description of the present invention, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present invention can be understood by those of ordinary skill in the art through specific situations.

As shown in fig. 1, the overvoltage protection circuit comprises a resistor R1, a resistor R2, a resistor R3 and a three-terminal parallel regulator U1. One end of the resistor R1 is connected with a power supply, the other end of the resistor R1 is connected with a reference electrode of the three-terminal shunt regulator U1, one end of the resistor R2 is connected with the reference electrode of the three-terminal shunt regulator U1, the other end of the resistor R3 is grounded, one end of the resistor R3 is connected with the power supply, the other end of the resistor R3 is connected with a cathode of the three-terminal shunt regulator U1, an anode of the three-terminal shunt regulator U1 is grounded, a cathode of the three-terminal shunt regulator U1 is connected with the resistor R4, the other end of the resistor R4 is connected with a grid of the MOS transistor Q1 and the resistor R5 in parallel, and the other end of the resistor R5 is grounded. The model number of the three-terminal parallel voltage stabilizer U1 is TLV431, and preferably TLV431B is adopted, so that the control accuracy is further improved to 0.5%.

The MOS transistor Q1 is preferably an NMOS transistor. And a capacitor C4 is connected between the resistor R1 and the resistor R3 to play a role in interference leakage.

The overvoltage protection circuit further comprises a voltage stabilizing diode D1, the negative electrode of the voltage stabilizing diode D1 is connected with the reference electrode of the three-terminal parallel regulator U1, and the positive electrode of the voltage stabilizing diode is grounded. The circuit further comprises a voltage stabilizing diode D2, the negative electrode of the voltage stabilizing diode D2 is connected with the cathode of the three-terminal shunt regulator U1 and the resistor R4, and the positive electrode of the voltage stabilizing diode D2 is grounded. The voltage stabilizing diodes D1 and D2 play a role in stabilizing voltage.

The circuit can further comprise a MOS tube Q2, the source electrode and the gate electrode of the MOS tube Q2 are connected with the drain electrode of the MOS tube Q1, and the drain electrode of the MOS tube Q2 is grounded. The on-off of the MOS tube Q2 is controlled by the on-off of the MOS tube Q1. A resistor R7 and a resistor R6 are connected in series between the source of the MOS transistor Q2 and the drain of the MOS transistor Q1. A resistor R8 and a resistor R9 are connected in series between the gate of the MOS transistor Q2 and the drain of the MOS transistor Q1. The MOS transistor Q2 is preferably a PMOS transistor. The MOS transistor Q1 only plays a role of switching, and the MOS transistor Q2 not only plays a role of switching, but also is provided with large current on the main circuit. And thus the two model choices are different.

The utility model discloses can specifically be used for controlling input power supply 12V's overvoltage protection, through divider resistance R1, R2 produces a voltage and does the comparison with TLV431B reference voltage, can specifically set for overvoltage protection point and be 12.91V, be less than 12.91V when input voltage 12V _ IN, TLV431B (U1)'s negative pole produces a 6V's high level, this high level is again through R4, R5's a partial pressure control MOS pipe Q1 switches on, Q1 switches on the back and then control switching on of MOS pipe Q2, input power supply 12V _ IN switches on like this. When the input power supply 12V _ IN is higher than 12.91V, the cathode of the TLV431B (U1) generates a low level of 1V, and the low level of 1V generates a divided voltage of 0.6 by the divided voltage of R4 and R5, and the low voltage turns off the MOS transistor Q1, thereby controlling the turn-off of the MOS transistor Q2, and finally completing the overvoltage protection function of the input power supply 12V _ IN. The utility model discloses be particularly useful for router equipment.

To sum up, the utility model discloses a three-terminal shunt regulator's voltage reference comparison function is compared the back by monitoring voltage rather than reference voltage, and three-terminal shunt regulator produces a high-low level, comes the no-load break-make by monitoring voltage through this high-low level, adopts general electron device, and the operation is stable, and the precision is high, and is with low costs.

It is obvious to a person skilled in the art that the invention is not restricted to details of the above-described exemplary embodiments, but that it can be implemented in other specific forms without departing from the spirit or essential characteristics of the invention. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.

Furthermore, it should be understood that although the present description refers to embodiments, not every embodiment may contain only a single embodiment, and such description is for clarity only, and those skilled in the art should integrate the description, and the embodiments may be combined as appropriate to form other embodiments understood by those skilled in the art.

Claims

1. The overvoltage protection circuit is characterized by comprising a resistor R1, a resistor R2, a resistor R3 and a three-terminal parallel regulator U1, wherein one end of the resistor R1 is connected with a power supply, the other end of the resistor R1 is connected with a reference electrode of a three-terminal parallel regulator U1, one end of the resistor R2 is connected with the reference electrode of the three-terminal parallel regulator U1, the other end of the resistor R3 is grounded, one end of the resistor R3 is connected with the power supply, the other end of the resistor R3 is connected with a cathode of the three-terminal parallel regulator U1, an anode of the three-terminal parallel regulator U1 is grounded, a cathode of the three-terminal parallel regulator U1 is connected with the resistor R4, the other end of the resistor R4 is connected with a grid of a MOS transistor Q1 and the resistor R5 in parallel, and the other end of the resistor R5 is grounded.

2. The overvoltage protection circuit of claim 1, wherein the three-terminal shunt regulator U1 is model number TLV 431.

3. The overvoltage protection circuit of claim 1, wherein the MOS transistor Q1 is an NMOS transistor.

4. The overvoltage protection circuit of claim 1, wherein a capacitor C4 is connected between the resistor R1 and the resistor R3.

5. The overvoltage protection circuit of claim 1, further comprising a zener diode D1, wherein a cathode of the zener diode D1 is connected to a reference electrode of the three-terminal shunt regulator U1, and an anode of the zener diode D1 is grounded.

6. The overvoltage protection circuit of claim 1, further comprising a zener diode D2, wherein a cathode of the zener diode D2 is connected to a cathode of the three-terminal shunt regulator U1 and the resistor R4, and an anode thereof is grounded.

7. The overvoltage protection circuit of claim 1, further comprising a MOS transistor Q2, wherein the source and gate of the MOS transistor Q2 are connected to the drain of MOS transistor Q1, and the drain of the MOS transistor Q2 is grounded.

8. The overvoltage protection circuit of claim 2, wherein the three-terminal shunt regulator U1 is model number TLV 431B.

9. The overvoltage protection circuit of claim 7, wherein a resistor R7 and a resistor R6 are connected in series between the source of the MOS transistor Q2 and the drain of the MOS transistor Q1.

10. The overvoltage protection circuit of claim 7, wherein a resistor R8 and a resistor R9 are connected in series between the gate of the MOS transistor Q2 and the drain of the MOS transistor Q1.