CN210958152U - Novel ultra-wide voltage input three-level circuit - Google Patents
Novel ultra-wide voltage input three-level circuit Download PDFInfo
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- CN210958152U CN210958152U CN201922331343.7U CN201922331343U CN210958152U CN 210958152 U CN210958152 U CN 210958152U CN 201922331343 U CN201922331343 U CN 201922331343U CN 210958152 U CN210958152 U CN 210958152U
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Abstract
The utility model discloses a novel three level circuit of super wide pressure input belongs to the switching power supply field, voltage input VIN before the steady voltage, public earthing terminal GND, resistance R1, first electric capacity C1, second electric capacity C2, third electric capacity C3, fourth electric capacity C4, first winding TIA, second winding TIAG, first electronic switch component Q1, second electronic switch component Q2, first electronic switch component Q1 is provided with an, b and C end, second electronic switch component Q2 is provided with e, d and f end; a voltage-stabilizing front voltage input end VIN is respectively and electrically connected with an input end of the first capacitor C1 and an input end of the first winding TIA; the output end of the first capacitor C1 is electrically connected with the input end of the second capacitor C2, and the output end of the second capacitor C2 is electrically connected with the input end of the second winding TIAG and the input end of the third capacitor C3 respectively; the output end of the third capacitor C3 is electrically connected with the input end of the fourth capacitor C4; the requirement of high power output by three-level input high voltage can be met.
Description
Technical Field
The utility model relates to a switching power supply field, more specifically say, relate to a novel three level circuit of super wide voltage input.
Background
The switching power supply is a power supply which utilizes modern power electronic technology to control the on-off time ratio of an activated switching tube and maintain stable output voltage, generally comprises a Pulse Width Modulation (PWM) control IC and a MOSFET, and is continuously innovated along with the development and innovation of the power electronic technology.
The three-level circuit can not simultaneously achieve high withstand voltage and large capacity with very low cost due to the process and technical limitations of the electrolytic capacitor, so the three-level design is often limited to meet the requirement of high input voltage due to the problem of capacitor capacity or capacitor withstand voltage.
SUMMERY OF THE UTILITY MODEL
1. Technical problem to be solved
To the problem that exists among the prior art, the utility model aims to provide a novel super wide presses input three-level circuit, and it can satisfy the powerful demand of three-level input high-voltage output.
2. Technical scheme
In order to solve the above problem, the utility model adopts the following technical scheme:
a novel ultra-wide voltage input three-level circuit comprises a voltage input end VIN before voltage stabilization, a common ground end GND, a resistor R1, a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a first winding TIA, a second winding TIAG, a first electronic switch element Q1 and a second electronic switch element Q2, wherein the first electronic switch element Q1 is provided with ends a, b and C, and the second electronic switch element Q2 is provided with ends e, d and f;
the voltage-stabilizing front voltage input end VIN is respectively and electrically connected with an input end of a first capacitor C1 and an input end of a first winding TIA;
the output end of the first capacitor C1 is electrically connected with the input end of a second capacitor C2, and the output end of the second capacitor C2 is electrically connected with the input end of a second winding TIAG and the input end of a third capacitor C3 respectively;
the output end of the third capacitor C3 is electrically connected with the input end of a fourth capacitor C4;
the output end of the first winding TIA is electrically connected with the a end of a first electronic switching element Q1, and the b end of the first electronic switching element Q1 is electrically connected with the input end of a second winding TIAG;
the output end of the second winding TIAG is electrically connected with the e end of a second electronic switching element Q2, and the d end of the second electronic switching element Q2 is electrically connected with the output end of a resistor R1;
the output end of the resistor R1 and the output end of the fourth capacitor C4 are both electrically connected with a common ground end GND, so that the requirement of three-level input high-voltage output high power can be met.
As a preferable embodiment of the present invention, the first capacitor C1 is an electrolytic capacitor.
As a preferable embodiment of the present invention, the second capacitor C2 is an electrolytic capacitor.
As a preferable embodiment of the present invention, the third capacitor C3 is an electrolytic capacitor.
As a preferable embodiment of the present invention, the fourth capacitor C4 is an electrolytic capacitor.
As a preferable aspect of the present invention, the first electronic switching element Q1 is an N-MOS transistor.
As a preferable aspect of the present invention, the second electronic switching element Q2 is an N-MOS transistor.
3. Advantageous effects
Compared with the prior art, the utility model has the advantages of:
the withstand voltage value of the capacitor is increased by using the capacitors in series connection, the first capacitor C1 and the second capacitor C2 are connected in series as shown in fig. 1, the third capacitor C3 and the fourth capacitor C4 are connected in series, the withstand voltage value of the capacitor can be increased to twice of that of the original single capacitor easily, and the capacitor has large capacity which can be well realized at low voltage, so that the capacitor series circuit in the circuit can meet the requirement of inputting high voltage and outputting high power at three levels.
Drawings
Fig. 1 is a circuit diagram of the present invention.
Detailed Description
The technical solution in the embodiment of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiment of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all embodiments, and all other embodiments obtained by those skilled in the art without any inventive work are within the scope of the present invention based on the embodiments of the present invention.
In the description of the present invention, it should be noted that the terms "upper", "lower", "inner", "outer", "top/bottom", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplification of description, but do not indicate or imply that the device or element referred to must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present invention, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted", "provided", "sleeved/connected", "connected", and the like are to be understood in a broad sense, such as "connected", which may be fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present invention can be understood in specific cases to those skilled in the art.
Example (b):
a novel ultra-wide voltage input three-level circuit comprises a voltage input end VIN before voltage stabilization, a common ground end GND, a resistor R1, a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a first winding TIA, a second winding TIAG, a first electronic switch element Q1 and a second electronic switch element Q2, wherein the first electronic switch element Q1 is provided with ends a, b and C, and the second electronic switch element Q2 is provided with ends e, d and f;
a voltage-stabilizing front voltage input end VIN is respectively and electrically connected with an input end of the first capacitor C1 and an input end of the first winding TIA;
the output end of the first capacitor C1 is electrically connected with the input end of the second capacitor C2, and the output end of the second capacitor C2 is electrically connected with the input end of the second winding TIAG and the input end of the third capacitor C3 respectively;
the output end of the third capacitor C3 is electrically connected with the input end of the fourth capacitor C4;
the output end of the first winding TIA is electrically connected with the end a of a first electronic switching element Q1, and the end b of the first electronic switching element Q1 is electrically connected with the input end of a second winding TIAG;
the output end of the second winding TIAG is electrically connected with the e end of the second electronic switching element Q2, and the d end of the second electronic switching element Q2 is electrically connected with the output end of the resistor R1;
the output terminal of the resistor R1 and the output terminal of the fourth capacitor C4 are both electrically connected to the common ground GND.
Preferably, the first capacitor C1, the second capacitor C2, the third capacitor C3 and the fourth capacitor C4 are all electrolytic capacitors, and the first electronic switching element Q1 and the second electronic switching element Q2 are all N-MOS transistors.
The working principle is as follows: the withstand voltage value of the capacitor is increased by using the capacitors in series connection, the first capacitor C1 and the second capacitor C2 are connected in series as shown in fig. 1, the third capacitor C3 and the fourth capacitor C4 are connected in series, the withstand voltage value of the capacitor can be increased to twice of that of the original single capacitor easily, and the capacitor has large capacity which can be well realized at low voltage, so that the capacitor series circuit in the circuit can meet the requirement of inputting high voltage and outputting high power at three levels.
The above description is only the preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can substitute or change the technical solution and the improvement concept of the present invention within the technical scope disclosed in the present invention.
Claims (7)
1. The utility model provides a novel three level circuit of super wide voltage input which characterized in that: the voltage stabilizing circuit comprises a voltage stabilizing front voltage input end (VIN), a common ground end (GND), a resistor (R1), a first capacitor (C1), a second capacitor (C2), a third capacitor (C3), a fourth capacitor (C4), a first winding (TIA), a second winding (TIAG), a first electronic switch element (Q1) and a second electronic switch element (Q2), wherein the first electronic switch element (Q1) is provided with ends a, b and C, and the second electronic switch element (Q2) is provided with ends e, d and f;
the voltage-stabilizing front voltage input end (VIN) is electrically connected with the input end of the first capacitor (C1) and the input end of the first winding (TIA) respectively;
the output end of the first capacitor (C1) is electrically connected with the input end of a second capacitor (C2), and the output end of the second capacitor (C2) is electrically connected with the input end of a second winding (TIAG) and the input end of a third capacitor (C3) respectively;
the output end of the third capacitor (C3) is electrically connected with the input end of a fourth capacitor (C4);
the output end of the first winding (TIA) is electrically connected with the a end of a first electronic switching element (Q1), and the b end of the first electronic switching element (Q1) is electrically connected with the input end of a second winding (TIAG);
the output end of the second winding (TIAG) is electrically connected with the e end of a second electronic switching element (Q2), and the d end of the second electronic switching element (Q2) is electrically connected with the output end of a resistor (R1);
the output end of the resistor (R1) and the output end of the fourth capacitor (C4) are both electrically connected with a common Ground (GND).
2. The novel ultra-wide voltage input three-level circuit according to claim 1, characterized in that: the first capacitor (C1) is an electrolytic capacitor.
3. The novel ultra-wide voltage input three-level circuit according to claim 1, characterized in that: the second capacitor (C2) is an electrolytic capacitor.
4. The novel ultra-wide voltage input three-level circuit according to claim 1, characterized in that: the third capacitor (C3) is an electrolytic capacitor.
5. The novel ultra-wide voltage input three-level circuit according to claim 1, characterized in that: the fourth capacitor (C4) is an electrolytic capacitor.
6. The novel ultra-wide voltage input three-level circuit according to claim 1, characterized in that: the first electronic switching element (Q1) is an N-MOS tube.
7. The novel ultra-wide voltage input three-level circuit according to claim 1, characterized in that: the second electronic switching element (Q2) is an N-MOS tube.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201922331343.7U CN210958152U (en) | 2019-12-23 | 2019-12-23 | Novel ultra-wide voltage input three-level circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201922331343.7U CN210958152U (en) | 2019-12-23 | 2019-12-23 | Novel ultra-wide voltage input three-level circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN210958152U true CN210958152U (en) | 2020-07-07 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201922331343.7U Active CN210958152U (en) | 2019-12-23 | 2019-12-23 | Novel ultra-wide voltage input three-level circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN210958152U (en) |
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2019
- 2019-12-23 CN CN201922331343.7U patent/CN210958152U/en active Active
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