CN213844127U - 1553 transceiving driving circuit for half-duplex high-speed transmission - Google Patents
1553 transceiving driving circuit for half-duplex high-speed transmission Download PDFInfo
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- CN213844127U CN213844127U CN202120037805.9U CN202120037805U CN213844127U CN 213844127 U CN213844127 U CN 213844127U CN 202120037805 U CN202120037805 U CN 202120037805U CN 213844127 U CN213844127 U CN 213844127U
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Abstract
The utility model provides a 1553 transceiving drive circuit of half-duplex high-speed transmission, a serial communication port, including sending end, receiving end and input/output conversion end, the input/output conversion end adopts 1553 special transformer, the sending end with the receiving end is connected respectively the input BUS _ H and the output BUS _ L of input/output conversion end, the input/output conversion end still be connected with the signal end of 1553B BUS. The utility model relates to an exquisiteness, simple structure adopts discrete device to carry out the circuit and builds, has realized that transmission rate is applicable to 4 Mbps's half-duplex signal transmission transceiver circuit.
Description
Technical Field
The utility model relates to an electronic circuit technical field, in particular to 1553 receiving and dispatching drive circuit of half-duplex high-speed transmission.
Background
The MIL-STD-1553B bus (aircraft interior time division command/response multiplexed data bus) is an avionics system data bus introduced by the united states military in 1978. The 1553B bus transmission adopts a Manchester II code, the transmission mode is a half-duplex mode, and the transmission rate is standard 1 Mbps. The 1553B bus has the advantages of reliable data transmission, high real-time performance, flexible modification, simple and convenient expansion and maintenance and the like, becomes a mature airborne avionics bus through development for many years, and is widely applied to the fields of aviation, aerospace and the like. However, with the development of the times, the requirement of the avionics system on the transmission rate is higher and higher, and the transmission rate of 1Mbps becomes the higher rate of the avionics system. At present, research units in China have requirements on an airborne aviation bus with 4Mbps transmission rate, but the rate of a 1553B bus transceiver in China can only reach 1Mbps, and a transceiver circuit is realized through an integrated chip.
SUMMERY OF THE UTILITY MODEL
In order to solve the problem, the utility model provides a 1553 transceiving drive circuit of half-duplex high-speed transmission. The transmission rate of the half-duplex signal transmission transceiving circuit is suitable for 4Mbps by adopting a discrete device for construction.
The utility model provides a 1553 transmit-receive driving circuit of half-duplex high-speed transmission, the concrete technical scheme is as follows: the circuit comprises a sending end, a receiving end and an input/output conversion end, wherein the sending end and the output end are connected to the input/output conversion end together, and the input/output conversion end is a 1553B special transformer;
the transmitting end is provided with two level signal transmitting units with the same structure, each level signal transmitting unit comprises an MOS (metal oxide semiconductor) tube, a pull-up resistor and a current-limiting resistor, the level signal transmitting end of each level signal transmitting unit is connected with the grid of the MOS tube, the source of the MOS tube is connected with a power end, the pull-up resistor is connected between the source and the grid, and the drain of the MOS tube is connected with the current-limiting resistor;
the receiving end is provided with two level signal output units with the same structure, each level signal output unit comprises a comparison circuit unit and a differential operational amplifier circuit unit, each comparison circuit comprises a high-speed comparator and a series resistor, each differential operational amplifier circuit unit comprises a high-speed differential operational amplifier, a capacitor and a plurality of precise resistors, and the output end of each differential operational amplifier circuit unit is connected with the reverse input end of the corresponding high-speed comparator through the series resistor;
the 1553B special transformer is provided with six pins, coil pins 1 and 3 are respectively connected with the input end and the output end of the transceiver, a coil center tap pin is grounded, pins 4 and 6 are respectively connected with a positive end signal and a negative end signal on a 1553B bus, and a coil center tap pin 5 is connected with the shielding ground of the 1553B bus.
Furthermore, the MOS tube of the level signal sending unit adopts a power transistor with the switching rate of ns resolution.
Further, the positive input ends and the negative input ends of two high-speed differential operational amplifiers in the level signal output unit are respectively connected with a pin 1 and a pin 3 of the transformer through serially connected resistors, wherein the positive input end and the negative input end of the same high-speed differential operational amplifier are connected with different pins.
Furthermore, the positive input end of the high-speed differential operational amplifier is also connected with a feedback resistor which is connected with the ground end.
Furthermore, a feedback resistor is connected between the reverse input end of the high-speed differential operational amplifier and the output end of the differential operational amplifier circuit unit.
Furthermore, a common-mode voltage end of the high-speed differential operational amplifier is connected with a grounding capacitor.
Furthermore, the ratio of the bus connecting end to the transmitting and receiving end coil of the 1553B special transformer is 1.79: 1.
Furthermore, the resistance values of the precision resistors in the same level signal output unit are the same, and the operational amplification factor of the differential operational amplifier circuit unit is set to be 5 or 6 times.
The utility model has the advantages as follows:
a discrete device is adopted to build a transceiving circuit, a circuit transmission mode adopts a half-duplex mode, a power transistor with the switching rate of ns resolution is adopted, a transmitting end and a receiving end share one transformer, signal interference is reduced, the circuit structure design is simple, and the transmission rate is suitable for a 1553 transceiving driving circuit with 4 Mbps.
Drawings
Fig. 1 is a schematic view of the overall structure of the present invention;
fig. 2 is a schematic diagram of the circuit connection structure of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.
An embodiment of the utility model provides a 1553 transceiving drive circuit of half-duplex high-speed transmission, as shown in fig. 1, this circuit includes transmitting terminal, receiving terminal and input/output conversion end, the transmitting terminal with the receiving terminal is connected respectively the input BUS _ H and the output BUS _ L of input/output conversion end, still be connected with the signal end of 1553B BUS of input/output conversion end.
As shown in fig. 2, the input/output conversion terminal adopts a 1553B dedicated transformer, which is denoted as T1, the transmitting terminal and the receiving terminal share a transformer T1, pin 1 and pin 3 of the transformer T1 are respectively connected to an input/output terminal BUS _ H and BUS _ L of a transceiver, that is, the transmitting terminal and the receiving terminal are respectively connected, and a pin 2 of a coil center tap is grounded to GND; pin 4 and pin 6 connect positive terminal signal BUS + and negative terminal signal BUS-on the 1553B BUS respectively, coil center tap pin 5 connects the shielding ground of 1553B BUS, the coil ratio of transformer T1 pins 1 and 3 and pins 4 and 6 is 1: 1.79.
the transmitting terminal comprises two PMOS tubes Q1 and Q2 and 4 resistors R1, R2, R3 and R4 which respectively form two level signal transmitting units with the same structure, the PMOS tubes adopt power transistors with the switching rate of ns resolution, and the level signal transmitting terminals of the two level signal transmitting units receive two TTL level transmitting signals with opposite phases, namely TTL _ TX _ H, TTL _ TX _ L; the TTL _ TX _ H and TTL _ TX _ L level signal transmitting ends are respectively connected to gates of the PMOS transistors Q1 and Q2, sources of the PMOS transistors Q1 and Q2 are connected to the gates, and the sources are respectively pulled up to a 5V power supply end through pull-up resistors R1 and R2 to control on and off of the two PMOS transistors, in this embodiment, resistance values of the pull-up resistors R1 and R2 are both 10K Ω, drains of the PMOS transistors are connected to pins 1 and 3 of the transformer T1 through current limiting resistors R3 and R4, and resistance values of the current limiting resistors R3 and R4 in this embodiment are both 2 Ω.
When the TTL _ TX _ H level is high and the TTL _ TX _ L level is low, the PMOS tube Q1 is cut off, the Q2 is conducted, and current flows from the PMOS tube Q2 through the high-power current-limiting resistor R4 and then flows to the center tap pin 2 of the primary coil through the pin 3 of the 1553B special transformer T1; when the level of TTL _ TX _ L is high, the level of TTL _ TX _ H is low, the PMOS tube Q2 is cut off, the Q1 is conducted, and current flows from the PMOS tube Q1 through the high-power current-limiting resistor R3 and then flows to the center tap pin 2 of the primary coil through the pin 1 of the 1553B special transformer T1.
The receiving end comprises two high-speed comparators COMP1 and COMP2, two high-speed differential operational amplifiers OP1 and OP2, a plurality of precise resistors and capacitors, and two level signal output units with the same structure are respectively formed, wherein each level signal output unit comprises a comparison circuit unit and a differential operational amplifier circuit unit;
the receiving end is connected with a pin 1 and a pin 3 of a secondary coil of the transformer T1 to receive signals BUS _ H and BUS _ L, and outputs two TTL level signals with opposite phases of TTL _ TX _ H and TTL _ TX _ L after passing through a differential operational amplifier circuit and a comparison circuit.
The comparison circuit unit consists of high-speed comparators COMP1 and COMP2, the high-speed comparators are powered by a 5V power supply, a VIN + pin is connected with a reference power supply VREF, and a VIN-pin is connected with the output end VOUT + of the high-speed differential operational amplifier of the differential operational amplifier amplification circuit unit through low-resistance series resistors R5 and R6 respectively;
when the waveform level of the output end VOUT + of the high-speed differential operational amplifier is higher than the reference power source VREF, the level of the output end QA-of the comparator is low (GND); when the waveform level of the output terminal VOUT + of the high-speed differential operational amplifier is lower than the reference power source VREF, the level of the output terminal QA-of the comparator is high (5V).
The differential operational amplifier amplifying circuit unit is composed of high-speed differential operational amplifiers OP1, OP2, a plurality of precision resistors and capacitors, the high-speed differential operational amplifiers are powered by a 5V power supply, a common-mode voltage input end VCOM is connected with a 0.1 muF capacitor and then grounded, feedback resistors R7 and R8 are respectively connected between output ends VOUT + and reverse input ends VIN-of the high-speed differential operational amplifiers OP1 and OP2, the reverse input ends VIN-of the high-speed differential operational amplifiers OP1 and OP2 are respectively connected with series resistors R11 and R13, and the series resistors R11 and R13 are respectively connected with pin 1 and pin 3 of the transformer T1;
positive input ends VIN + of the high-speed differential OP1 and OP2 are respectively connected with feedback resistors R9 and R10 to the ground, the positive input ends VIN + are also respectively connected with resistors R12 and R14 in series, and the resistors R12 and R14 are respectively connected with pin 3 and pin 1 of the transformer T1;
in this embodiment, the precision resistor R7 ═ R8 ═ R9 ═ R10, the resistance is 200 Ω, and the resistance value R11 ═ R12 ═ R13 ═ R14 is 1K Ω, that is, the signal amplification factor of the differential operational amplifier circuit unit is 5.
The transceiving process of the transceiver is as follows:
when a sending end circuit of the transceiver works, pins 1 and 3 of the transformer are used as signal input ends, pins 4 and 6 are used as 1553B bus signal output ends, and the input-output coil ratio is 1: 1.79. After the transmitting waveform of the transceiver is subjected to 1:1.79 transformation ratio by the transformer, Manchester II code waveform differential pair signals BUS + and BUS-with positive and negative levels are formed and output, and the transmitting process is as follows: TTL _ TX _ H/TTL _ TX _ L level signals are input into a transformer T1 and a 1553B bus signal output.
When the receiving end of the transceiver works, the transformer pins 4 and 6 are used as 1553B bus signal input ends, the transformer pins 1 and 3 are used as signal output ends, and the ratio of input and output coils is 1.79: 1. after Manchester II code differential pair signals BUS + and BUS-of the positive and negative levels are attenuated by a transformer in a ratio of 1.79:1, reverse output signals BUS _ H and BUS _ L are formed to a receiving end input interface of the transceiver, and the receiving process is as follows: 1553B bus signal input-transformer T1-TTL _ RX _ H/TTL _ RX _ L terminal level signal output.
The above only is the embodiment of the present invention, not limiting the patent scope of the present invention, all the equivalent structures or equivalent flow changes made by the contents of the specification and the drawings, or direct or indirect applications in other related technical fields, are included in the patent protection scope of the present invention.
Claims (8)
1. A1553 transceiving driving circuit for half-duplex high-speed transmission is characterized by comprising a sending end, a receiving end and an input-output conversion end, wherein the sending end and the output end are connected to the input-output conversion end together, and the input-output conversion end is a 1553B special transformer;
the transmitting end is provided with two level signal transmitting units with the same structure, each level signal transmitting unit comprises an MOS (metal oxide semiconductor) tube, a pull-up resistor and a current-limiting resistor, the level signal transmitting end of each level signal transmitting unit is connected with the grid of the MOS tube, the source of the MOS tube is connected with a power end, the pull-up resistor is connected between the source and the grid, and the drain of the MOS tube is connected with the current-limiting resistor;
the receiving end is provided with two level signal output units with the same structure, each level signal output unit comprises a comparison circuit unit and a differential operational amplifier circuit unit, each comparison circuit comprises a high-speed comparator and a series resistor, each differential operational amplifier circuit unit comprises a high-speed differential operational amplifier, a capacitor and a plurality of precise resistors, and the output end of each differential operational amplifier circuit unit is connected with the reverse input end of the corresponding high-speed comparator through the series resistor;
the 1553B special transformer is provided with six pins, coil pins 1 and 3 are respectively connected with the input end and the output end of the transceiver, a coil center tap pin is grounded, pins 4 and 6 are respectively connected with a positive end signal and a negative end signal on a 1553B bus, and a coil center tap pin 5 is connected with the shielding ground of the 1553B bus.
2. The 1553 transceiving driving circuit of claim 1, wherein the MOS transistor of the level signal transmitting unit adopts a power transistor with a switching rate of ns resolution.
3. The 1553 transceiving driving circuit of claim 2, wherein the forward input terminal and the reverse input terminal of two high-speed differential operational amplifiers in the level signal output unit are respectively connected to pin 1 and pin 3 of the transformer through serially connected resistors, and the forward input terminal and the reverse input terminal of the same high-speed differential operational amplifier are connected to different pins.
4. A 1553 transceiver driving circuit for half-duplex high-speed transmission according to claim 3, wherein the positive input terminal of the high-speed differential operational amplifier is further connected with a feedback resistor connected to ground.
5. The 1553 transceiving drive circuit of claim 4, wherein a feedback resistor is further connected between the inverting input terminal of the high-speed differential operational amplifier and the output terminal of the differential operational amplifier circuit unit.
6. The 1553 transceiving driving circuit of claim 5, wherein a common mode voltage end of the high speed differential operational amplifier is connected with a ground capacitor.
7. A1553 transceiving drive circuit for half-duplex high-speed transmission according to claim 6, wherein the ratio of bus connection end to transceiving end coil of the 1553B dedicated transformer is 1.79: 1.
8. The 1553 transceiving driving circuit of claim 7, wherein the resistances of the precision resistors in the same level signal output unit are the same, and the operational amplification factor of the differential operational amplifier circuit unit is set to be 5 or 6.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202120037805.9U CN213844127U (en) | 2021-01-07 | 2021-01-07 | 1553 transceiving driving circuit for half-duplex high-speed transmission |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202120037805.9U CN213844127U (en) | 2021-01-07 | 2021-01-07 | 1553 transceiving driving circuit for half-duplex high-speed transmission |
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| CN213844127U true CN213844127U (en) | 2021-07-30 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115314069A (en) * | 2022-08-08 | 2022-11-08 | 慷智集成电路(上海)有限公司 | Full-duplex transmitting and receiving circuit, deserializing circuit chip, electronic equipment and vehicle |
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2021
- 2021-01-07 CN CN202120037805.9U patent/CN213844127U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115314069A (en) * | 2022-08-08 | 2022-11-08 | 慷智集成电路(上海)有限公司 | Full-duplex transmitting and receiving circuit, deserializing circuit chip, electronic equipment and vehicle |
| CN115314069B (en) * | 2022-08-08 | 2023-10-13 | 慷智集成电路(上海)有限公司 | Full duplex transmitting and receiving circuit, deserializing circuit chip, electronic equipment and vehicle |
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