CN102664782A - Discrete transceiver circuit suitable for high-speed 1553 bus - Google Patents
Discrete transceiver circuit suitable for high-speed 1553 bus Download PDFInfo
- Publication number
- CN102664782A CN102664782A CN2012101044953A CN201210104495A CN102664782A CN 102664782 A CN102664782 A CN 102664782A CN 2012101044953 A CN2012101044953 A CN 2012101044953A CN 201210104495 A CN201210104495 A CN 201210104495A CN 102664782 A CN102664782 A CN 102664782A
- Authority
- CN
- China
- Prior art keywords
- pin
- output
- transceiver circuit
- mos pipe
- voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Abstract
The invention aims at overcoming the defects in the prior art and provide a discrete transceiver circuit suitable for a high-speed 1553 bus. The discrete transceiver circuit suitable for the high-speed 1553 bus comprises a transmitter and a receiver; wherein the transmitter is connected with a protocol processor to finish the transmitting of a high-speed Manchester code, and the discrete transceiver circuit also comprises a voltage conversion driving circuit, a lateral double-diffused metal-oxide semiconductor (LDMOS) (or N-metal-oxide-semiconductor (NMOS)) and a resistor/capacitor with certain resistance and capacitance. The receiver comprises a first-order active filter, a comparator, a voltage reference and a voltage conversion driving circuit and is connected with the protocol processor through the voltage conversion driving circuit. The discrete transceiver circuit suitable for the high-speed 1553 bus has the advantages that the discrete transceiver circuit achieves the transmission of 1553 bus data at 10Mbps rate by cooperating with the external protocol processor to work, is built by adopting a discrete device without changing the original bus structure and is flexible and convenient in realization.
Description
Technical field
The present invention relates to a kind of transceiver circuit, especially a kind of discrete transceiver circuit of 1553 buses at a high speed that is applicable to.
Background technology
The MIL-STD-1553 data/address bus is widely used in a plurality of fields such as aircraft, Aeronautics and Astronautics because of the special plurality of advantages of its high reliability.Over half a century in the past, MIL-STD-1553 is considered to the current network warfare that we are commonly called as origin always, and it has realized the information sharing and the transmission of various electronics such as transducer, and fundamentally having changed with the U.S. is the mode of operation of representative and alliance thereof.But along with the birth of faster processor, the miniaturization of encapsulation and the innovation of software engineering, the 1553B only data transmission bauds of 1Mbps becomes the bottleneck of information data transmission undoubtedly, and the transmission means of releasing a kind of faster speed is extremely urgent.
Abroad compare early in the research of high speed 1553 buses.As far back as 2006; John Keller has delivered the article that is entitled as " Rebirth of the 1553 databus " on AVIONICS magazine; The high speed 1553 bus Extended 1553 that are responsible for developing by Edgewater and the Hyper 1553 of DDC company have been introduced; They all adopt the mode that is similar to DSL transmission carrier wave; On the basis that does not change original cable and interface, the high frequency low frequency signal is modulated to different channel transfer, realized transmit high-speed signals on original 1553 platforms.In addition; Andrew D.Parker has also delivered the article that is entitled as " Product Focus:High-Speed 1553:Technology Advances Boost Performance " on AVIONICS magazine; Spoken of the 10M system between 1M1553 and 100M1553: enhancement mode bit stream 1553, develop by SAE.
100,000,000 the major defect that is similar to Extended 1553 and Hyper1553 has: though 1 need not change original bus structures and cable, device etc.; But because employing is modulation carrier transmission mode; Transceiver circuit partly need compare big change, and the construction cycle also can increase greatly.
As for the 10M1553 of SAE, according to the article introduction, what its transceiver circuit adopted is the RS485 bus transceiver; Its same some shortcoming that exist: 1, RS485 is a kind of set consensus standard; Agreement has not had the leeway of change, and terminal resistance, line length etc. also have clear and definite regulation, very flexible; Though 2, RS485 can reach the transmission speed of 10Mbps, also can transmit larger distance, be difficult to when high-speed transfer guarantee that the voltage on the bus reaches the 28Vpp that 1553 bus specifications require; 3, adopt the transceiver circuit of RS485; Its transmission medium no longer is 1553 original cables, must change the RS485 client cables into, and EBI also will be changed; This has increased the cost of system development undoubtedly, and will spend long time existing 1553 systems are redeployed.
Summary of the invention
The objective of the invention is to overcome the deficiency that exists in the prior art; A kind of discrete transceiver circuit of 1553 buses at a high speed that is applicable to is provided; Through with the collaborative work of external protocol processor, realize the transmission of 10Mbps speed 1553 bus datas, do not change original bus structures; The employing discrete device is built, and implements flexible.
According to technical scheme provided by the invention; The said discrete transceiver circuit of high speed 1553 buses that is applicable to comprises transmitter and receiver; The Manchester code that said transmitter is accomplished 10Mbps speed sends; Comprise: the input of the voltage transitions drive circuit of the ternary output of band links to each other with protocol processor; First output of the voltage transitions drive circuit of the ternary output of said band is connected with the grid of first power MOS pipe through resistance, and the drain electrode of first power MOS pipe links to each other with the first power MOS pipe grid through electric capacity, and is connected with 1 pin of isolating transformer through resistance; The output of the voltage transitions drive circuit of the ternary output of said band is connected with the grid of second power MOS pipe through resistance, and the drain electrode of second power MOS pipe links to each other with the second power MOS pipe grid through electric capacity, and connects 3 pin of isolating transformer through resistance; The two ends of isolating transformer input coil are respectively 1 pin and 3 pin; The centre tap of input coil is 2 pin; The two ends of isolating transformer output winding are respectively 4 pin and 8 pin, and three centre taps are followed successively by 5 pin, 6 pin, 7 pin, and wherein 3 pin and 8 pin are end of the same name; 2 pin of isolating transformer connect+the 5V power supply, connect load between 5 pin and 7 pin; Said receiver comprises: the positive Manchester code analog signal of bus connects the negative input end of the first single order active filter and the positive input terminal of the second single order active filter, and the negative Manchester code analog signal of bus connects the positive input terminal of the first single order active filter and the negative input end of the second single order active filter; The output of the first single order active filter connects the negative input end of first comparator; The first comparator positive input termination voltage reference; The negative Manchester code digital signal of first comparator negative output terminal output, and the process voltage transitions is delivered to the reception negative signal end of protocol processor; The output of the second single order active filter connects the negative input end of second comparator; The second comparator positive input termination voltage reference; The negative output terminal of second comparator is exported positive Manchester code digital signal, and delivers to the reception positive signal end of protocol processor through voltage transitions.
Protocol processor is given transmitter 3.3V signal; Said voltage transitions driver adopts integrated circuit SN74LVC2T45; The voltage transitions driver is the signal of 10Mbps, 5V with the conversion of signals of 10Mbps, 3.3V; The level of first power MOS pipe and the second power MOS pipe grid is raised, and drain terminal has enough big electric current when guaranteeing the data high-speed transmission, and the VCC of integrated circuit SN74LVC2T45 can be as the Enable Pin of transmitter simultaneously.
Said first power MOS pipe and second power MOS pipe are LDMOS or NMOS.
Said LDMOS or NMOS adopt switching speed to be not less than 1800MHz high-speed power transistor, satisfy cut-in voltage 1.9V, and when gate source voltage reached 5.65V, drain current can reach 3.1A.
Said receiver produces the Transistor-Transistor Logic level signal that matees with protocol processor from the Manchester code of 1553 buses reception 10MHz through filtering, comparison, level conversion.
The said first single order active filter and the second single order active filter require bandwidth to be not less than 140MHz, and switching rate is not less than 480V/ μ s.
The frequency of said comparator input terminal is not less than 90MHz, and has the time-delay of 4ns under the 5V operating voltage.
Said voltage reference provides stable 1.8V output voltage benchmark.
Advantage of the present invention is:
1) do not change original bus structures, need not change cable and interface mode, saved great amount of cost and time;
2) adopt discrete device to build, saved expensive flow expense, implement flexible;
3) owing to adopt discrete device, can have good versatility and powerful extensibility through changing the requirement that different parameters such as capacitance resistance satisfy different transmission rates.
Description of drawings
Fig. 1 is the protocol processor circuit block diagram relevant with the present invention.
Fig. 2 is that model of the present invention is a SN74LVC2T45 voltage transitions drive circuit pinouts.
Fig. 3 is that model of the present invention is a BLF6G21-10G LDMOS pinouts.
Fig. 4 is an isolating transformer pinouts of the present invention.
Fig. 5 is that model of the present invention is a THS4521 high speed operation amplifier circuit pinouts.
Fig. 6 is that model of the present invention is an AD8611 comparator circuit pinouts.
Fig. 7 is that model of the present invention is a LM4120-1.8 voltage reference circuit pinouts.
Fig. 8 is the present invention's 1553 bus discrete device transmitter architecture block diagrams at a high speed.
Fig. 9 is the present invention's 1553 bus discrete device receiver architecture block diagrams at a high speed.
Figure 10 is a single order active filter circuit schematic diagram of the present invention.
Figure 11 is a voltage reference circuit schematic diagram of the present invention.
Figure 12 is a comparator circuit schematic diagram of the present invention.
Embodiment
Below in conjunction with accompanying drawing and embodiment the present invention is described further.
The mode that the present invention adopts discrete device to build is divided into two parts of transmitter and receiver.
Transmitter is connected with protocol processor, accomplishes the transmission of high speed Manchester code, and it is made up of the resistance of voltage transitions driver, LDMOS (or NMOS) and the certain resistance and the appearance value of the ternary output of two-way tape.The circuit pinouts of the structured flowchart of high speed protocol processor circuit, SN74LVC2T45, LDMOS-BLF6G21-10G is seen Fig. 1, Fig. 2 and Fig. 3 respectively.
As shown in Figure 1, said high speed protocol processor circuit comprises: dual-channels communication protocol process module, external interface logic module, configuration register module, memory management module, bit wide are selected module, monitoring bus module, bus control module, remote terminal control module and clock/reseting module; Said dual-channels communication protocol process module, configuration register module, memory management module, bit wide select module, monitoring bus module, bus control module, remote terminal control module to be connected mutually through 1533 buses with clock/reseting module, and said dual-channels communication protocol process module connects external equipment through the external interface logic module.The external interface logic module includes and sends positive signal end Txa, sends negative signal end Txa_n, receives positive signal end Rxa, receives negative signal end Rxa_n.
The Manchester code that said transmitter is accomplished 10Mbps speed sends; Comprise: the input of the voltage transitions drive circuit of the ternary output of band links to each other with protocol processor; The first output B1 of the voltage transitions drive circuit of the ternary output of said band is connected with the grid of the first power MOS pipe M1 through resistance; First power MOS pipe M1 drain electrode links to each other with the first power MOS pipe M1 grid through electric capacity, and is connected with 1 pin of isolating transformer through resistance; The output B2 of the voltage transitions drive circuit of the ternary output of said band is connected with the grid of the second power MOS pipe M2 through resistance; Second power MOS pipe M2 drain electrode links to each other with the second power MOS pipe M2 grid through electric capacity, and connects 3 pin of isolating transformer through resistance.Said receiver comprises: the positive Manchester code analog signal of bus RXIN+ connects the negative input end of the first single order active filter and the positive input terminal of the second single order active filter, and the negative Manchester code analog signal RXIN-of bus connects the positive input terminal of the first single order active filter and the negative input end of the second single order active filter; The output of the first single order active filter connects the negative input end of first comparator; The first comparator positive input termination voltage reference; The negative Manchester code digital signal RXOUT-of first comparator negative output terminal output, and the process voltage transitions is delivered to the reception negative signal end Rxa_n of protocol processor; The output of the second single order active filter connects the negative input end of second comparator; The second comparator positive input termination voltage reference; The negative output terminal of second comparator is exported positive Manchester code digital signal RXOUT+, and delivers to the reception positive signal end Rxa of protocol processor through voltage transitions.
Integrated circuit SN74LVC2T45 is the voltage transitions driver of the ternary output of two-way tape.Since protocol processor give flourishing device for the 3.3V level signal, the drain terminal of LDMOS has enough big electric current when guaranteeing the data high-speed transmission, need the level of grid be raised.The voltage transitions driver can be the high-speed level signal of 5V with the high-speed level conversion of signals of 3.3V; The A1 of circuit SN74LVC2T45 and A2 pin meet transmission positive signal end Txa, the transmission negative signal end Txa_n of protocol processor respectively, and VCC is as the Enable Pin of transmitter.
LDMOS adopts the high-speed power transistor BLF6G21-10G of NXP company,, switching speed is not less than 1800MHz; Cut-in voltage 1.9V, when gate source voltage reached 5.65V, drain current can reach 3.1A; Input and output electric capacity meets design requirement between several pF ~ tens pF.
Its pin of isolating transformer is as shown in Figure 4.Effective output of this isolating transformer is the transformer coupled output of 1:1.79, and the centre tap of transformer input (the 2nd pin) connects+the 5V power supply.The two ends of isolating transformer input coil are respectively 1 pin and 3 pin, and the centre tap of input coil is 2 pin, and the two ends of isolating transformer output winding are respectively 4 pin and 8 pin, and three centre taps are followed successively by 5 pin, 6 pin, 7 pin.Wherein 3 pin and 8 pin are end of the same name, connect load between 5 pin and 7 pin.
The receiver part receives the high speed Manchester code from 1553 buses, produces the Transistor-Transistor Logic level signal that matees with protocol processor through filtering, comparison, level conversion.
The single order active filter that filter adopts high speed operation amplifier to build.Require bandwidth to be not less than 140MHz, switching rate is not less than 480V/ μ s, and its circuit theory diagrams are shown in figure 10.
The comparator that adopts requires this device to be not less than under the condition of 90MHz in the frequency of input, has under the 5V operating voltage time-delay less than 4ns.Voltage reference in the comparator requires stable 1.8V output voltage benchmark can be provided, and its circuit theory diagrams are shown in figure 12.
The single order active filter that filter adopts the operational amplifier THS4521 of TI company to build.The THS4521 bandwidth can reach 145MHz, and switching rate can reach 490V/ μ s.Its pin is as shown in Figure 5.
Comparator adopts the comparator AD8611 of ADI company, and the frequency of this device input can reach 100MHz, and has the time-delay of 4ns under the 5V operating voltage, and is as shown in Figure 6.
Voltage reference in the comparator adopts the LM4120 of National Semicondutor company, and it can provide stable 1.8V output voltage benchmark, and as shown in Figure 7, its circuit theory diagrams are shown in figure 11.
High speed 1553 bus discrete device transceiver circuits of the present invention divide transmission and receive two part work.Like the discrete device transmitter shown in Fig. 8 frame of broken lines; Protocol processor produces A1, the A2 port that a pair of differential signal Txa, Txa_n deliver to SN74LVC2T45; The power end VCCA of SN74LVC2T45 selects 3.3V power supply or GND through wire jumper; With opening and shutting off of control transmitter, power end VCCB connects the 5.0V power supply, and this is because protocol processor adopts the port voltage of 3.3V standard; In order to guarantee that LDMOS has enough big electric current to drive next stage, the signal that protocol processor is exported is converted to 5V voltage through the level conversion device.Direction control end DIR connects high level, makes data-signal deliver to the B end by the A end.Earth terminal GND links to each other with the ground end of circuit board.Pass through 10 Ω resistance to reduce signal reflex through the signal after the level conversion.Then two paths of differential signals is delivered to the grid Pin2 of two LDMOS pipes respectively; Source electrode Pin3 connects together with substrate and receives ground; Drain electrode Pin1 is as the primary side Pin1, the Pin3 that export and be connected in series 2 Ω resistance to transformers, and the feedback capacity of the grid of LDMOS and drain electrode cross-over connection 100pF is used to adjust the staircase of signal.To secondary, load is connected between the pin 5 and pin 7 of isolating transformer signal through isolating transformer.The operation principle of transmitter is following.
When the corresponding graceful sign indicating number of Txa is high level; The graceful sign indicating number that Txa_n is corresponding should be low level, at this moment, and the first power MOS pipe conducting among Fig. 8; So No. 1 tap of transformer is pulled to ground; Electric current is stream from middle tap Pin2 toward No. 1 tap, and coupling produces electric current in the opposite direction between No. 3 taps of transformer input and centre tap, has just formed the graceful sign indicating number of positive negative level between such 1, No. 3 tap; In like manner, when Txa_n was high level corresponding to graceful sign indicating number, the graceful sign indicating number that Txa is corresponding should be low level, at this moment, the second power MOS pipe conducting, so No. 3 taps of transformer are pulled to ground, electric current flows toward No. 3 taps from middle tap.Coupling produces opposite electric current between No. 1 tap of transformer input and centre tap, has formed the graceful sign indicating number of positive negative level between such 1, No. 3 tap equally.
The output of transmitter directly links to each other with the input of receiver; Be that TXOUT+ among Fig. 8 is connected with RXIN+ among Fig. 9; TXOUT-among Fig. 8 is connected with RXIN-among Fig. 9; Through the single order active filter (see figure 10) among Fig. 9, comparator (seeing Figure 12), model is the voltage transitions driver of SN74LVC2T45, delivers to the Rxa of protocol processor respectively, the Rxa_n end.
The single order active filter is made up of the high speed amplifier, and the differential signal of transmitter output is connected to its differential input end Pin1, Pin8 through 1/2 dividing potential drop after, makes the amplifier can normal response with the reduction common mode voltage signal.Power supply Vs+ (Pin3) connects+5V, Vs-(Pin6) ground connection, and common-mode voltage input VOCM (Pin2) connects 0.1uF electric capacity to ground, to reduce the coupled noise on the pin.
For the single order active filter, its cut-off frequency is:
Through choose suitable R, the C value can make the signal in the certain frequency scope pass through.For fear of the influence of HF noise signal to normal graceful sign indicating number; Here we choose:
, substitution 1 formula has:
I.e.
; The quintuple harmonics component that can satisfy square wave passes through, and higher harmonic component (being noise mostly) is filtered.
In order to make comparator that higher sensitivity is arranged, need the output signal process of filter be amplified, selecting multiplication factor here is 6.Therefore, at positive output VOUT+ of operational amplifier (Pin4) and negative input end VIN-(Pin1) cross-over connection feedback resistance R
F
The multiplication factor of operational amplifier is determined by following formula:
The output of active filter (Pin4) is connected to the negative input end IN-(Pin3) of comparator; The thresholding of comparator is decided to be 1.8V; Therefore the input VIN (Pin4) of Voltage Reference LM4120 is connected to+the 5V power supply with Enable Pin Enable (Pin3); REF end (Pin1) is unsettled, and GND (Pin2) is connected to commonly and holds, and the positive input terminal IN+ (Pin2) of comparator is received in its output (VOUT).When the level of filter output waveform is higher than 1.8V, output level be high (+5V), when output level was lower than 1.8V, output level was low (0V).Like this, just by filter shape, prevent that noise signal from making protocol processor produce misoperation through the Manchester code after the bus transfer.
At last, the 5V signal of output will pass through level shifting circuit, is converted into the 3.3V level signal that protocol processor can receive.Input A1, A2 meet RXOUT-, RXOUT+ respectively, with voltage transitions driver in the transmitter connect method different be, receiver need not enable control, so VCCA connects fixing 3.3V level, DIR ground connection is held so that data-signal is delivered to A by the B end.The signal B1 of output, Rxa_n, the Rx that B2 is delivered to protocol processor respectively.
Claims (8)
1. be applicable to the discrete transceiver circuit of 1553 buses at a high speed; Comprise transmitter and receiver; It is characterized in that: the Manchester code that said transmitter is accomplished 10Mbps speed sends; Comprise: the input of the voltage transitions drive circuit of the ternary output of band links to each other with protocol processor; First output (B1) of the voltage transitions drive circuit of the ternary output of said band is connected with the grid of first power MOS pipe (M1) through resistance, and first power MOS pipe (M1) drain electrode links to each other with first power MOS pipe (M1) grid through electric capacity, and is connected with 1 pin of isolating transformer through resistance; The output (B2) of the voltage transitions drive circuit of the ternary output of said band is connected with the grid of second power MOS pipe (M2) through resistance; Second power MOS pipe (M2) drain electrode links to each other with second power MOS pipe (M2) grid through electric capacity, and connects 3 pin of isolating transformer through resistance; The two ends of isolating transformer input coil are respectively 1 pin and 3 pin; The centre tap of input coil is 2 pin; The two ends of isolating transformer output winding are respectively 4 pin and 8 pin, and three centre taps are followed successively by 5 pin, 6 pin, 7 pin, and wherein 3 pin and 8 pin are end of the same name; 2 pin of isolating transformer connect+the 5V power supply, connect load between 5 pin and 7 pin; Said receiver comprises: the positive Manchester code analog signal of bus (RXIN+) connects the negative input end of the first single order active filter and the positive input terminal of the second single order active filter, and the negative Manchester code analog signal (RXIN-) of bus connects the positive input terminal of the first single order active filter and the negative input end of the second single order active filter; The output of the first single order active filter connects the negative input end of first comparator; The first comparator positive input termination voltage reference; The negative Manchester code digital signal (RXOUT-) of first comparator negative output terminal output, and the process voltage transitions is delivered to the reception negative signal end (Rxa_n) of protocol processor; The output of the second single order active filter connects the negative input end of second comparator; The second comparator positive input termination voltage reference; The negative output terminal of second comparator is exported positive Manchester code digital signal (RXOUT+), and delivers to the reception positive signal end (Rxa) of protocol processor through voltage transitions.
2. be applicable to the discrete transceiver circuit of 1553 buses at a high speed according to claim 1; It is characterized in that; Protocol processor is given transmitter 3.3V signal; Said voltage transitions driver adopts integrated circuit SN74LVC2T45, and the voltage transitions driver is the signal of 10Mbps, 5V with the conversion of signals of 10Mbps, 3.3V, and the level of first power MOS pipe (M1) and second power MOS pipe (M2) grid is raised; Drain terminal has enough big electric current when guaranteeing the data high-speed transmission, and the VCC of integrated circuit SN74LVC2T45 can be as the Enable Pin of transmitter simultaneously.
3. be applicable to the discrete transceiver circuit of 1553 buses at a high speed according to claim 1, it is characterized in that said first power MOS pipe (M1) and second power MOS pipe (M2) are LDMOS or NMOS.
4. like the said discrete transceiver circuit of 1553 buses at a high speed that is applicable to of claim 3; It is characterized in that said LDMOS or NMOS adopt switching speed to be not less than 1800MHz high-speed power transistor, satisfy cut-in voltage 1.9V; And when gate source voltage reached 5.65V, drain current can reach 3.1A.
5. be applicable to the discrete transceiver circuit of 1553 buses at a high speed according to claim 1; It is characterized in that; Said receiver produces the Transistor-Transistor Logic level signal that matees with protocol processor from the Manchester code of 1553 buses reception 10MHz through filtering, comparison, level conversion.
6. be applicable to the discrete transceiver circuit of 1553 buses at a high speed according to claim 1, it is characterized in that the said first single order active filter and the second single order active filter require bandwidth to be not less than 140MHz, switching rate is not less than 480V/ μ s.
7. be applicable to the discrete transceiver circuit of 1553 buses at a high speed according to claim 1, it is characterized in that the frequency of said comparator input terminal is not less than 90MHz, and have the time-delay of 4ns under the 5V operating voltage.
8. be applicable to the discrete transceiver circuit of 1553 buses at a high speed according to claim 1, it is characterized in that said voltage reference provides stable 1.8V output voltage benchmark.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210104495.3A CN102664782B (en) | 2012-04-09 | 2012-04-09 | Discrete transceiver circuit suitable for high-speed 1553 bus |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210104495.3A CN102664782B (en) | 2012-04-09 | 2012-04-09 | Discrete transceiver circuit suitable for high-speed 1553 bus |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102664782A true CN102664782A (en) | 2012-09-12 |
| CN102664782B CN102664782B (en) | 2015-01-14 |
Family
ID=46774201
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210104495.3A Active CN102664782B (en) | 2012-04-09 | 2012-04-09 | Discrete transceiver circuit suitable for high-speed 1553 bus |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102664782B (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103235769A (en) * | 2013-03-27 | 2013-08-07 | 中国航天科技集团公司第九研究院第七七一研究所 | High speed 1553 bus protocol processor |
| CN103391081A (en) * | 2013-07-19 | 2013-11-13 | 中国航天科技集团公司第九研究院第七七一研究所 | Digital controllable inductive load drive circuit |
| CN104485937A (en) * | 2014-11-24 | 2015-04-01 | 成都盛军电子设备有限公司 | Output level conversion circuit of delay signal generator |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5444546A (en) * | 1989-11-10 | 1995-08-22 | Canon Kabushiki Kaisha | Image signal processing apparatus having multiplexing capability |
| CN101800600A (en) * | 2009-12-30 | 2010-08-11 | 航天时代电子技术股份有限公司 | Photoelectric conversion circuit and realizing method thereof based on 1553B bus |
-
2012
- 2012-04-09 CN CN201210104495.3A patent/CN102664782B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5444546A (en) * | 1989-11-10 | 1995-08-22 | Canon Kabushiki Kaisha | Image signal processing apparatus having multiplexing capability |
| CN101800600A (en) * | 2009-12-30 | 2010-08-11 | 航天时代电子技术股份有限公司 | Photoelectric conversion circuit and realizing method thereof based on 1553B bus |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103235769A (en) * | 2013-03-27 | 2013-08-07 | 中国航天科技集团公司第九研究院第七七一研究所 | High speed 1553 bus protocol processor |
| CN103235769B (en) * | 2013-03-27 | 2016-01-13 | 中国航天科技集团公司第九研究院第七七一研究所 | A kind of 1553 bus protocol processors at a high speed |
| CN103391081A (en) * | 2013-07-19 | 2013-11-13 | 中国航天科技集团公司第九研究院第七七一研究所 | Digital controllable inductive load drive circuit |
| CN104485937A (en) * | 2014-11-24 | 2015-04-01 | 成都盛军电子设备有限公司 | Output level conversion circuit of delay signal generator |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102664782B (en) | 2015-01-14 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| DE102011076153B4 (en) | Communication signal generating device and communication device for use in a communication system | |
| US20110280322A1 (en) | Data transmission system capable of transmitting interrupt signal without interrupt gate period | |
| CN101741373B (en) | Low voltage differential signal driver adaptive to various IO power supplies | |
| CN102664782B (en) | Discrete transceiver circuit suitable for high-speed 1553 bus | |
| CN102169472B (en) | RS485 bus interface circuit | |
| CN203324975U (en) | Serial communication debugging tool | |
| CN202587010U (en) | Discrete transceiver circuit suitable for high speed 1553 bus | |
| CN107147431A (en) | A kind of low-voltage direct carrier communication circuit and its implementation based on differential coupling | |
| CN202014233U (en) | Digital signal communication circuit and air conditioner equipped therewith | |
| CN108233991B (en) | RS 485-based direct current carrier communication system | |
| WO2022040999A1 (en) | Isolation circuit and apparatus for controller area network communication | |
| CN212064011U (en) | Electrical port module | |
| CN102065039A (en) | High-speed interface circuit adaptive equalization method and circuit therefor | |
| CN103257944A (en) | Method and device for long-distance transmission of USB signals | |
| CN205792519U (en) | A kind of digital signal isolator | |
| CN101576868B (en) | I2C bus communication drive circuit | |
| CN103645689A (en) | Differential signal based single bus transmission device | |
| CN202798661U (en) | Industrial control bus structure | |
| CN213069543U (en) | Circuit and device for controller area network communication | |
| CN111147341A (en) | Communication conversion circuit and communication system for RGV | |
| CN210954703U (en) | Analog quantity signal acquisition functional module and acquisition system based on edge calculation technology | |
| CN203616628U (en) | Differential signal-based unibus transmission device | |
| CN209072340U (en) | Voltage processing unit | |
| CN219875776U (en) | SPI remote control transmission device | |
| CN219697667U (en) | FlexRay bus communication module based on FPGA |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |