CN203133832U - Anti-jamming communication interface circuit - Google Patents
Anti-jamming communication interface circuit Download PDFInfo
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- CN203133832U CN203133832U CN 201320069949 CN201320069949U CN203133832U CN 203133832 U CN203133832 U CN 203133832U CN 201320069949 CN201320069949 CN 201320069949 CN 201320069949 U CN201320069949 U CN 201320069949U CN 203133832 U CN203133832 U CN 203133832U
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Abstract
The utility model belongs to the field of electronic circuits and relates to an anti-jamming RS485 and RS422 communication interface circuit. According to the technical scheme, the anti-jamming communication interface circuit comprises a host communication interface circuit, a slave communication interface circuit and a DC-DC power conversion circuit. The DC-DC power conversion circuit converts input VCC1 into VCCDCout2 and is provided with a return circuit earth wire GND1 of the VCC1 and a return circuit earth wire GNDDC2 of the VCCDCout2. The host communication interface circuit is the same as the slave communication interface circuit in constitution. High-speed optical couplers are connected into the different earth wires in the DC-DC power conversion circuit to isolate the earth wires, and therefore the communication interface circuit can have strong anti-jamming capability and is suitable for working in an electromagnetic environment and complex severe environments.
Description
Technical field
The utility model belongs to electronic circuit field, relates to a kind of jamproof RS485, RS422 communication interface circuit.
Background technology
RS485 and RS422 industrial communication data bus are very extensive in current application, and this data communication bus adopts the mode of differential transfer to carry out, the distance of transmission, and the disturbance rejection ability is stronger, and possesses the function of a plurality of telecommunication circuit cascades.
But in the environment of some electromagnetic environment very severes, data communication inevitably can be disturbed, and causes the data communication instability, even causes the out of control of equipment.
Summary of the invention
The purpose of this utility model is: a kind of jamproof communication interface circuit that can guarantee reliably working in abominable electromagnetic environment is provided;
The technical solution of the utility model is: a kind of jamproof communication interface circuit, and it comprises: host communication interface circuit, slave communication interface circuit and DC_DC power-switching circuit;
The DC_DC power-switching circuit converts the VCC1 of input to VCCDCout2, and be provided with the loop ground wire GND1 of VCC1 and the loop ground wire GNDDC2 of VCCDCout2, between the VCC1 that imports and loop ground wire GND1, insert capacitor C 9, between the VCCDCout2 that exports and loop ground wire GNDDC2, insert capacitor C 10 and electrochemical capacitor C11;
The host communication interface circuit comprises: high speed photo coupling B1, high speed photo coupling B2, MAX489 chip D1 and a filtering circuit; The input negative terminal of high speed photo coupling B2 inserts the signal sending end of external circuits, the input anode meets VCC1 by resistance R 10, output plus terminal meets VCCDCout2 on the one hand, insert 5 pin of MAX489 chip D1 on the other hand by resistance R 3, the collector of the triode of the output negative terminal of high speed photo coupling B2 inserts between 5 pin of resistance R 3 and MAX489 chip D1, and emitter meets GNDDC2; The output plus terminal of high speed photo coupling B1 meets VCC1 on the one hand, insert the signal receiving end of external circuitry on the other hand by resistance R 1, the emitter of the triode of output negative terminal meets GND1, collector inserts the signal receiving end of external circuitry, the output plus terminal of high speed photo coupling B1 inserts VCCDCout2 by resistance R 9, and the output negative terminal inserts 2 pin of MAX489 chip D1; 3 pin of MAX489 chip D1 meet GNDDC2, and 4 pin meet VCCDCout2,6 pin with meet GNDDC2 after 7 pin are in parallel, 13 pin with meet VCCDCout2 after 14 pin are in parallel; Filtering circuit is by capacitor C 1, capacitor C 2, capacitor C 3, capacitor C 4, resistance R 13 and resistance R 15, wherein, capacitor C 1 is connected with 12 pin of MAX489 chip D1, capacitor C 2 is connected with 11 pin of MAX489 chip D1, capacitor C 3 is connected with 9 pin of MAX489 chip D1, capacitor C 4 is connected with 10 pin of MAX489 chip D1, the other end of capacitor C 1, capacitor C 2, capacitor C 3 and capacitor C 4 all inserts GNDDC2,12 pin and 11 pin of MAX489 chip D1 are inserted at the two ends of resistance R 13, and 9 pin and 10 pin of MAX489 chip D1 are inserted at the two ends of resistance R 15;
Slave communication interface circuit comprises: high speed photo coupling B3, high speed photo coupling B4, MAX489 chip D2 and a filtering circuit; The input negative terminal of high speed photo coupling B4 inserts the signal sending end of external circuits, the input anode meets VCC2 by resistance R 12, output plus terminal meets VCCDCout2 on the one hand, insert 5 pin of MAX489 chip D2 on the other hand by resistance R 4, the collector of the triode of the output negative terminal of high speed photo coupling B4 inserts between 5 pin of resistance R 4 and MAX489 chip D2, and emitter meets GNDDC2; The output plus terminal of high speed photo coupling B3 meets VCC2 on the one hand, insert the signal receiving end of external circuitry on the other hand by resistance R 2, the emitter of the triode of output negative terminal meets GND2, collector inserts the signal receiving end of external circuitry, the output plus terminal of high speed photo coupling B3 inserts VCCDCout2 by resistance R 11, and the output negative terminal inserts 2 pin of MAX489 chip D2; 3 pin of MAX489 chip D2 meet GNDDC2, and 4 pin meet VCCDCout2,6 pin with meet GNDDC2 after 7 pin are in parallel, 13 pin with meet VCCDCout2 after 14 pin are in parallel; Filtering circuit is by capacitor C 5, capacitor C 6, capacitor C 7, capacitor C 8, resistance R 14 and resistance R 16, wherein, capacitor C 5 is connected with 12 pin of MAX489 chip D2, capacitor C 6 is connected with 11 pin of MAX489 chip D2, capacitor C 7 is connected with 9 pin of MAX489 chip D2, capacitor C 8 is connected with 10 pin of MAX489 chip D2, the other end of capacitor C 5, capacitor C 6, capacitor C 7 and capacitor C 8 all inserts GNDDC2,12 pin and 11 pin of MAX489 chip D2 are inserted at the two ends of resistance R 14, and 9 pin and 10 pin of MAX489 chip D2 are inserted at the two ends of resistance R 16;
12 pin of MAX489 chip D1 insert 9 pin of MAX489 chip D2 in the slave communication interface circuit in the host communication interface circuit, 11 pin of MAX489 chip D1 insert 10 pin of MAX489 chip D2,9 pin of MAX489 chip D1 insert 12 pin of MAX489 chip D2, and 10 pin of MAX489 chip D1 insert 11 pin of MAX489 chip D2.
In this patent communication chip as one independently Circuits System handle, supply with independently power supply, the DC-DCDC_DC power-switching circuit is transformed into required direct supply output to the direct supply of input, use for telecommunication circuit, utilizing the DC_DC power-switching circuit mainly is that this type of power supply can isolated ground, ground wire between both sides' circuit is not produced crosstalk;
Utilize the port between high speed photo coupling B1, B2, B3, B4 isolated communication circuit and the external circuitry, guarantee in both sides' port connects, not exist the problem on common ground, wherein high speed photo coupling B1 and high speed photo coupling B2 isolate as receiving end and the transmitting terminal of MAX489 chip D1 respectively, and high speed photo coupling B3 and high speed photo coupling B4 isolate as receiving end and the transmitting terminal of MAX489 chip D2 respectively.
Beneficial effect: the utility model with communication chip as one independently Circuits System handle, supply with independently power supply, and utilize high speed photo coupling that ground wire is isolated, possess extremely strong antijamming capability, be applicable under electromagnetic environment and the complicated rugged surroundings thereof and work.
Description of drawings
Fig. 1 is the utility model host and slave processors communication interface circuit connection diagram;
Fig. 2 is the utility model DC_DC power-switching circuit connection diagram.
Embodiment
Referring to accompanying drawing 1,2, a kind of jamproof communication interface circuit, it comprises: host communication interface circuit, slave communication interface circuit and DC_DC power-switching circuit;
The DC_DC power-switching circuit converts the VCC1 of input to VCCDCout2, and be provided with the loop ground wire GND1 of VCC1 and the loop ground wire GNDDC2 of VCCDCout2, between the VCC1 that imports and loop ground wire GND1, insert capacitor C 9, between the VCCDCout2 that exports and loop ground wire GNDDC2, insert capacitor C 10 and electrochemical capacitor C11;
The host communication interface circuit comprises: high speed photo coupling B1, high speed photo coupling B2, MAX489 chip D1 and a filtering circuit; The input negative terminal of high speed photo coupling B2 inserts the signal sending end of external circuits, the input anode meets VCC1 by resistance R 10, output plus terminal meets VCCDCout2 on the one hand, insert 5 pin of MAX489 chip D1 on the other hand by resistance R 3, the collector of the triode of the output negative terminal of high speed photo coupling B2 inserts between 5 pin of resistance R 3 and MAX489 chip D1, and emitter meets GNDDC2; The output plus terminal of high speed photo coupling B1 meets VCC1 on the one hand, insert the signal receiving end of external circuitry on the other hand by resistance R 1, the emitter of the triode of output negative terminal meets GND1, collector inserts the signal receiving end of external circuitry, the output plus terminal of high speed photo coupling B1 inserts VCCDCout2 by resistance R 9, and the output negative terminal inserts 2 pin of MAX489 chip D1; 3 pin of MAX489 chip D1 meet GNDDC2, and 4 pin meet VCCDCout2,6 pin with meet GNDDC2 after 7 pin are in parallel, 13 pin with meet VCCDCout2 after 14 pin are in parallel; Filtering circuit is by capacitor C 1, capacitor C 2, capacitor C 3, capacitor C 4, resistance R 13 and resistance R 15, wherein, capacitor C 1 is connected with 12 pin of MAX489 chip D1, capacitor C 2 is connected with 11 pin of MAX489 chip D1, capacitor C 3 is connected with 9 pin of MAX489 chip D1, capacitor C 4 is connected with 10 pin of MAX489 chip D1, the other end of capacitor C 1, capacitor C 2, capacitor C 3 and capacitor C 4 all inserts GNDDC2,12 pin and 11 pin of MAX489 chip D1 are inserted at the two ends of resistance R 13, and 9 pin and 10 pin of MAX489 chip D1 are inserted at the two ends of resistance R 15;
Slave communication interface circuit quantity is one or more, and it comprises: high speed photo coupling B3, high speed photo coupling B4, MAX489 chip D2 and a filtering circuit; The input negative terminal of high speed photo coupling B4 inserts the signal sending end of external circuits, the input anode meets VCC2 by resistance R 12, output plus terminal meets VCCDCout2 on the one hand, insert 5 pin of MAX489 chip D2 on the other hand by resistance R 4, the collector of the triode of the output negative terminal of high speed photo coupling B4 inserts between 5 pin of resistance R 4 and MAX489 chip D2, and emitter meets GNDDC2; The output plus terminal of high speed photo coupling B3 meets VCC2 on the one hand, insert the signal receiving end of external circuitry on the other hand by resistance R 2, the emitter of the triode of output negative terminal meets GND2, collector inserts the signal receiving end of external circuitry, the output plus terminal of high speed photo coupling B3 inserts VCCDCout2 by resistance R 11, and the output negative terminal inserts 2 pin of MAX489 chip D2; 3 pin of MAX489 chip D2 meet GNDDC2, and 4 pin meet VCCDCout2,6 pin with meet GNDDC2 after 7 pin are in parallel, 13 pin with meet VCCDCout2 after 14 pin are in parallel; Filtering circuit is by capacitor C 5, capacitor C 6, capacitor C 7, capacitor C 8, resistance R 14 and resistance R 16, wherein, capacitor C 5 is connected with 12 pin of MAX489 chip D2, capacitor C 6 is connected with 11 pin of MAX489 chip D2, capacitor C 7 is connected with 9 pin of MAX489 chip D2, capacitor C 8 is connected with 10 pin of MAX489 chip D2, the other end of capacitor C 5, capacitor C 6, capacitor C 7 and capacitor C 8 all inserts GNDDC2,12 pin and 11 pin of MAX489 chip D2 are inserted at the two ends of resistance R 14, and 9 pin and 10 pin of MAX489 chip D2 are inserted at the two ends of resistance R 16;
12 pin of MAX489 chip D1 insert 9 pin of MAX489 chip D2 in the slave communication interface circuit in the host communication interface circuit, 11 pin of MAX489 chip D1 insert 10 pin of MAX489 chip D2,9 pin of MAX489 chip D1 insert 12 pin of MAX489 chip D2, and 10 pin of MAX489 chip D1 insert 11 pin of MAX489 chip D2.
The model of selected high speed photo coupling B1-B4 is 6N137 in the such scheme.
Claims (3)
1. a jamproof communication interface circuit is characterized in that it comprises: host communication interface circuit, slave communication interface circuit and DC_DC power-switching circuit;
Described DC_DC power-switching circuit converts the VCC1 of input to VCCDCout2, and be provided with the loop ground wire GND1 of VCC1 and the loop ground wire GNDDC2 of VCCDCout2, between the VCC1 that imports and loop ground wire GND1, insert capacitor C 9, between the VCCDCout2 that exports and loop ground wire GNDDC2, insert capacitor C 10 and electrochemical capacitor C11;
Described host communication interface circuit comprises: high speed photo coupling B1, high speed photo coupling B2, MAX489 chip D1 and a filtering circuit; The input negative terminal of high speed photo coupling B2 inserts the signal sending end of external circuits, the input anode meets VCC1 by resistance R 10, output plus terminal meets VCCDCout2 on the one hand, insert 5 pin of MAX489 chip D1 on the other hand by resistance R 3, the collector of the triode of the output negative terminal of high speed photo coupling B2 inserts between 5 pin of resistance R 3 and MAX489 chip D1, and emitter meets GNDDC2; The output plus terminal of high speed photo coupling B1 meets VCC1 on the one hand, insert the signal receiving end of external circuitry on the other hand by resistance R 1, the emitter of the triode of output negative terminal meets GND1, collector inserts the signal receiving end of external circuitry, the output plus terminal of high speed photo coupling B1 inserts VCCDCout2 by resistance R 9, and the output negative terminal inserts 2 pin of MAX489 chip D1; 3 pin of MAX489 chip D1 meet GNDDC2, and 4 pin meet VCCDCout2,6 pin with meet GNDDC2 after 7 pin are in parallel, 13 pin with meet VCCDCout2 after 14 pin are in parallel; Filtering circuit is by capacitor C 1, capacitor C 2, capacitor C 3, capacitor C 4, resistance R 13 and resistance R 15, wherein, capacitor C 1 is connected with 12 pin of MAX489 chip D1, capacitor C 2 is connected with 11 pin of MAX489 chip D1, capacitor C 3 is connected with 9 pin of MAX489 chip D1, capacitor C 4 is connected with 10 pin of MAX489 chip D1, the other end of capacitor C 1, capacitor C 2, capacitor C 3 and capacitor C 4 all inserts GNDDC2,12 pin and 11 pin of MAX489 chip D1 are inserted at the two ends of resistance R 13, and 9 pin and 10 pin of MAX489 chip D1 are inserted at the two ends of resistance R 15;
Described slave communication interface circuit comprises: high speed photo coupling B3, high speed photo coupling B4, MAX489 chip D2 and a filtering circuit; The input negative terminal of high speed photo coupling B4 inserts the signal sending end of external circuits, the input anode meets VCC2 by resistance R 12, output plus terminal meets VCCDCout2 on the one hand, insert 5 pin of MAX489 chip D2 on the other hand by resistance R 4, the collector of the triode of the output negative terminal of high speed photo coupling B4 inserts between 5 pin of resistance R 4 and MAX489 chip D2, and emitter meets GNDDC2; The output plus terminal of high speed photo coupling B3 meets VCC2 on the one hand, insert the signal receiving end of external circuitry on the other hand by resistance R 2, the emitter of the triode of output negative terminal meets GND2, collector inserts the signal receiving end of external circuitry, the output plus terminal of high speed photo coupling B3 inserts VCCDCout2 by resistance R 11, and the output negative terminal inserts 2 pin of MAX489 chip D2; 3 pin of MAX489 chip D2 meet GNDDC2, and 4 pin meet VCCDCout2,6 pin with meet GNDDC2 after 7 pin are in parallel, 13 pin with meet VCCDCout2 after 14 pin are in parallel; Filtering circuit is by capacitor C 5, capacitor C 6, capacitor C 7, capacitor C 8, resistance R 14 and resistance R 16, wherein, capacitor C 5 is connected with 12 pin of MAX489 chip D2, capacitor C 6 is connected with 11 pin of MAX489 chip D2, capacitor C 7 is connected with 9 pin of MAX489 chip D2, capacitor C 8 is connected with 10 pin of MAX489 chip D2, the other end of capacitor C 5, capacitor C 6, capacitor C 7 and capacitor C 8 all inserts GNDDC2,12 pin and 11 pin of MAX489 chip D2 are inserted at the two ends of resistance R 14, and 9 pin and 10 pin of MAX489 chip D2 are inserted at the two ends of resistance R 16;
12 pin of MAX489 chip D1 insert 9 pin of MAX489 chip D2 in the described slave communication interface circuit in the described host communication interface circuit, 11 pin of MAX489 chip D1 insert 10 pin of MAX489 chip D2,9 pin of MAX489 chip D1 insert 12 pin of MAX489 chip D2, and 10 pin of MAX489 chip D1 insert 11 pin of MAX489 chip D2.
2. a kind of jamproof communication interface circuit as claimed in claim 1 is characterized in that the model of described high speed photo coupling B1-B4 is 6N137.
3. a kind of jamproof communication interface circuit as claimed in claim 1 or 2 is characterized in that the quantity of described slave communication interface circuit is one or more.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201320069949 CN203133832U (en) | 2013-02-06 | 2013-02-06 | Anti-jamming communication interface circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201320069949 CN203133832U (en) | 2013-02-06 | 2013-02-06 | Anti-jamming communication interface circuit |
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| Publication Number | Publication Date |
|---|---|
| CN203133832U true CN203133832U (en) | 2013-08-14 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN 201320069949 Expired - Lifetime CN203133832U (en) | 2013-02-06 | 2013-02-06 | Anti-jamming communication interface circuit |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104124958A (en) * | 2014-07-02 | 2014-10-29 | 惠州市亿能电子有限公司 | Circuit for biasing communication ground to positive pole of system |
| CN105468559A (en) * | 2015-11-24 | 2016-04-06 | 上海航天科工电器研究院有限公司 | IO (Input/Output) interface board card for signal classification processing |
-
2013
- 2013-02-06 CN CN 201320069949 patent/CN203133832U/en not_active Expired - Lifetime
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104124958A (en) * | 2014-07-02 | 2014-10-29 | 惠州市亿能电子有限公司 | Circuit for biasing communication ground to positive pole of system |
| CN105468559A (en) * | 2015-11-24 | 2016-04-06 | 上海航天科工电器研究院有限公司 | IO (Input/Output) interface board card for signal classification processing |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
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| CX01 | Expiry of patent term |
Granted publication date: 20130814 |