CN213816147U

CN213816147U - Chip packaging structure, chip and electronic equipment

Info

Publication number: CN213816147U
Application number: CN202022944015.7U
Authority: CN
Inventors: 穆新; 仇元红
Original assignee: Spreadtrum Communications Shanghai Co Ltd
Current assignee: Spreadtrum Communications Shanghai Co Ltd
Priority date: 2020-12-10
Filing date: 2020-12-10
Publication date: 2021-07-27
Anticipated expiration: 2030-12-10

Abstract

The utility model provides a chip packaging structure, chip and electronic equipment, this chip packaging structure includes the base plate and sets up a plurality of first bumps and a plurality of second bump on the base plate, and a plurality of first bumps are the arranging of multirow multiseriate, and a plurality of second bumps also are the arranging of multirow multiseriate, are equipped with the second bump of a line between the every two adjacent lines of first bumps, are equipped with a second bump between every two adjacent first bumps. The whole of arranging for non-array through setting up first bump and second bump, under the same row interval and the interval of being listed as, can make the space increase between first bump and the second bump, satisfy the space basis of seting up the through-hole, can set up more rows and more multiseriate first bump and second bump on the base plate to can make the chip body be connected with more first bumps and second bumps, thereby promote chip electrical property.

Description

Chip packaging structure, chip and electronic equipment

Technical Field

The utility model belongs to the technical field of the chip, especially, relate to a chip packaging structure, chip and electronic equipment.

Background

Chip packaging mainly comprises a normal mounting and a flip chip, and the flip chip has excellent heat conducting property and electrical property and can have the advantages of a plurality of IO contacts and the like, so that the flip chip is greatly developed.

In the current chip packaging structure, the central region of the chip body is connected with the outside through a plurality of metal bumps, the arrangement of the metal bumps is array arrangement, the number of the metal bumps in the arrangement mode is less, and the improvement of the electrical property of the chip is not facilitated.

SUMMERY OF THE UTILITY MODEL

The utility model aims at providing a chip package structure, chip and electronic equipment can increase the quantity of metal bump, promotes the electrical property of chip.

For realizing the purpose of the utility model, the utility model provides a following technical scheme:

in a first aspect, the utility model provides a chip packaging structure, be in including base plate and setting a plurality of first bumps and a plurality of second bump on the base plate are a plurality of first bump is multirow multiseriate arranging, and is a plurality of the second bump also is multirow multiseriate arranging, every adjacent two lines be equipped with the one line between the first bump the second bump, every adjacent two be equipped with one between the first bump the second bump.

In one embodiment, the second bumps in each row are spaced apart from the first bumps in two adjacent rows by the same distance, and/or the second bumps in each column are spaced apart from the second bumps in two adjacent columns by the same distance.

In one implementation mode, a plurality of through holes with circular cross sections are formed in the substrate, each through hole is located around the first salient point and the second salient point, and the diameter of each through hole is smaller than the distance between two adjacent rows and two adjacent columns of the first salient points.

In one embodiment, the center of the through hole is located on a line connecting geometric center points of the first salient points or the second salient points in each row.

In one embodiment, the number of the through holes is less than the sum of the number of the first bumps and the number of the second bumps.

In one embodiment, the substrate includes a first surface and a second surface opposite to the first surface, the first bump and the second bump are both disposed on the first surface, and the through hole penetrates through the first surface and the second surface; the chip packaging structure further comprises a plurality of first connecting structures and a plurality of second connecting structures, the first connecting structures and the second connecting structures are filled in the corresponding through holes and extend from the first surface, each first connecting structure is connected with a plurality of first bumps on one row, and each second connecting structure is connected with a plurality of second bumps on one row.

In one embodiment, the first connecting structure includes a first hollow space, the second connecting structure includes a second hollow space, the first protruding point is located in the first hollow space, and the second protruding point is located in the second hollow space, wherein the periphery of the first hollow space is sealed, and/or the periphery of the second hollow space is sealed.

In one embodiment, the first bumps and the second bumps are oval, the major axis directions of the ovals of the first bumps and the second bumps are consistent with the row direction, and the peripheries of the first hollowed-out space and the second hollowed-out space are sealed.

In one embodiment, the chip package structure further includes a plurality of ball pads, the ball pads are disposed on the second surface, each of the ball pads is connected to the first connecting structure or the second connecting structure, and a side of the ball pad facing away from the substrate is used for being connected to a solder ball.

In a second aspect, the present application further provides a chip, which includes a chip body and the chip package structure described in any of the various embodiments of the first aspect, wherein the chip body is connected to the plurality of first bumps and the plurality of second bumps.

In a third aspect, the present application also provides an electronic device comprising the chip of the second aspect.

Through setting up whole of first bump and second bump and arranging for non-array, be equipped with the second bump of a line between every adjacent two lines of first bumps promptly, every adjacent two is equipped with a second bump between the first bump, arrange for traditional array, the same line interval with be listed as under the interval, can make the space increase between first bump and the second bump, satisfy the space basis of seting up the through-hole on, can set up more lines and more multiseriate first bump and second bump on the base plate, thereby can make the chip body be connected with more first bumps and second bumps, thereby promote the chip electrical property.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

FIG. 1 is a schematic structural diagram of a chip package structure according to an embodiment;

FIG. 2 is a schematic structural diagram of a chip package structure according to an embodiment;

FIG. 3 is a schematic cross-sectional view of a chip package structure according to an embodiment;

FIG. 4 is a schematic structural diagram of a chip package structure according to an embodiment;

fig. 5 is a schematic structural diagram of a chip package structure according to an embodiment.

Description of the reference numerals

10-substrate, 11-first surface, 12-second surface;

21-a first bump, 22-a second bump;

31-a first connecting structure, 311-a filling part, 312-an extending part, 315-a first hollow space, 32-a second connecting structure, 325-a second hollow space, 33-a ball pad, 35-a through hole and 38-a transition structure;

40-a chip body;

50-insulating protective layer.

Detailed Description

The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work all belong to the protection scope of the present invention.

Referring to fig. 1 and 2, wherein fig. 1 and 2 are only partial structural illustrations, an application embodiment provides a chip package structure, including a substrate 10 and a plurality of first bumps 21 and a plurality of second bumps 22 disposed on the substrate 10. The plurality of first salient points 21 are arranged in a plurality of rows and a plurality of columns, the plurality of second salient points 22 are also arranged in a plurality of rows and a plurality of columns, a row of second salient points 22 is arranged between every two adjacent rows of first salient points 21, and a column of second salient points 22 is arranged between every two adjacent columns of first salient points 21.

Specifically, the substrate 10 may be a thermoplastic resin material, which is used only as a carrying base and is not conductive, and the first bumps 21 and the second bumps 22 are both made of a metal material and have conductivity for transmitting electrical signals, that is, the plurality of first bumps 21 are used for transmitting power signals to the chip body 40, and the plurality of second bumps 22 are used for transmitting ground signals to the chip body 40. The number of the first bumps 21 and the number of the second bumps 22 may be equal, the number of the rows of the first bumps 21 and the number of the rows of the second bumps 22 may be equal, and the number of the columns of the first bumps 21 and the number of the columns of the second bumps 22 may also be equal.

The plurality of first bumps 21 and the plurality of second bumps 22 of the present embodiment may be arranged in an array, but the entirety of the first bumps 21 and the second bumps 22 is arranged in a non-array, that is, is not formed by an array based on one first bump 21 or one second bump 22. From another perspective, the plurality of first bumps 21 and the plurality of second bumps 22 are arranged in different rows and different columns, and the first bumps 21, the second bumps 22 and the first bumps 21 in one row are sequentially and alternately arranged in sequence; in terms of rows, a row of the first bumps 21, a row of the second bumps 22, and a row of the first bumps 21 are alternately arranged in sequence. The difference from the array arrangement of the first bumps 21 and the second bumps 22 as a whole is that, in terms of columns, the array arrangement is that one column of the first bumps 21 and an adjacent column of the second bumps 22 are located in the same column, while one column of the first bumps 21 and an adjacent column of the second bumps 22 are located in different columns in the present application.

Since the electrical signals of the first bumps 21 and the second bumps 22 need to be transmitted through the metal filled in the through holes 35 (described in detail later, not shown here), and the through holes 35 formed in the substrate 10 need to occupy a certain space, in this embodiment, the first bumps 21 and the second bumps 22 are arranged in a non-array manner as a whole, that is, one row of the second bumps 22 is arranged between every two adjacent rows of the first bumps 21, and one column of the second bumps 22 is arranged between every two adjacent columns of the first bumps 21, compared with the conventional array arrangement, the space between the first bumps 21 and the second bumps 22 can be increased under the same row interval and column interval, and on the basis of satisfying the space for forming the through holes 35, more rows and more columns of the first bumps 21 and the second bumps 22 can be formed on the substrate 10, so that the chip body 40 can be connected with more first bumps 21 and more second bumps 22, thereby improving the electrical performance of the chip.

Optionally, the second bumps 22 in each row are spaced apart from the first bumps 21 in two adjacent rows by the same distance. In other words, one of the rows of the second bumps 22 is located at the middle position of the row pitch of the two adjacent rows of the first bumps 21, so that the rows of the first bumps 21 and the second bumps 22 are arranged at equal intervals, and the first bumps 21 and the second bumps 22 are uniformly distributed on the rows, so that the through holes 35 can be uniformly formed on the substrate 10 in the rows.

Optionally, the second bumps 22 in each column are spaced apart from the second bumps 22 in two adjacent columns by the same distance. In other words, one of the rows of the second bumps 22 is located at the middle position of the row pitch of two adjacent rows of the first bumps 21, so that the rows of the first bumps 21 and the second bumps 22 are arranged at equal intervals, and the first bumps 21 and the second bumps 22 are uniformly distributed on the rows, so that the through holes 35 can be uniformly formed on the substrate 10 in the rows.

When the first bumps 21 and the second bumps 22 are uniformly distributed in rows and columns, that is, the spacing distance from each row of the second bumps 22 to two adjacent rows of the first bumps 21 is equal, and the spacing distance from each column of the second bumps 22 to two adjacent columns of the second bumps 22 is equal, so that the multiple rows and multiple columns of the first bumps 21 and the multiple columns of the second bumps 22 can be arranged more tightly, more rows and columns can be arranged on the substrate 10, more first bumps 21 and more second bumps 22 are added, and the electrical performance of the chip is improved.

In an embodiment, referring to fig. 1 and fig. 2, a plurality of through holes 35 are formed on the substrate 10, each through hole 35 is located around the first bump 21 and the second bump 22, and the diameter of each through hole 35 is smaller than the distance between two adjacent rows and two adjacent columns of the first bumps 21.

In the present embodiment, the via 35 is formed to fill metal in the via 35 to transmit electrical signals to the first bump 21 and the second bump 22. The through-hole 35 is typically machined and has a circular cross-sectional shape. The diameter of the through hole 35 needs to satisfy a certain condition, so as to avoid the virtual position caused by the position of the through hole 35 occupying the first bump 21 and the second bump 22, and the embodiment is defined by taking the first bump 21 as a reference. In other embodiments, when the second bumps 22 are used as a reference for definition, the diameter of the through holes 35 should be smaller than the distance between two adjacent rows and two adjacent columns of the second bumps 22. When the first bumps 21 and the second bumps 22 are uniformly distributed on the rows and the columns, one through hole 35 should be surrounded by four bumps, i.e., two bumps on the rows (both the first bumps 21 or the second bumps 22) and two bumps on the columns (both the second bumps 22 or the first bumps 21), and the through hole 35 has the same spacing distance to the two bumps on the rows and the same spacing distance to the two bumps on the columns.

Further, the center of the through hole 35 should be located on the line center line of each line, wherein the line center line refers to the connection line of the geometric center points of the first bumps 21 or the second bumps 22 of each line. With the arrangement, the metal filled in the through holes 35 can be connected with the plurality of first bumps 21 or the plurality of second bumps 22 in rows, so that the occupied space of adjacent rows is reduced, and the plurality of bumps in one row are simultaneously connected through the metal filled in the through holes 35, thereby facilitating the transmission of electric signals in batches.

Optionally, the number of the through holes 35 is smaller than the sum of the numbers of the first bumps 21 and the second bumps 22. Because the plurality of first bumps 21 or the plurality of second bumps 22 in each row need to be electrically connected through the metal filled in the through holes 35, the through holes 35 need to be formed in each row, and because of the structural strength requirement of the substrate 10, the number of the through holes 35 cannot be too large, otherwise, the structural strength of the substrate 10 is damaged, so that the number of the through holes 35 is smaller than the sum of the number of the first bumps 21 and the number of the second bumps 22, and the structural strength of the substrate 10 can be ensured on the basis of meeting the electrical connection. Taking a row of the first bumps 21 as an example, assuming that the number of the first bumps 21 in a row is 20, the number of the through holes 35 in the row may be 2-15, some of the through holes 35 may be disposed adjacent to each other in sequence, and some of the through holes 35 may be disposed further apart. A row of the second bumps 22 may also be referred to as such and will not be described in detail. The plurality of through holes 35 of the whole of the plurality of first salient points 21 and the plurality of second salient points 22 in the plurality of rows and the plurality of columns can be arranged in an irregular discrete manner, and can also be arranged in a certain regular manner, for example, the plurality of through holes 35 are arranged in a plurality of columns, and the number of the columns of the through holes 35 is less than that of the first salient points 21 or the second salient points 22.

In an embodiment, referring to fig. 3 to fig. 5, wherein fig. 4 and fig. 5 are only partial structural illustrations, the substrate 10 includes a first surface 11 and a second surface 12 opposite to each other, the first bump 21 and the second bump 22 are both disposed on the first surface 11, and the through hole 35 penetrates through the first surface 11 and the second surface 12. The through hole 35 may be a cylindrical hole or a truncated cone hole, and when the through hole 35 is a truncated cone hole, the diameter size of the through hole 35 in the foregoing refers to the cross-sectional size of the through hole 35 at the first surface 11.

The chip package structure of the present embodiment further includes a plurality of first connection structures 31 and a plurality of second connection structures 32. The first connection structure 31 and the second connection structure 32 each fill the corresponding through hole 35 and extend at the first surface 11. Each first connection structure 31 connects a row of the plurality of first bumps 21, and each second connection structure 32 connects a row of the plurality of second bumps 22.

Specifically, the first connection structure 31 and the second connection structure 32 may have substantially the same structure, and the first connection structure 31 is taken as an example for detailed description, and the second connection structure 32 may be referred to. The first connection structure 31 includes a filling portion 311 and an extension portion 312, the filling portion 311 is filled in the through hole 35, the extension portion 312 is connected to the filling portion 311, and the extension portion 312 is located on the first surface 11 and connected to the plurality of first bumps 21 in one row. The filling portion 311 and the extending portion 312 may be integrally formed, and may be made of copper. The current flows to the extension portion 312 through the filling portion 311 and is transmitted to the first bump 21, so that the transmission of the electrical signal is realized. The transmission of the electrical signal is realized by the way that the first connection structures 31 fill the through holes 35 and extend to the first surface 11 to be connected with the plurality of first bumps 21 in a row, and the structure is simple and easy to realize. In addition, as described above, the number of the through holes 35 is smaller than that of the first bumps 21 for one row, so that the electrical signal transmission of a larger number of the first bumps 21 can be realized by a smaller number of the filling portions 311, and the structure of the electrical signal transmission can be simplified.

Further, referring to fig. 4 and 5, the first connecting structure 31 includes a first hollow space 315, the second connecting structure 32 includes a second hollow space 325, the first bump 21 is located in the first hollow space 315, and the second bump 22 is located in the second hollow space 325, wherein the periphery of the first hollow space 315 is closed, and/or the periphery of the second hollow space 325 is closed.

Taking the first hollow space 315 as an example, the second hollow space 325 can be referred to. Specifically, referring to fig. 4, in an embodiment, in some rows, the first hollow spaces 315 are in a groove shape extending inward from the edge of the first connecting structure 31, and a side wall of the groove of the first hollow spaces 315 is connected to the first bump 21, in other words, the periphery of the first hollow spaces 315 in the rows is not closed, but has an opening on one side (i.e., the edge of the first connecting structure 31); in other rows, the first hollow space 315 is a square hole formed in the middle of the first connecting structure 31, two opposite side walls of the square hole of the first hollow space 315 are respectively connected to two ends of the first bump 21, in other words, the periphery of the first hollow space 315 in the rows is closed.

In other embodiments, all the rows of the first hollow space 315 are not closed and have openings, or all the rows are closed.

In one embodiment, referring to fig. 1 and 4, the first bumps 21 and the second bumps 22 are oval, and the major axis directions of the oval shapes of the first bumps 21 and the second bumps 22 are consistent with the column direction. In this embodiment, one end or two ends of the first bump 21 on the row are connected to the first connecting structure 31, so that the first hollow space 315 is not closed in some rows, and the first hollow space 315 is closed in other rows.

In one embodiment, referring to fig. 2 and 5, the first bumps 21 and the second bumps 22 are oval, and the major axis directions of the oval shapes of the first bumps 21 and the second bumps 22 are consistent with the row direction. In this embodiment, in all rows, the first hollow space 315 and the second hollow space 325 are enclosed at their peripheries. Compared with the embodiment of fig. 4, the first bump 21 and the second bump 22 of the present embodiment are rotated by 90 ° equivalently, and the two ends of the first bump 21 in the row direction are connected to the first connecting structure 31, so that the row pitch can be further reduced, and more rows can be arranged on the substrate 10, thereby further improving the electrical performance.

In other embodiments, the shapes of the first bump 21 and the second bump 22 may not be limited, and whether the first hollow space 315 and the second hollow space 325 are closed may not be limited, and may be set according to specific situations.

In one embodiment, referring to fig. 3, the chip package structure further includes a plurality of ball pads 33, the plurality of ball pads 33 are disposed on the second surface 12, each ball pad 33 is connected to the first connecting structure 31 or the second connecting structure 32, and a side of the ball pad 33 opposite to the substrate 10 is used for connecting to a solder ball (not shown). In this embodiment, the ball pad 33 may be integrated with the first connecting structure 31 or the second connecting structure 32, and both of them are made of the same material and are used for transmitting electrical signals.

In one embodiment, the first surface 11 and/or the second surface 12 of the substrate 10 may further include an insulating layer, the insulating protective layer 50 may be a green paint, and the insulating protective layer 50 is disposed at the periphery of the plurality of first bumps 21 and the plurality of second bumps 22 and around the ball pads 33, and is used for protecting and insulating the substrate 10 and preventing the first bumps 21 and the second bumps 22, and the first connection structures 31 and the second connection structures 32 from other external electrical signals.

In an embodiment, a transition structure 38 may be further disposed between the first bump 21 and the first connection structure 31, and between the second bump 22 and the second connection structure 32, where the transition structure 38 is used to make the connection between the first bump 21 and the first connection structure 31, and the connection between the second bump 22 and the second connection structure 32 more stable, as shown in fig. 4, the transition structure 38 (not shown in fig. 4) may have one end connected to the first bump 21 and the other end connected to the first connection structure 31 to form a structure similar to a bridge.

Referring to fig. 1 to fig. 5, the present application further provides a chip, which includes a chip body 40 and the chip package structure in the foregoing embodiment, wherein the chip body 40 is connected to the plurality of first bumps 21 and the plurality of second bumps 22. The chip of the present application may be various chips for industrial use, and may also be various chips for cost consumption. Specifically, the chip may be a chip for 5G communication, a computing chip, a memory chip, a light emitting chip, or the like.

The utility model provides a chip, arrange for non-array through the whole that sets up first bump 21 and second bump 22, be equipped with a row of second bump 22 between every adjacent two rows of first bumps 21, arrange for traditional array, the same row interval with be listed as under the interval, can make the space increase between first bump 21 and the second bump 22, satisfy the space basis of seting up through-hole 35 on, can set up more rows and more multiseriate first bump 21 and second bump 22 on base plate 10, thereby can make chip body 40 be connected with more first bumps 21 and second bump 22, thereby promote chip electrical property.

An embodiment of the present application further provides an electronic device, including the chip of the foregoing embodiment. The electronic device of the embodiment may be a device in the industrial field or a device in the consumer field. Specifically, the electronic device may be a 5G communication device, such as a base station, or may be an electronic computer, a smartphone, a wearable device, or the like.

While the invention has been described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention.

Claims

1. The chip packaging structure is characterized by comprising a substrate, a plurality of first bumps and a plurality of second bumps, wherein the first bumps and the second bumps are arranged on the substrate in a plurality of rows and columns, the first bumps are arranged in a plurality of rows and columns, the second bumps are arranged in a plurality of rows and columns, every two adjacent rows are arranged between the first bumps, one row is arranged between the second bumps, and every two adjacent rows are arranged between the first bumps, and one row is arranged between the second bumps.

2. The chip packaging structure according to claim 1, wherein the second bumps in each row are spaced apart from the first bumps in two adjacent rows by equal distances, and/or the second bumps in each column are spaced apart from the second bumps in two adjacent columns by equal distances.

3. The chip packaging structure according to claim 1 or 2, wherein the substrate is provided with a plurality of through holes having a circular cross section, each through hole is located around the first salient point and the second salient point, and the diameter of each through hole is smaller than the distance between two adjacent rows and two adjacent columns of the first salient points.

4. The chip package structure according to claim 3, wherein the center of the through hole is located on a line connecting geometric center points of the first bumps or the second bumps in each row.

5. The chip packaging structure of claim 3, wherein the number of vias is less than the sum of the number of first bumps and the number of second bumps.

6. The chip package structure according to claim 3, wherein the substrate comprises a first surface and a second surface opposite to each other, the first bump and the second bump are both disposed on the first surface, and the through hole penetrates through the first surface and the second surface; the chip packaging structure further comprises a plurality of first connecting structures and a plurality of second connecting structures, the first connecting structures and the second connecting structures are filled in the corresponding through holes and extend from the first surface, each first connecting structure is connected with a plurality of first bumps on one row, and each second connecting structure is connected with a plurality of second bumps on one row.

7. The chip package structure according to claim 6, wherein the first connection structure includes a first hollow space, the second connection structure includes a second hollow space, the first bump is located in the first hollow space, and the second bump is located in the second hollow space, wherein the first hollow space is enclosed at the periphery, and/or the second hollow space is enclosed at the periphery.

8. The chip package structure according to claim 7, wherein the first bumps and the second bumps are oval, major axis directions of the ovals of the first bumps and the second bumps are consistent with a row direction, and peripheries of the first hollowed-out spaces and the second hollowed-out spaces are closed.

9. The chip package structure of claim 6, further comprising a plurality of ball pads, the plurality of ball pads being disposed on the second surface, each of the ball pads being connected to the first connection structure or the second connection structure, a side of the ball pad facing away from the substrate being used for connecting to a solder ball.

10. A chip comprising a chip body and the chip packaging structure according to any one of claims 1 to 9, wherein the chip body is connected to the plurality of first bumps and the plurality of second bumps.

11. An electronic device comprising the chip of claim 10.