CN213751958U

CN213751958U - Device for realizing PDM decoding based on FGPA

Info

Publication number: CN213751958U
Application number: CN202022510529.1U
Authority: CN
Inventors: 叶金生; 谢裕明
Original assignee: Shenzhen Ansheng Technology Co ltd
Current assignee: Shenzhen Ansheng Technology Co ltd
Priority date: 2020-11-03
Filing date: 2020-11-03
Publication date: 2021-07-20
Anticipated expiration: 2030-11-03

Abstract

The utility model discloses a device based on FGPA realizes PDM and decodes relates to PDM technical field that decodes. The FPGA integrated circuit is provided with a data input port, the output end of the data input port is connected with a CIC decimation filter, the output end of the CIC decimation filter is connected with two half-band decimation filters in series, the output end of the second half-band decimation filter is provided with an FIR low-pass filter, and the output end of the FIR low-pass filter is connected with a PC (personal computer) end; the FPGA integrated circuit is fixed in the shell, a clock direction selector and a level shifter are further arranged in the shell, the output end of the level shifter is connected with the clock direction selector, and the output end of the clock direction selector is connected with the FPGA integrated circuit. The utility model discloses an inside PDM signal of realizing of FPGA and becoming the PCM signal, avoided conversion IC to the restriction of function, and have the characteristics of can dynamic adjustment sampling rate, can dynamic adjustment oversampling multiple.

Description

Device for realizing PDM decoding based on FGPA

Technical Field

The utility model discloses a PDM decodes technical field, especially relates to a device based on FGPA realizes PDM and decodes.

Background

Pdm (pulse Density modulation) is a modulation method for representing an analog signal by a digital signal. In the prior art, two signal lines, PDM _ CLK and PDM _ DATA, are used for transmitting binaural DATA in a PDM interface manner, and the left channel DATA is sampled at the rising edge of PDM _ CLK and the right channel DATA is sampled at the falling edge of PDM _ CLK. Because the PDM has a simple structure, the PDM has wide application prospect in occasions with strict space limitation, such as mobile phones, flat panels and the like, and the PDM interface is the most widely applied PDM interface in the field of digital microphones.

With the widespread use of PDM microphones in mobile phones and smart speakers, audio analyzers based on PDM interfaces are more popular with customers, and in the prior art, as shown in fig. 5, a part of PDM to I2S is to implement receiving and also converting PDM signals, and usually, existing PDM to I2SIC such as ADAU7112 in the market is adopted, and then, an MCU is used to implement receiving PCM data on I2S and upload the PCM data to a PC end analysis result.

The PDM receiving is realized by adopting a special IC, although the PDM receiving can be realized quickly and simply, the realization function is limited by the functions of the adopted IC, such as incapability of dynamically adjusting oversampling multiple and sampling rate, incapability of changing PDM level due to IC limitation, and limited channel number

In summary, the problems of the prior art are as follows: the special IC is adopted to realize the receiving of the PDM, the oversampling multiple and the sampling rate cannot be dynamically adjusted, the PDM level is also limited by the IC and cannot be changed, and the number of channels is also limited.

SUMMERY OF THE UTILITY MODEL

In order to overcome the problems existing in the related art, the disclosed embodiments of the present invention provide a device for realizing PDM decoding based on FGPA. The technical scheme is as follows:

the utility model provides a device that realizes PDM decoding in FGPA is provided with:

an audio analyzer;

an FPGA integrated circuit is arranged in the audio analyzer, a data input port is arranged on the FPGA integrated circuit, a CIC decimation filter is connected to the output end of the data input port, two half-band decimation filters are arranged in series at the output end of the CIC decimation filter, an FIR low-pass filter is arranged at the output end of the second half-band decimation filter, and the output end of the FIR low-pass filter is connected with a PC end; the FPGA integrated circuit is also provided with an MCU chip.

Furthermore, the FPGA integrated circuit is fixed in a shell, a clock direction selector and a level shifter are further arranged in the shell, the output end of the level shifter is connected with the clock direction selector, and the output end of the clock direction selector is connected with the FPGA integrated circuit.

Furthermore, the device for realizing PDM decoding based on FGPA is also provided with standard equipment and a controller, wherein the controller is respectively connected with the shell and the standard equipment, and the controller controls the audio analyzer to be tested and/or parameters of the standard equipment according to test instructions.

Further, the standard apparatus includes: the device comprises an alternating voltage standard source, a distortion degree calibrating device, a function signal generator, a standard voltmeter, a universal counter and a low distortion degree measuring instrument; the alternating voltage standard source, the distortion degree calibrating device and the function signal generator are connected with the input end of the audio analyzer; and the standard voltmeter, the universal counter and the low-distortion measuring instrument are connected with the output end of the audio analyzer.

Further, the controller comprises a plurality of control units, and each control unit corresponds to one standard device.

The utility model discloses a technical scheme that embodiment provided can include following beneficial effect:

first, the utility model discloses an inside PDM signal that realizes of FPGA and become the PCM signal, avoided conversion IC to the restriction of function, and have the characteristics of dynamic adjustment sampling rate, dynamic adjustment oversampling multiple, simultaneously, the utility model discloses avoid the passageway restriction, can easily realize 16 passageways even more.

Second, the utility model discloses eliminate external IC, reduced the instrument cost.

Thirdly, the audio analyzer provided by the utility model realizes the automation of calibration, reduces the manual intervention, reduces the workload of the calibration personnel, reduces the introduction of errors and improves the accuracy of calibration; compared with manual calibration, the calibration time of each channel is shortened, the calibration period is further shortened, and the working efficiency is improved.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and together with the description, serve to explain the principles of the disclosure.

Fig. 1 is a schematic structural diagram of an apparatus for implementing PDM decoding based on FGPA according to an embodiment of the present invention.

Fig. 2 is a schematic structural diagram of an audio analyzer provided in an embodiment of the present invention.

Fig. 3 is a schematic structural diagram of an FPGA integrated circuit according to an embodiment of the present invention.

Fig. 4 is a schematic structural diagram of a standard device provided in an embodiment of the present invention.

Fig. 5 is a schematic diagram of an audio analyzer provided in the prior art.

Fig. 6 is a diagram illustrating the comparison effect between the PCM signal and the PDM signal according to an embodiment of the present invention.

Fig. 7 is an amplitude-frequency characteristic diagram of a 6-stage comb filter provided by an embodiment of the present invention.

Fig. 8 is a schematic diagram of implementing chirp by an FPGA integrated circuit according to an embodiment of the present invention.

Reference numerals:

1. a controller; 2. standard equipment; 3. an audio analyzer; 4. a standard source of alternating voltage; 5. a distortion degree calibrating device; 6. a function signal generator; 7. a standard voltmeter; 8. a general purpose counter; 9. a low distortion factor measurement instrument; 10. a level shifter; 11. a clock direction selector; 12. an FPGA integrated circuit; 13. a PC terminal; 14. a data input port; 15. a CIC decimation filter; 16. a half-band decimation filter; 17. an FIR low pass filter.

Detailed Description

In order to make the above objects, features and advantages of the present invention more comprehensible, embodiments of the present invention are described in detail below with reference to the accompanying drawings. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. The present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein, but rather should be construed as broadly as the present invention is capable of other embodiments without departing from the spirit and scope thereof as defined by the appended claims.

It will be understood that when an element is referred to as being "secured to" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present. As used herein, the terms "vertical," "horizontal," "left," "right," and the like are for illustrative purposes only and do not denote a single embodiment.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

As shown in fig. 1 to fig. 4, an apparatus for implementing PDM decoding based on FGPA provided by the embodiment of the present invention includes: the device comprises a controller 1, standard equipment 2, an audio analyzer 3, an alternating voltage standard source 4, a distortion degree calibrating device 5, a function signal generator 6, a standard voltmeter 7, a universal counter 8, a low distortion degree measuring instrument 9, a level converter 10, a clock direction selector 11, an FPGA integrated circuit 12, a PC end 13, a data input port 14, a CIC decimation filter 15, a half-band decimation filter 16 and an FIR low-pass filter 17.

In the present embodiment, an FPGA integrated circuit 12 is disposed in the audio analyzer 3, the FPGA integrated circuit 12 is provided with a data input port 14, an output end of the data input port 14 is connected to a CIC decimation filter 15, an output end of the CIC decimation filter 15 is connected in series to two half-band decimation filters 16, an output end of the second half-band decimation filter 16 is provided with an FIR low-pass filter 17, and an output end of the FIR low-pass filter 17 is connected to a PC terminal 13; the FPGA integrated circuit 12 is also provided with an MCU chip; the FPGA integrated circuit 12 is fixed in the shell, a clock direction selector 11 and a level shifter 10 are further arranged in the shell, the output end of the level shifter 10 is connected with the clock direction selector 11, and the output end of the clock direction selector 11 is connected with the FPGA integrated circuit 12; the access to the level shifter 10 enables the instrument to match any level of PDM production.

The utility model discloses an inside PDM signal of realizing of FPGA and becoming the PCM signal, avoided conversion IC to the restriction of function, and have characteristics that can dynamic adjustment sampling rate, can dynamic adjustment oversampling multiple, simultaneously, the utility model discloses avoid the passageway restriction, can easily realize 16 passageways or more passageways.

In this embodiment, the apparatus for implementing PDM decoding based on FGPA is further provided with a standard device 2 and a controller 1, the controller 1 is respectively connected with the housing and the standard device 2, and the controller 1 controls parameters of the audio analyzer 3 to be tested and/or the standard device 2 according to the test instruction.

The standard apparatus 2 includes: the device comprises an alternating voltage standard source 4, a distortion degree calibrating device 5, a function signal generator 6, a standard voltmeter 7, a universal counter 8 and a low distortion degree measuring instrument 9; the alternating voltage standard source 4, the distortion degree calibrating device 5 and the function signal generator 6 are connected with the input end of the audio analyzer 3; and the standard voltmeter 7, the universal counter 8 and the low-distortion measuring instrument 9 are connected with the output end of the audio analyzer 3.

The controller 1 includes a plurality of control units, each corresponding to one of the standard devices 2.

The audio analyzer 3 provided by the utility model realizes the automation of calibration, reduces the manual intervention, reduces the workload of the calibration personnel, reduces the introduction of errors, and improves the accuracy of calibration; compared with manual calibration, the calibration time of each channel is shortened, the calibration period is further shortened, and the working efficiency is improved.

The utility model discloses a theory of operation does:

the PDM data receiving module receives an external PDM interface signal into a single-

bit

0 and 1 value sequence according to a time sequence; 0. after the 1-value sequence passes through the

CIC decimation filter

15 and 2 FIR half-band filters, the single-bit sequence becomes a multi-bit PCM value sequence, wherein the density components represented by 0 and 1 are converted into amplitude components by the decimation filter when PDM is converted into PCM, as shown in fig. 6.

In FPGA implementation, a comb filter is adopted to realize conversion from PDM signals to PCM. The comb filter has a simple structure, only has multiplying and adding units, can realize the down-sampling conversion at multiple times of speed, and can filter high-frequency components. When the FPGA is realized, a 6-level extraction comb filter is adopted, the extraction multiple can be set according to the oversampling multiple, because the amplitude-frequency characteristic of the comb filter is only related to the cascade number of the comb filter and is not related to the extraction multiple, the design of the comb filter cannot be influenced by changing the extraction multiple, and the amplitude-frequency characteristic of the 6-level cascade is shown in figure 7.

Because the frequency response of the comb filter is not smooth, a compensation FIR filter is added for compensation, so that the frequency response of the whole conversion circuit becomes smooth.

During calibration, the PC terminal 13 is connected to the audio analyzer 3 and all the standard devices 2 through the bus, and respective communication addresses are set, and the communication addresses are not repeated, so that the plurality of standard devices 2 can operate simultaneously, calibration time is further shortened, and detection efficiency is submitted. According to different calibration functions, the controller 1 sends a control instruction to the audio analyzer 3 through the bus, and the audio analyzer 3 completes compared function selection and compared parameter setting after receiving the instruction; the controller 1 also sends a control instruction to the standard equipment 2 with the specified address through the bus, the standard equipment 2 completes the setting of the calibration parameters after receiving the instruction, and opens an input or output channel to complete the calibration. The controller 1 also collects test data, finally generates a test report, and completes the automatic calibration of the audio analyzer 3.

Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any variations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.

It will be understood that the present disclosure is not limited to the precise arrangements described above and shown in the drawings and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure should be limited only by the attached claims.

Claims

1. An apparatus for implementing PDM decoding based on FGPA is provided with:

an audio analyzer;

an FPGA integrated circuit is arranged in the audio analyzer, a data input port is arranged on the FPGA integrated circuit, a CIC decimation filter is connected to the output end of the data input port, two half-band decimation filters are connected in series to the output end of the CIC decimation filter, an FIR low-pass filter is arranged at the output end of one of the half-band decimation filters, and a PC end is connected to the output end of the FIR low-pass filter; the FPGA integrated circuit is also provided with an MCU chip.

2. The apparatus of claim 1, wherein the FPGA integrated circuit is fixed in a housing, and a clock direction selector and a level shifter are further disposed in the housing, wherein the output terminal of the level shifter is connected to the clock direction selector, and the output terminal of the clock direction selector is connected to the FPGA integrated circuit.

3. The apparatus for implementing PDM decoding based on FGPA as claimed in claim 2, wherein the apparatus for implementing PDM decoding based on FGPA is further provided with standard equipment and a controller, the controller is respectively connected to the housing and the standard equipment, and the controller controls the parameters of the audio analyzer and/or the standard equipment according to the test instructions.

4. The apparatus of claim 3, wherein the standard device comprises: the device comprises an alternating voltage standard source, a distortion degree calibrating device, a function signal generator, a standard voltmeter, a universal counter and a low distortion degree measuring instrument; the alternating voltage standard source, the distortion degree calibrating device and the function signal generator are connected with the input end of the audio analyzer; and the standard voltmeter, the universal counter and the low-distortion measuring instrument are connected with the output end of the audio analyzer.

5. The apparatus of claim 3, wherein the controller comprises a plurality of control units, each of the control units corresponding to one of the standard devices.