CN213660412U

CN213660412U - Super junction device

Info

Publication number: CN213660412U
Application number: CN202022983441.1U
Authority: CN
Inventors: 徐大朋; 薛忠营; 罗杰馨; 柴展
Original assignee: Shanghai Industrial Utechnology Research Institute; Shanghai Gongcheng Semiconductor Technology Co Ltd
Current assignee: Shanghai Gongcheng Semiconductor Technology Co Ltd
Priority date: 2020-12-08
Filing date: 2020-12-08
Publication date: 2021-07-09
Anticipated expiration: 2030-12-08

Abstract

The utility model provides a super junction device, include: 1) providing a first substrate, wherein the first substrate comprises a first main surface and a second main surface, and etching a groove on the first main surface of the first substrate through a photoetching-etching process based on a photomask, wherein the groove is in an inverted trapezoid shape; 2) bonding the first substrate to the second substrate; 3) thinning the first substrate and reserving a supporting layer; 4) oxidizing the supporting layer, and corroding to remove the oxide layer to expose the groove; 5) and etching the bottom of the groove based on a hard mask plate with the same pattern as the photomask to increase the width of the bottom of the groove and enable the appearance of the groove to be rectangular. The utility model discloses a carry out the sculpture from the less slot bottom of width to increase the size of this slot bottom, thereby make this slot be the rectangle, thereby reduce the charge gap of the P type post and the N type post in the super junction structure, make super junction device reach charge balance, thereby improve the voltage resistance of super junction device and reduce the on-resistance who surpasses the junction device.

Description

Super junction device

Technical Field

The utility model belongs to semiconductor device design and manufacturing field especially relates to a super junction device.

Background

In the Field of power semiconductors, a vertical Metal Oxide Semiconductor Field Effect Transistor (MOSFET) formed by a vertical double diffusion process is called a VDMOSFET, which is abbreviated as a VDMOS. For conventional VDMOS, the breakdown voltage is generally increased by increasing the epitaxial layer thickness and decreasing the epitaxial layer doping concentration, but this approach results in a significant increase in the epitaxial layer resistance. A Super junction Metal oxide semiconductor Field Effect Transistor (SJ-MOSFET) is an improved structure of a VDMOS device, and a P-type upright post and an N-type upright post are formed by adding alternate P-N structures in an epitaxial layer, so that when the device is in a blocking state, a longitudinal electric Field in the epitaxial layer is almost constant, the dependence of the on-resistance of the device on breakdown voltage is greatly reduced, and the on-state loss of the device is reduced. Therefore, the structure is widely applied to devices with high breakdown voltage.

SUMMERY OF THE UTILITY MODEL

In view of the above prior art's shortcoming, the utility model aims at providing a surpass knot device for solve among the prior art that the gained slot of sculpture is for falling the trapezium structure, lead to surpassing the electric charge of knot P type post and N type post and have great disparity, be unfavorable for charge balance and cause the withstand voltage problem that reduces of device.

In order to achieve the above objects and other related objects, the present invention provides a method for manufacturing a super junction device, the method comprising: 1) providing a first substrate, wherein the first substrate comprises a first main surface and a second main surface which are opposite, and etching a groove on the first main surface of the first substrate through a photoetching-etching process based on a photomask, wherein the groove is in an inverted trapezoid shape; 2) providing a second substrate, and bonding the first main surface of the first substrate with the second substrate; 3) thinning the first substrate from the second main surface of the first substrate, and reserving a support layer between the second main surface of the first substrate and the groove; 4) oxidizing the supporting layer to form an oxide layer, and removing the oxide layer through corrosion to expose the groove; 5) based on the hard mask plate with the same photomask graph as the photomask graph in the step 1), after the hard mask plate is aligned with the groove, the bottom of the groove is directly etched, so that the width of the bottom of the groove is increased, and the appearance of the groove is approximately rectangular.

Optionally, the width of the bottom of the trench in step 1) is between one quarter and three quarters of the width of the top.

Optionally, the depth of the groove is between 1 and 50 microns.

Optionally, the depth of the groove is between 30 and 45 microns.

Optionally, the etching method in step 1) and step 5 includes one of Reactive Ion Etching (RIE) and deep silicon etching (ICP).

Optionally, in step 3), the first substrate is thinned by using a chemical mechanical polishing process, and the thickness of the thinned support layer is between 0.5 micrometers and 2 micrometers.

Optionally, the manufacturing method further comprises the steps of: 6) the first substrate is doped with a first conduction type, and the groove is filled with a semiconductor material layer doped with a second conduction type so as to form a super junction structure together with the first substrate.

Optionally, the manufacturing method further comprises the steps of: 7) forming a second conductivity type body region on the super junction structure; 8) forming a first conductive type source region in the second conductive type body region; 9) manufacturing a grid structure on the first conduction type source region and the second conduction type body region; 10) forming an insulating layer and an electrode lead-out structure; wherein the second substrate includes a first conductive type drain region.

Optionally, step 8) further comprises the step of forming a second conductivity type contact region in the first conductivity type source region.

Optionally, the first conductivity type is an N type, and the second conductivity type is a P type, or the first conductivity type is a P type, and the second conductivity type is an N type.

The utility model also provides a super junction device, super junction device includes: a first conductivity type drain region; the super junction structure is positioned on the first conduction type drain region and comprises a first conduction type column and a second conduction type column which are sequentially arranged, and the first conduction type column and the second conduction type column are rectangular in shape; a second conductivity type body region formed on the super junction structure; a first conductive type source region formed in the second conductive type body region; a gate structure formed on the first conductive type source region and the second conductive type body region; and the insulating layer and the electrode lead-out structure are positioned on the first conduction type source region and the grid structure.

Optionally, a second conductive type contact region formed in the first conductive type source region is further included.

Optionally, the depth of the super junction structure is between 30 and 45 microns.

As described above, the super junction device of the present invention has the following beneficial effects:

the utility model discloses a be formed with the sculpture and fall the first substrate and the bonding of second substrate of trapezoidal slot, the back attenuate exposes this back of falling the bottom of trapezoidal slot, carry out the sculpture from the less slot bottom of this width to increase the size of this slot bottom, thereby make this slot be the rectangle, thereby reduce the charge gap of the P type post and the N type post in the super junction structure, make super junction device reach charge balance, thereby improve the voltage resistance of super junction device and reduce the on-resistance of super junction device.

The utility model discloses a fall the hard mask version that trapezoidal slot has the same figure with the sculpture, directly carry out the sculpture so that the slot is the rectangle to falling trapezoidal slot bottom, need not carry out the step of photoetching, can practice thrift process cost greatly.

The utility model discloses a chemical mechanical polishing, oxidation, the method of getting rid of the oxide layer carry out the attenuate to the substrate, compare in direct grinding and show out the slot, the supporting layer that remains can provide the support for slot and lateral wall when grinding, can effectively avoid direct grinding to cause the risk that the slot lateral wall collapses easily when showing the slot, improves process stability.

The utility model discloses super junction device made has that technological stability is high, withstand voltage energy is strong and on-resistance is low advantage.

Drawings

Fig. 1 to fig. 10 show schematic structural diagrams of steps of a method for manufacturing a super junction device according to an embodiment of the present invention.

Description of the element reference numerals

101 first substrate

102 trench

103 second substrate

104 support layer

105 oxide layer

106 hard mask

201 drain region

202 drain electrode

203N type column

204P type column

205 body region

206 source region

207 contact zone

208 gate structure

209 insulating layer

210 electrode lead-out structure

Detailed Description

The following description of the embodiments of the present invention is provided for illustrative purposes, and other advantages and effects of the present invention will be readily apparent to those skilled in the art from the disclosure herein. The present invention can also be implemented or applied through other different specific embodiments, and various details in the present specification can be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

As in the detailed description of the embodiments of the present invention, the cross-sectional views illustrating the device structure are not partially enlarged in general scale for convenience of illustration, and the schematic views are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.

For convenience in description, spatial relational terms such as "below," "beneath," "below," "under," "over," "upper," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these terms of spatial relationship are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. Further, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

In the context of this application, a structure described as having a first feature "on" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed in between the first and second features, such that the first and second features may not be in direct contact.

It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and only the components related to the present invention are shown in the drawings rather than being drawn according to the number, shape and size of the components in actual implementation, and the form, amount and ratio of the components in actual implementation may be changed at will, and the layout of the components may be more complicated.

The key of the super junction device capable of realizing high voltage resistance and low on-resistance is that P-N charge balance is achieved by forming an N-type conductive region and a P-type conductive region in a substrate. Therefore, the ideal P-type conductive region is rectangular, but due to the limitation of the etching process, the etched trench can only be in an inverted trapezoidal structure, so that the charges of the P-type column and the N-type column at different depths have a large difference, which is not favorable for charge balance and has a certain influence on the voltage resistance of the device.

In order to solve the problem that the charge difference between the P-type column 204 and the N-type column 203 is large and is not favorable for charge balance, the present embodiment provides a method for manufacturing a super junction device, including the following steps:

as shown in fig. 1 to 2, step 1) is performed first, a first substrate 101 is provided, where the first substrate 101 includes a first main surface and a second main surface opposite to each other, and a trench 102 is etched in the first main surface of the first substrate 101 through a photolithography-etching process based on a photomask, where the trench 102 has an inverted trapezoid shape.

The first substrate 101 may be a semiconductor substrate such as a silicon substrate, a silicon germanium substrate, or a germanium substrate, and in this embodiment, the first substrate 101 is an N-type lightly doped silicon substrate.

Based on a photomask, a trench 102 is etched on the first main surface of the first substrate 101 by a lithography-etching process, the etching method may be, for example, one of ordinary plasma etching, reactive ion etching RIE and deep silicon etching ICP, and since the trench 102 has a high aspect ratio, for example, above 10:1, and due to the limitation of the etching process, the sidewall of the etched trench 102 is inclined inward from the top of the trench 102 to the bottom of the trench 102, the trench 102 is in an inverted trapezoid shape. For example, the width of the bottom of the inverted trapezoidal shaped trench 102 is between one quarter and three quarters of the width of the top, and in a particular implementation, the width of the bottom of the inverted trapezoidal shaped trench 102 is one quarter of the width of the top.

The depth of the trench 102 may be between 1-50 μm, depending on the device size requirement. Preferably, the depth of the trench 102 is between 30 and 45 microns.

As shown in fig. 3 and 4, step 2) is then performed to provide a second substrate 103, and the first main surface of the first substrate 101 is bonded to the second substrate 103.

In this embodiment, the second substrate 103 is made of the same material as the first substrate 101, and the second substrate 103 is an N-type lightly doped silicon substrate. The bonding method of the first substrate 101 and the second substrate 103 may be a silicon direct bonding process.

As shown in fig. 5, step 3) is performed to thin the first substrate 101 from the second major surface of the first substrate 101, so that a support layer 104 remains between the second major surface of the first substrate 101 and the trench 102.

For example, a chemical mechanical polishing process may be used to thin the first substrate 101 from the second major surface of the first substrate 101, so that a support layer 104 remains between the second major surface of the first substrate 101 and the trench 102, the thickness of the thinned support layer 104 is between 0.5 microns and 2 microns, and in a specific embodiment, the thickness of the thinned support layer 104 is 1 micron.

As shown in fig. 6 to 7, step 4) is performed to oxidize the support layer 104 to form an oxide layer 105, and the oxide layer 105 is removed by etching to expose the trench 102.

In this embodiment, the supporting layer 104 is oxidized by a thermal oxidation process, so that the supporting layer 104 is completely oxidized to form an oxide layer 105, and then the oxide layer 105 is removed by a wet etching process to expose the trench 102, wherein an etching solution used in the wet etching process has a high selectivity to silicon dioxide and silicon, for example, the etching solution may be hydrofluoric acid (HF).

The utility model discloses a chemical mechanical polishing, oxidation, the method of getting rid of oxide layer 105 carry out the attenuate to the substrate, compare in direct grinding and show out slot 102, the supporting layer 104 that remains can provide the support for slot 102 and lateral wall when grinding, can effectively avoid direct grinding to cause the risk that slot 102 lateral wall collapses easily when showing slot 102, improve process stability.

As shown in fig. 8 to 9, step 5) is performed, based on the hard mask 106 having the same photomask pattern as the photomask pattern in step 1), after the hard mask 106 is aligned with the trench 102, the bottom of the trench 102 is directly etched to increase the width of the bottom of the trench 102, so that the trench 102 has a rectangular shape.

The etch shown may be one of normal plasma etch, reactive ion etch RIE and deep silicon etch ICP. The depth of the etching may be set to be the same as the depth of the trench 102 to ensure that the profile of the trench 102 is substantially rectangular, which means that the profile of the trench 102 is substantially rectangular, which may include a certain degree of profile variation due to errors caused by technical or process limitations, and such profile variation should not be excluded from the scope of the claims.

The utility model discloses a fall trapezoidal slot 102 with the sculpture and have the hard mask version 106 of the same figure, directly carry out the sculpture so that slot 102 is the rectangle to falling trapezoidal slot 102 bottom, need not carry out the step of photoetching, can practice thrift process cost greatly.

As shown in fig. 10, step 6) is performed to make the first substrate 101 doped with the first conductivity type, and the trench 102 is filled with a semiconductor material layer doped with the second conductivity type to form a super junction structure together with the first substrate 101.

For example, the second conductive-type-doped semiconductor material layer may be a P-type silicon layer, and the P-type silicon layer and the N-type-doped first substrate 101 are arranged together to form a super junction structure in which P-type columns 204 and N-type columns 203 are alternately arranged.

The utility model discloses a be formed with the sculpture and fall trapezoidal slot 102's first substrate 101 and the bonding of second substrate 103, the back attenuate exposes this back of falling trapezoidal slot 102, carry out the sculpture from the less slot 102 bottom of this width, with the size of this slot 102 bottom of increase, thereby make this slot 102 be the rectangle, thereby reduce the charge difference of P type post 204 and N type post 203 in the super junction structure, make super junction device reach charge balance, thereby improve super junction device's voltage endurance and reduce the on-resistance who surpasses junction device.

As shown in fig. 10, step 7) is followed by forming a second conductivity-type body region 205 on the superjunction structure.

For example, P-type body region 205 may be formed on the superjunction structure by an ion implantation process.

As shown in fig. 10, step 8) is followed by forming first conductivity-type source regions 206 in the second conductivity-type body regions 205.

For example, N-type source regions 206 may be formed in the P-type body regions 205 by a photolithography process and an ion implantation process. In this step, a step of forming a P-type contact region 207 in the N-type source region 206 by an ion implantation process is further included to facilitate electrical extraction of the subsequent N-type source region 206.

As shown in fig. 10, step 9) is then performed to fabricate a gate structure 208 on the first-conductivity-type source regions 206 and the second-conductivity-type body regions 205.

As shown in fig. 10, step 10) is finally performed, forming an insulating layer 209 and an electrode lead-out structure 210.

In this embodiment, a first conductive type drain region 201 is formed in the second substrate 103, a drift region of a first conductive type may also be formed on the first conductive type drain region 201, the drift of the first conductive type and the first substrate 101 are bonded to form a drift region of a super junction device together, and a drain electrode 202 is further formed on the first conductive type drain region 201.

In this embodiment, the first conductive type is an N type, and the second conductive type is a P type, but in other embodiments, the first conductive type may also be a P type, and the second conductive type may also be an N type.

As shown in fig. 10, the present embodiment also provides a super junction device including: a first conductive type drain region 201; the super junction structure is positioned on the first conduction type drain region and comprises an N-type column 203 and a P-type column 204 which are sequentially arranged, and the N-type column 203 and the P-type column 204 are almost rectangular in shape; a second conductivity type body region 205 formed on the super junction structure; a first conductive-type source region 206 formed in the second conductive-type body region 205; a gate structure 208 formed on the first conductive type source region 206 and the second conductive type body region 205; an insulating layer 209 and an electrode extension structure 210 are disposed on the first conductive type source region 206 and the gate structure 208.

In this embodiment, the superjunction device further includes a second conductive-type contact region 207 formed in the first conductive-type source region 206.

In the embodiment, the depth of the super junction structure is between 30 and 45 micrometers.

The utility model discloses a chemical mechanical polishing, oxidation, the method of getting rid of the oxide layer carry out the attenuate to the substrate, compare and show out slot 102 in direct grinding, the supporting layer 104 that remains can provide the support for slot 102 and lateral wall when grinding, can effectively avoid direct grinding to cause the risk that slot 102 lateral wall collapses easily when showing slot 102, improves process stability.

The utility model discloses super junction device made has the advantage that technological stability is high, and the withstand voltage can be strong.

Therefore, the utility model effectively overcomes various defects in the prior art and has high industrial utilization value.

The above embodiments are merely illustrative of the principles and effects of the present invention, and are not to be construed as limiting the invention. Modifications and variations can be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which may be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims

1. A super junction device, comprising:

a first conductivity type drain region;

the super junction structure is positioned on the first conduction type drain region and comprises a first conduction type column and a second conduction type column which are sequentially arranged, and the first conduction type column and the second conduction type column are rectangular in shape;

a second conductivity type body region formed on the super junction structure;

a first conductive type source region formed in the second conductive type body region;

a gate structure formed on the first conductive type source region and the second conductive type body region;

and the insulating layer and the electrode lead-out structure are positioned on the first conduction type source region and the grid structure.

2. The superjunction device of claim 1, wherein: and a second conductive type contact region formed in the first conductive type source region.

3. The superjunction device of claim 1, wherein: the depth of the super junction structure is 30-45 micrometers.

4. The superjunction device of claim 1, wherein: the first conductive type is an N type, the second conductive type is a P type, or the first conductive type is a P type, and the second conductive type is an N type.