CN117832267A - Super-junction MOSFET structure and preparation method thereof - Google Patents
Super-junction MOSFET structure and preparation method thereof Download PDFInfo
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Abstract
The invention provides a super-junction MOSFET structure and a preparation method thereof, wherein the super-junction MOSFET structure comprises a substrate, a first epitaxial layer, a second epitaxial layer, a source region, a grid structure, a source electrode and a drain electrode, wherein a plurality of layers of first epitaxial layers are sequentially stacked and positioned above the substrate, a second conductive type column region is arranged in the first epitaxial layer, second conductive type columns stacked upwards are formed in the second conductive type column region, adjacent second conductive type column regions are arranged at intervals, and the outer part of the second conductive type column region is a first column region; a body region is arranged in the second epitaxial layer, and the outer part of the body region is divided into a second column region and forms a first conductive type column with the first column region; the source region is positioned in the body region; the grid structure is positioned on the upper surface of the first conductive type column; the source electrode is positioned on the upper surface of the body region, and the drain electrode is positioned on the lower surface of the substrate. The invention utilizes the second conductive type column structures formed by the second conductive type column structures which are arranged at intervals, reduces the hole extraction speed in the device and improves the reverse recovery softness factor of the device.
Description
Technical Field
The invention belongs to the field of semiconductor integrated circuit manufacturing, and relates to a super-junction MOSFET structure and a preparation method thereof.
Background
With the increase of breakdown voltage, the vertical double diffusion goldThe resistivity and thickness of the epitaxial layer in the oxide semiconductor structure (VDMOS) need to be increased, resulting in a device with a large on-resistance, which is related to the breakdown voltage: r is equal to BV 2.5 This is known as the 'silicon limit'. In order to reduce the on-resistance of the device or break through the silicon limit, currently, a superjunction technology (charge compensation technology: chen-e, semiconductor power device, patent No. CN1056018A, 1991) is generally adopted, as shown in fig. 1, which is a schematic cross-sectional structure of a superjunction MOSFET structure, and includes a substrate 01, an epitaxial layer 02, a first conductive type column 021, a second conductive type column 022, a body 023, a source 024, a gate structure 03, a gate dielectric layer 031, a gate 032, a source 04 and a drain 05, where the relationship between the on-resistance and breakdown voltage in the superjunction MOSFET device is:wherein breakdown voltage bv=e C t pillar 。
However, the use of super junction structures allows the device to be turned offThe excessive reverse recovery current is increased, the reverse recovery time is reduced, the softness factor is small, current overshoot is easy to generate, and the device is damaged.
Therefore, there is an urgent need to find a superjunction MOSFET structure that reduces the device reverse recovery softness factor.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a super-junction MOSFET structure and a method for manufacturing the same, which are used for solving the problem of small reverse recovery softness factor of the super-junction MOSFET in the prior art.
To achieve the above and other related objects, the present invention provides a method for manufacturing a super junction MOSFET structure, comprising the steps of:
providing a first conductive type substrate;
forming a plurality of layers of first conductive type first epitaxial layers which are sequentially stacked upwards on the upper surface of the substrate, wherein a plurality of second conductive type column regions with preset intervals are formed in each layer of first epitaxial layers, the stacked second conductive type column regions form second conductive type columns, the part, except the second conductive type columns, in the first epitaxial layers is used as a first column region, and the preset intervals are formed between two adjacent second conductive type column regions in the second conductive type columns;
forming a first conductive type second epitaxial layer on the upper surface of the first epitaxial layer, forming a second conductive type body region in the second epitaxial layer above the second conductive type column, wherein the bottom surface of the body region is in contact with the second conductive type column, the part, except the body region, in the second epitaxial layer is used as a second column region, and the first column region and the second column region form a first conductive type column;
forming two source regions of a first conductivity type in the body region at intervals, wherein the source regions are spaced from the side walls of the body region by a preset distance, a gate structure is formed on the upper surface of the first conductivity type column, and the side walls of the gate structure extend to the upper part of the source region;
and forming a source electrode on the upper surface of the body region between the two source regions, wherein the side wall of the source electrode extends to the upper side of the source region, and forming a drain electrode on the lower surface of the substrate.
Optionally, the method of forming the second conductivity type pillar region includes ion implantation.
Optionally, the ion implantation dose of the second conductive type column region is 70% -130% of the ion implantation dose of the first epitaxial layer.
Optionally, a separation distance between two adjacent second conductive type column regions in the second conductive type column is smaller than an expansion width of the depletion layer.
Optionally, the method for forming the second conductive type column region includes chemical vapor deposition and physical vapor deposition.
Optionally, after forming each layer of the first epitaxial layer, a step of forming a trench in the first epitaxial layer is further included before forming the second conductivity type pillar region.
Optionally, the second conductivity type pillar region fills the trench.
Optionally, the number of stacked layers of the first epitaxial layer is not less than 2.
The invention also provides a super junction MOSFET structure, which comprises:
a first conductivity type substrate;
a plurality of layers of first conductive type first epitaxial layers which are sequentially stacked upwards and are positioned on the upper surface of the substrate, a plurality of second conductive type column regions which are arranged at intervals are arranged in each layer of first epitaxial layers, the stacked second conductive type column regions form second conductive type columns, the first epitaxial layers outside the second conductive type columns are used as first column regions, and a preset distance is reserved between two adjacent second conductive type column regions in the second conductive type columns;
a second epitaxial layer of a first conductivity type, which is positioned on the upper surface of the first epitaxial layer, wherein a second conductivity type body region is arranged in the second epitaxial layer above the second conductivity type column, the bottom surface of the body region is contacted with the upper surface of the second conductivity type column, the part of the second epitaxial layer outside the body region is used as a second column region, and the first column region and the second column region form a first conductivity type column;
two source regions of the first conductivity type arranged at intervals are positioned in the body region, and the side walls of the source regions are spaced from the side walls of the body region by a preset distance;
a gate structure on the upper surface of the first conductivity type pillar, the sidewall of the gate structure extending above the source region;
the source electrode is positioned on the upper surface of the body region between the source regions, the side wall of the source electrode extends to the upper surface of the source region, and the drain electrode is positioned on the lower surface of the substrate.
Optionally, a trench is further provided in each layer of the first epitaxial layer, and the second conductivity type column region fills the trench.
Optionally, a separation distance between two adjacent second conductive type column regions in the second conductive type column is smaller than an expansion width of the depletion layer.
As described above, in the super junction MOSFET structure and the method for manufacturing the same, the first epitaxial layer is formed multiple times by adjusting the process of forming the second conductive type column, and after each epitaxial layer is formed, the second conductive type column regions are formed in the first epitaxial layer, so that a plurality of second conductive type column regions are formed in the second conductive type column at intervals, and the interval distance between two adjacent second conductive type column regions in the second conductive type column is smaller than the development width of the depletion layer of the device, so that the voltage of the second conductive type column region electrically connected with the top layer acts on the second conductive type column region below the second conductive type column region at the top layer, thereby ensuring the reverse breakdown voltage of the device; due to the fact that the adjacent two second conduction type column regions are arranged at intervals, the expansion of the depletion layer in the device is segmented, the expansion of the depletion layer in the device is slow, the depletion layer between the adjacent two second conduction type column regions is formed, the extraction speed of holes in the device is delayed, the hole extraction speed of the device is slow, the current change speed in the device is restrained, the problem that current overshoot in the device is caused due to too fast current change when reverse voltage is applied is solved, and the reverse recovery softness factor of the device is improved. In addition, in the super junction MOSFET structure, the second conductive type column structures are formed by utilizing a plurality of second conductive type column structures which are arranged at intervals, and the super junction MOSFET structure is combined with a minority carrier lifetime control process, so that the reverse recovery softness factor of the device can be further improved, and the super junction MOSFET structure has high industrial utilization value.
Drawings
Fig. 1 is a schematic cross-sectional view of a super junction MOSFET structure.
Fig. 2 is a process flow diagram of a method of fabricating a superjunction MOSFET structure according to the present invention.
Fig. 3 is a schematic cross-sectional view of a substrate of the method for fabricating a super junction MOSFET structure according to the present invention.
Fig. 4 is a schematic cross-sectional view of the super-junction MOSFET structure according to the present invention after forming the second conductivity type pillar.
Fig. 5 is a schematic cross-sectional view of a super junction MOSFET structure according to the present invention after forming a body region.
Fig. 6 is a schematic cross-sectional view of the super-junction MOSFET structure of the present invention after forming a source region.
Fig. 7 is a schematic cross-sectional view of the super-junction MOSFET structure of the present invention after forming the source and gate structures.
Fig. 8 is a schematic cross-sectional view of a super junction MOSFET structure according to the present invention after forming a drain.
Fig. 9 shows a reverse recovery curve of the super junction MOSFET structure of fig. 1 and a super junction MOSFET structure of a different column pitch of the second conductivity type of the present invention.
Fig. 10 shows reverse breakdown curves of the superjunction MOSFET structure of fig. 1 and a superjunction MOSFET structure of a different column pitch of the second conductivity type of the present invention.
Description of element reference numerals
01. Substrate and method for manufacturing the same
02. Epitaxial layer
021. First conductivity type column
022. Second conductivity type column
023. Body region
024. Source region
03. Gate structure
031. Gate dielectric layer
032. Grid electrode
04. Source electrode
05. Drain electrode
1. Substrate and method for manufacturing the same
2. First epitaxial layer
21. Second conductivity type column region
22. Second conductivity type column
23. First column region
3. Second epitaxial layer
31. Body region
32. Second column zone
33. First conductivity type column
34. Source region
4. Gate structure
41. Gate dielectric layer
42. Grid electrode
5. Source electrode
6. Drain electrode
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
Please refer to fig. 2 to fig. 10. It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
Example 1
The embodiment provides a preparation method of a super junction MOSFET structure, as shown in FIG. 2, which is a process flow chart of the preparation method of the super junction MOSFET structure, and comprises the following steps:
s1: providing a first conductive type substrate;
s2: forming a plurality of layers of first conductive type first epitaxial layers which are sequentially stacked upwards on the upper surface of the substrate, wherein a plurality of second conductive type column regions with preset intervals are formed in each layer of first epitaxial layers, the stacked second conductive type column regions form second conductive type columns, the part, except the second conductive type columns, in the first epitaxial layers is used as a first column region, and the preset intervals are formed between two adjacent second conductive type column regions in the second conductive type columns;
s3: forming a first conductive type second epitaxial layer on the upper surface of the first epitaxial layer, forming a second conductive type body region in the second epitaxial layer above the second conductive type column, wherein the bottom surface of the body region is in contact with the second conductive type column, the part, except the body region, in the second epitaxial layer is used as a second column region, and the first column region and the second column region form a first conductive type column;
s4: forming two source regions of a first conductivity type in the body region at intervals, wherein the source regions are spaced from the side walls of the body region by a preset distance, a gate structure is formed on the upper surface of the first conductivity type column, and the side walls of the gate structure extend to the upper part of the source region;
s5: and forming a source electrode on the upper surface of the body region between the two source regions, wherein the side wall of the source electrode extends to the upper side of the source region, and forming a drain electrode on the lower surface of the substrate.
Referring to fig. 3 to 4, the steps S1 and S2 are performed: providing a first conductivity type substrate 1; a plurality of first conductive type first epitaxial layers 2 are formed on the upper surface of the substrate 1, wherein the first conductive type first epitaxial layers 2 are sequentially stacked upwards, a plurality of second conductive type column regions 21 are formed in each first epitaxial layer 2 at preset intervals, the stacked second conductive type column regions 21 form second conductive type columns 22, a part, except for the second conductive type columns 22, of the first epitaxial layers 2 is used as a first column region 23, and a preset interval is formed between two adjacent second conductive type column regions 21 of the second conductive type columns 22.
Specifically, the first conductivity type includes one of an N-type or a P-type, the second conductivity type includes one of an N-type or a P-type, and the first conductivity type is opposite to the second conductivity type. In this embodiment, the first conductivity type is N-type, and the second conductivity type is P-type.
Specifically, the material of the substrate 1 includes silicon, silicon germanium, silicon carbide or other suitable semiconductor materials.
Specifically, the method of forming the first epitaxial layer 2 includes chemical vapor deposition, physical vapor deposition, or a suitable method.
Specifically, as shown in fig. 3, a schematic cross-sectional structure of the substrate 1 is shown, where the doping concentration of the substrate 1 is higher than that of the first epitaxial layer 2.
Specifically, in the case of ensuring the device performance and the ohmic contact between the substrate 1 and the drain electrode (see fig. 8 later), the doping concentration of the substrate 1 may be selected according to practical situations, and is not limited herein.
By way of example, the method of forming the second conductive-type column regions 21 includes ion implantation or other suitable method.
Specifically, the thickness of each first epitaxial layer 2 may be selected according to practical situations, and is not limited herein, while ensuring the device performance.
Specifically, the size of each of the second conductivity type pillar regions 21 may be selected according to the actual situation, while ensuring the device performance, and is not limited.
Specifically, the doping concentration of the first epitaxial layer 2 may be selected according to practical situations, and is not limited herein, while ensuring the device performance.
As an example, the ion implantation dose of the second conductive type column region 21 is 70% to 130% of the ion implantation dose of the first epitaxial layer 2.
Specifically, when the first epitaxial layer 2 is doped by using an ion implantation method, the implantation energy of the ion implantation for forming the second conductive type column region 21 above the underlying first epitaxial layer 2 is smaller than the implantation energy of the ion implantation for forming the first epitaxial layer 2, so that the bottom surface of the second conductive type column region 21 above the underlying first epitaxial layer 2 is higher than the bottom surface of the first epitaxial layer 2 where the second conductive type column region 21 is located, and the effect of spacing two adjacent second conductive type column regions 21 in the second conductive type column 22 is achieved.
As an example, as shown in fig. 4, in order to illustrate a cross-sectional structure after the second conductive type column 22 is formed, a distance between two adjacent second conductive type column regions 21 in the second conductive type column 22 is smaller than an expansion width of a depletion layer, that is, a distance between a bottom surface of the second conductive type column region 21 above the first epitaxial layer 2 and a lower surface of the first epitaxial layer 2 where the second conductive type column region 21 is located is smaller than an expansion width of a depletion layer in the device, so that a voltage connected to the second conductive type column 22 can act on the second conductive type column region 21 located below the second conductive type column region 21 on a top layer through the first epitaxial layer 2 between the two adjacent second conductive type column regions 21, thereby ensuring a breakdown voltage of the device.
Specifically, the method of forming the second conductive type pillar regions 21 includes chemical vapor deposition, physical vapor deposition, or other suitable methods.
As an example, after forming each layer of the first epitaxial layer 2, a step of forming a trench (not shown) in the first epitaxial layer 2 is further included before forming the second conductive type column region 21.
Specifically, the method for forming the trench includes dry etching, wet etching or other suitable methods.
Specifically, the opening size of the trench may be selected according to the actual situation, while ensuring the device performance, which is not limited.
As an example, the second conductivity type pillar regions 21 fill the trenches.
Specifically, the trench in the first epitaxial layer 2 located at the bottom layer penetrates through the first epitaxial layer 2 at the bottom layer, that is, the bottom of the trench exposes the substrate 1, and the bottom surface of the trench in the first epitaxial layer 2 located above the first epitaxial layer 2 at the bottom layer is spaced from the bottom surface of the first epitaxial layer 2 where the trench is located by a preset distance.
Specifically, the distance between the bottom surface of the trench above the first epitaxial layer 2 and the lower surface of the first epitaxial layer 2 where the trench is located is smaller than the spreading width of the depletion layer in the device, so that the voltage connected to the second conductivity type pillars 22 can act on the second conductivity type pillar regions 21 below the second conductivity type pillar regions 21 on the top layer through the barrier of the first epitaxial layer 2 between the two adjacent second conductivity type pillar regions 21, thereby ensuring the breakdown voltage of the device.
Specifically, after the second conductivity-type pillar regions 21 are filled in the trenches, the step of removing the second conductivity-type pillar regions 21 located on the upper surface of the first epitaxial layer 2 is further included.
Specifically, the method for removing the second conductivity type pillar regions 21 on the upper surface of the first epitaxial layer 2 includes chemical mechanical polishing or other suitable method.
As an example, the number of stacked layers of the first epitaxial layer 2 is not less than 2, i.e., at least 2 second conductivity type pillar regions 21 are included in the second conductivity type pillar 22.
Specifically, in the case where the number of stacked layers of the first epitaxial layer 2 is not less than 2, the number of stacked layers of the first epitaxial layer 2 may be selected according to the actual situation, that is, the number of the second conductivity type pillar regions 21 in the second conductivity type pillars 22 may be selected according to the actual situation, which is not limited herein.
Specifically, the distance between two adjacent second conductivity type pillar regions 21 may be selected according to practical situations on the same level, where the level is a plane parallel to the upper surface of the first epitaxial layer 2, without limitation.
Referring to fig. 5 to 10, the steps S3, S4 and S5 are performed: forming a first conductive type second epitaxial layer 3 on the upper surface of the first epitaxial layer 21, forming a second conductive type body region 31 in the second epitaxial layer 3 above the second conductive type column 22, wherein the bottom surface of the body region 31 is in contact with the second conductive type column 22, a part of the second epitaxial layer 3 outside the body region is used as a second column region 32, and the first column region 23 and the second column region 32 form a first conductive type column 33; forming two source regions 34 of the first conductivity type in the body region 31, wherein the source regions 34 are spaced apart from the sidewalls of the body region 31 by a predetermined distance, forming a gate structure 4 on the upper surface of the first conductivity type column 33, and the sidewalls of the gate structure 4 extend to above the source regions 34; a source 5 is formed on the upper surface of the body 31 between the two source regions 34, and the sidewall of the source 5 extends above the source region 34, and a drain 6 is formed on the lower surface of the substrate 1.
Specifically, the method of forming the second epitaxial layer 3 includes chemical vapor deposition, physical vapor deposition, or other suitable methods.
Specifically, the thickness of the second epitaxial layer 3 may be selected according to practical situations, without limitation, while ensuring the device performance.
Specifically, the method for doping the second epitaxial layer 3 includes ion implantation or other suitable methods.
Specifically, the doping concentration of the second epitaxial layer 3 is the same as the doping concentration of the first epitaxial layer 2, i.e. the doping concentrations of the first pillar region 23 and the second pillar region 32 are the same.
Specifically, the method of forming the body region 31 includes ion implantation or other suitable method.
Specifically, forming the body region 31 includes the steps of: forming a patterned first shielding layer (not shown) on the upper surface of the second epitaxial layer 3; the body region 31 is formed based on the patterned first shielding layer.
Specifically, the first shielding layer includes one of a hard mask layer, a photoresist layer and a composite photoresist layer of the hard mask layer, and may also be other suitable shielding material layers. In this embodiment, a hard mask layer is used as the first shielding layer.
Specifically, the doping concentration of the body region 31 is smaller than the doping concentration of the second conductivity type pillar 22.
Specifically, in the case of ensuring the device performance and the doping concentration of the body region 31 is smaller than that of the second conductivity type pillar 22, the doping concentration of the body region 31 may be selected according to the actual situation, which is not limited herein.
Specifically, as shown in fig. 5, the body region 31 is formed with a cross-sectional structure, and the sidewall of the body region 31 protrudes from the sidewall of the second conductivity type pillar 22 along the horizontal direction.
Specifically, the distance by which the side walls of the body regions 31 protrude in the horizontal direction from the side walls of the second conductivity type pillars 22 while ensuring device performance may be selected according to practical circumstances, and is not limited.
Specifically, the size and thickness of the body region 31 may be selected according to practical situations, while ensuring device performance, which is not limited.
Specifically, the step of removing the first shielding layer located on the upper surface of the second epitaxial layer 3 is further included after forming the body region 31.
Specifically, since the method of removing the first shielding layer is a conventional process, it is not limited herein.
Specifically, the method of forming the source regions 34 includes ion implantation or other suitable methods.
Specifically, as shown in fig. 6, to form the source region 34, the forming of the source region 34 includes the following steps: forming a patterned second shielding layer (not shown) on the upper surface of the second epitaxial layer 3; the source region 34 is formed based on the patterned second shielding layer.
Specifically, the second shielding layer includes one of a hard mask layer, a photoresist layer and a composite photoresist layer of the hard mask layer, and may also be other suitable shielding material layers. In this embodiment, a hard mask layer is used as the second shielding layer.
Specifically, the size and depth of the source region 34 may be selected according to the actual situation, while ensuring the device performance, which is not limited herein; the distance between two source regions 34 in the body region 31 may be selected according to practical situations, and is not limited herein, and the depth refers to the distance between the upper surface of the source region 34 and the lower surface of the source region 34.
Specifically, the doping concentration of the source region 34 is higher than the doping concentration of the first conductivity type pillar 33.
Specifically, in the case of ensuring device performance and the doping concentration of the source region 34 is higher than that of the first conductivity type pillar 33, the doping concentration of the source region 34 may be selected according to practical situations, which is not limited herein.
Specifically, as shown in fig. 7, the gate structure 4 includes a gate dielectric layer 41 and a gate 42 sequentially stacked upward, which are schematic cross-sectional structures after the gate structure 4 and the source 5 are formed.
Specifically, the method for forming the gate dielectric layer 41 includes chemical vapor deposition, physical vapor deposition, or other suitable methods.
Specifically, the thickness of the gate dielectric layer 41 may be selected according to practical situations, and is not limited herein, while ensuring the performance of the device.
Specifically, the gate dielectric layer 41 is made of silicon oxide, silicon nitride or other suitable high dielectric materials.
Specifically, the method of forming the gate electrode 42 includes sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition, or other suitable method.
Specifically, the material of the gate 42 includes one of titanium, titanium nitride, silver, gold, copper, aluminum and tungsten, and may be other suitable conductive materials.
Specifically, the method for forming the source electrode 5 includes sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition, or other suitable methods.
Specifically, the material of the source electrode 5 includes one of titanium, titanium nitride, silver, gold, copper, aluminum and tungsten, and may be other suitable conductive materials.
Specifically, the method of forming the drain electrode 6 includes sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition, or other suitable methods.
Specifically, as shown in fig. 8, in order to form the cross-sectional structure of the drain electrode 6, the drain electrode 6 may be made of one of titanium, titanium nitride, silver, gold, copper, aluminum and tungsten, or other suitable conductive materials.
Specifically, since the distance between two adjacent second conductivity-type pillar regions 21 in the second conductivity-type pillar 22 is smaller than the spreading width of the depletion layer in the device, the second conductivity-type pillar regions 21 located on the top of the second conductivity-type pillar 22 affect the remaining second conductivity-type pillar regions 21 in the second conductivity-type pillar 22, so that the spreading of the depletion layer in the device takes a segmented form.
Specifically, due to the segmentation of the depletion layer in the device, the hole extraction speed in the device is delayed, and meanwhile, due to the fact that the expansion of the depletion layer in the device takes the segmented form, the expansion of the depletion layer is slow, the current change speed in the device is restrained, and the current change speed in the device is improved when the device is turned offThe resulting current overshoot problem, in turn, improves the reverse recovery factor of the device.
Specifically, as shown in fig. 9 and fig. 10, the reverse recovery curves of the superjunction MOSFET in fig. 1 and the superjunction MOSFET in the different second conductivity type column intervals of the present invention and the reverse breakdown curves of the superjunction MOSFET in fig. 1 and the superjunction MOSFET in the different second conductivity type column intervals of the present invention are respectively the same, wherein the doping concentrations and the sizes of the substrate, the first conductivity type column, the second conductivity type column, the body region and the source region in the superjunction MOSFET in fig. 1 are the same, the second conductivity type column 22 of the superjunction MOSFET in the present invention is composed of 3 second conductivity type column regions 21 stacked upwards, that is, two faults separated by the first epitaxial layer 2 are arranged in the second conductivity type column 22, and as can be seen from fig. 9, the reverse recovery curves of the superjunction MOSFET in the present invention are improved in terms of the reverse recovery curves of the superjunction MOSFET, that is, the softness factor of the device is improved, compared with the reverse recovery curves of the superjunction MOSFET in terms of the case that the interval between the two second conductivity type column regions 21 is 1 μm and 0.5 μm; as can be seen from fig. 10, when the interval between two adjacent second conductivity type pillar regions 21 is 1 μm, the reverse breakdown voltage of the super junction MOSFET of the present invention slightly decreases (about 20V) relative to the reverse breakdown voltage of the super junction MOSFET, and when the interval between two adjacent second conductivity type pillar regions 21 is 0.5 μm, the reverse breakdown voltage of the super junction MOSFET of the present invention is similar (almost unchanged) to the reverse breakdown voltage of the super junction MOSFET, so that the distance between two adjacent second conductivity type pillar regions 21 in the second conductivity type pillar 22 needs to be reasonably selected according to the actual situation under the condition that the distance between two adjacent second conductivity type pillar regions 21 in the second conductivity type pillar 22 is ensured to be larger than the development width of the depletion layer in the device, so as to achieve the purpose of better improving the device performance.
According to the preparation method of the super-junction MOSFET structure, a plurality of first epitaxial layers 2 which are sequentially stacked upwards are formed by adjusting the process of forming the second conductive type column 22, after each layer of first epitaxial layers 2 is formed, a plurality of second conductive type column regions 21 which are spaced by a preset distance are formed in each layer of first epitaxial layers 2, the second conductive type column regions 21 which are sequentially stacked upwards form the second conductive type column 22, the first epitaxial layers 2 are formed for a plurality of times, so that adjacent two second conductive type column regions 21 in the second conductive type column 22 are arranged at intervals, the distance between the adjacent two second conductive type column regions 21 is smaller than the width of the expansion of a depletion layer of a device, so that the voltage connected with the second conductive type column 22 can penetrate through the barrier of the first epitaxial layers 2 between the adjacent two second conductive type column regions 21, and act on the second conductive type column regions 21 which are positioned below the top layer of the second conductive type column regions 21, the expansion of the second conductive type column regions is guaranteed, the expansion of the depletion layer of the second conductive type column 22 is improved, and the expansion factor of the second conductive type column 22 is reduced, and the expansion factor of the expansion of the second conductive type column is reduced. In addition, the depletion layer formed by the first epitaxial layer 2 and the second conductive type column regions 21 between two adjacent second conductive type column regions 21 delays the extraction speed of holes in the device, so that the extraction speed of holes in the device is reduced, the current in the device is restrained from changing too fast, the problem of current overshoot caused by the too fast current in the device when reverse voltage is applied is solved, and the reverse recovery softness factor of the device is further improved.
Example two
The present embodiment provides a super-junction MOSFET structure, as shown in fig. 8, which is a schematic cross-sectional structure of the super-junction MOSFET structure, and includes a first conductivity type substrate 1, a first conductivity type first epitaxial layer 2, a first conductivity type second epitaxial layer 3, a first conductivity type source region 34, a gate structure 4, a source 5, and a drain 6, wherein multiple layers of the first epitaxial layer 2 are sequentially stacked upwards, the first epitaxial layer 2 is located on the upper surface of the substrate 1, multiple second conductivity type column regions 21 are disposed in each layer of the first epitaxial layer 2 at intervals, the stacked second conductivity type column regions 21 form second conductivity type columns 22, the first epitaxial layer 2 outside the second conductivity type columns 22 is used as a first column region 23, and a preset distance is reserved between two adjacent second conductivity type column regions 21 in the second conductivity type columns 22; the second epitaxial layer 3 is located on the upper surface of the first epitaxial layer 2, a second conductive type body region 31 is arranged in the second epitaxial layer 3 above the second conductive type column 22, the bottom surface of the body region 31 is in contact with the upper surface of the second conductive type column 22, a part of the second epitaxial layer 3 outside the body region 31 is used as a second column region 32, and the first column region 23 and the second column region 32 form a first conductive type column 33; the two source regions 34 are arranged in the body region 31 at intervals, and the side walls of the source regions 34 are spaced from the side walls of the body region 31 by a preset distance; the gate structure 4 is located on the upper surface of the first conductivity type pillar 33, and the sidewall of the gate structure 4 extends to the upper side of the source region 34; the source 5 is located on the upper surface of the body region 31 between the source regions 34, the sidewall of the source 5 extends to the upper surface of the source region 34, and the drain 6 is located on the lower surface of the substrate 1.
Specifically, the thickness and the size of the substrate 1 may be set according to practical situations, which are not limited herein.
Specifically, the thickness of the stacked first epitaxial layer 2 may be set according to the actual situation, that is, the thickness of the first pillar region 23 may be set according to the actual situation, without limitation.
As an example, the ion implantation dose of the second conductive type column region 21 is 70% to 130% of the ion implantation dose of the first epitaxial layer 2.
As an example, a trench is further provided in each of the first epitaxial layers 2, and the second conductivity type pillar regions 21 fill the trench.
Specifically, the trench in the first epitaxial layer 2 at the bottom layer penetrates through the first epitaxial layer 2 at the bottom layer, that is, the bottom of the trench in the first epitaxial layer 2 at the bottom layer exposes the substrate 1.
Specifically, the trenches in the plurality of first epitaxial layers 2 above the first epitaxial layer 2 at the bottom layer do not penetrate through the first epitaxial layer 2, that is, the bottom surfaces of the trenches and the bottom surfaces of the first epitaxial layers 2 where the trenches are located are spaced by a preset distance, so that the spacing between two adjacent second conductivity type column regions 21 in the second conductivity type columns 22 is realized.
As an example, the spacing distance between two adjacent second conductive type column regions 21 in the second conductive type column 22 is smaller than the spreading width of the depletion layer, so that the depletion layer of the second conductive type column region 22 located at the top of the second conductive type column 22 extends to the second conductive type column region 21 located below under the reverse voltage, ensuring that the reverse breakdown voltage of the device can act on the second conductive type column region 21 located below the second conductive type column region 21 located at the top layer, and consequently, the reverse breakdown voltage of the device is not changed greatly, and the reverse breakdown voltage of the device is ensured.
Specifically, since the second conductive type column 22 is disposed between two adjacent second conductive type column regions 21 at intervals, the depletion layer in the device is expanded in sections, the expansion of the depletion layer is slowed down, and meanwhile, the extraction speed of holes in the device is slowed down by using the blocking of the depletion layer between two adjacent second conductive type column regions 21, so that the hole extraction speed in the device is slowed down, the current change speed in the device is inhibited, and the reverse recovery softness factor of the device is improved.
Specifically, the minority carrier lifetime control process is applied to the super junction MOSFET structure with the second conductive type column regions arranged at intervals, so that minority carrier lifetime in the device is increased, and the reverse recovery softness factor of the device can be further improved.
Specifically, the sidewalls of the body regions 31 protrude from the sidewalls of the second conductivity type pillars 22 in the horizontal direction.
Specifically, the gate structure 4 includes a gate dielectric layer 41 on the upper surface of the first conductive type pillar 33 and a gate electrode 42 on the upper surface of the gate dielectric layer 41.
In the super-junction MOSFET structure of this embodiment, the second conductivity type pillars 22 in the device are divided into a plurality of second conductivity type pillar regions 21 disposed at intervals, and the interval distance between two adjacent second conductivity type pillar regions 21 in the second conductivity type pillars 22 is smaller than the broadening of the depletion layer in the device, so that the reverse breakdown voltage of the device is ensured, and the reverse recovery softness factor of the device is improved.
In summary, the super junction MOSFET structure and the method for fabricating the same of the present invention form a plurality of first epitaxial layers stacked in sequence upward on a substrate by adjusting a process for forming the second conductive type pillars, and form a plurality of second conductive type pillar regions spaced apart by a predetermined distance in the first epitaxial layers after each first epitaxial layer is formed, the second conductive type pillar regions stacked in sequence upward form the second conductive type pillars, so that a plurality of second conductive type pillar regions spaced apart by a predetermined distance are formed in the second conductive type pillars, and a distance between two adjacent second conductive type pillar regions is smaller than a depletion layer development width of a device, the voltage of the second conductive type column region electrically connected with the top layer can penetrate through the blocking of the first epitaxial layer between the two adjacent second conductive type column regions and acts on the second conductive type column region at the lower layer of the second conductive type column region on the top layer, so that the breakdown voltage of the device is ensured, and due to the arrangement of the second conductive type column regions at intervals, the expansion of a depletion layer in the device is segmented, the expansion of the depletion layer in the device is slowed down, the depletion layer between the two adjacent second conductive type column regions is formed, the extraction speed of holes in the device is delayed, the hole extraction speed of the device is slowed down, the current change speed in the device is restrained, the current overshoot problem caused by the too fast current change in the device is solved, and the reverse recovery softness factor of the device is improved. In addition, in the super junction MOSFET structure, the reverse recovery softness factor of the device can be further improved by utilizing a plurality of second conductivity type pillar structures arranged at intervals to form the second conductivity type pillar structure and combining with a minority carrier lifetime control process. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.
Claims (11)
1. The preparation method of the super junction MOSFET structure is characterized by comprising the following steps of:
providing a first conductive type substrate;
forming a plurality of layers of first conductive type first epitaxial layers which are sequentially stacked upwards on the upper surface of the substrate, wherein a plurality of second conductive type column regions with preset intervals are formed in each layer of first epitaxial layers, the stacked second conductive type column regions form second conductive type columns, the part, except the second conductive type columns, in the first epitaxial layers is used as a first column region, and the preset intervals are formed between two adjacent second conductive type column regions in the second conductive type columns;
forming a first conductive type second epitaxial layer on the upper surface of the first epitaxial layer, forming a second conductive type body region in the second epitaxial layer above the second conductive type column, wherein the bottom surface of the body region is in contact with the second conductive type column, the part, except the body region, in the second epitaxial layer is used as a second column region, and the first column region and the second column region form a first conductive type column;
forming two source regions of a first conductivity type in the body region at intervals, wherein the source regions are spaced from the side walls of the body region by a preset distance, a gate structure is formed on the upper surface of the first conductivity type column, and the side walls of the gate structure extend to the upper part of the source region;
and forming a source electrode on the upper surface of the body region between the two source regions, wherein the side wall of the source electrode extends to the upper side of the source region, and forming a drain electrode on the lower surface of the substrate.
2. The method for manufacturing a super junction MOSFET structure according to claim 1, wherein: the method of forming the second conductivity type pillar region includes ion implantation.
3. The method for manufacturing the super junction MOSFET structure according to claim 2, wherein: the ion implantation dosage of the second conductive type column region is 70% -130% of the ion implantation dosage of the first epitaxial layer.
4. The method for manufacturing a super junction MOSFET structure according to claim 1, wherein: the spacing distance between two adjacent second conductive type column regions in the second conductive type column is smaller than the expansion width of the depletion layer.
5. The method for manufacturing a super junction MOSFET structure according to claim 1, wherein: the method for forming the second conductive type column region comprises chemical vapor deposition and physical vapor deposition.
6. The method for fabricating a super junction MOSFET structure according to claim 5, wherein: after forming each layer of the first epitaxial layer, the step of forming a trench in the first epitaxial layer is further included before forming the second conductivity type pillar region.
7. The method for fabricating a super junction MOSFET structure according to claim 6, wherein: the second conductivity type pillar region fills the trench.
8. The method for manufacturing a super junction MOSFET structure according to claim 1, wherein: the number of stacked layers of the first epitaxial layer is not less than 2.
9. A superjunction MOSFET structure, comprising:
a first conductivity type substrate;
a plurality of layers of first conductive type first epitaxial layers which are sequentially stacked upwards and are positioned on the upper surface of the substrate, a plurality of second conductive type column regions which are arranged at intervals are arranged in each layer of first epitaxial layers, the stacked second conductive type column regions form second conductive type columns, the first epitaxial layers outside the second conductive type columns are used as first column regions, and a preset distance is reserved between two adjacent second conductive type column regions in the second conductive type columns;
a second epitaxial layer of a first conductivity type, which is positioned on the upper surface of the first epitaxial layer, wherein a second conductivity type body region is arranged in the second epitaxial layer above the second conductivity type column, the bottom surface of the body region is contacted with the upper surface of the second conductivity type column, the part of the second epitaxial layer outside the body region is used as a second column region, and the first column region and the second column region form a first conductivity type column;
two source regions of the first conductivity type arranged at intervals are positioned in the body region, and the side walls of the source regions are spaced from the side walls of the body region by a preset distance;
a gate structure on the upper surface of the first conductivity type pillar, the sidewall of the gate structure extending above the source region;
the source electrode is positioned on the upper surface of the body region between the source regions, the side wall of the source electrode extends to the upper surface of the source region, and the drain electrode is positioned on the lower surface of the substrate.
10. The superjunction MOSFET structure of claim 9, wherein: and each layer of the first epitaxial layer is also provided with a groove, and the second conductive type column region fills the groove.
11. The superjunction MOSFET structure of claim 9, wherein: the spacing distance between two adjacent second conductive type column regions in the second conductive type column is smaller than the expansion width of the depletion layer.
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