CN116978925A - Super-junction MOSFET and manufacturing method thereof - Google Patents
Super-junction MOSFET and manufacturing method thereof Download PDFInfo
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- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
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Abstract
The invention provides a super-junction MOSFET and a manufacturing method thereof, wherein the super-junction MOSFET comprises a substrate, a buffer area, a first conductive type column, a second conductive type column, a body area, a source area, a grid structure, a groove, a source electrode and a drain electrode, wherein the buffer area is stacked above the substrate; the first conductive type column and the second conductive type column are parallelly adjacent to the upper surface of the buffer zone, and the body zone is stacked on the second conductive type column; the source region is adjacent to the body contact region and is positioned on the upper surface layer of the body region; the grid structure is positioned on the upper surface of the first conductive type column; the trench penetrates the source region and extends into at least the body region, the source electrode covers the upper surface of the device, the source electrode, the body region and the source region are respectively in Schottky contact and ohmic contact, and the drain electrode covers the bottom surface of the substrate. The invention increases the reverse recovery softness factor of the device by enabling the source electrode and the body region to form schottky contact so as to limit the quantity of unbalanced carriers injected into the source electrode in the junction region in the body region and the second conductive type column when the device is reversely conducted.
Description
Technical Field
The invention belongs to the technical field of semiconductors, and relates to a super junction MOSFET and a manufacturing method thereof.
Background
Because the super-junction MOSFET is provided with the N-type column region and the P-type column region which are mutually compensated, the influence of the ionization donor charge of the N-type column region on the longitudinal electric field is reduced. Therefore, the doping concentration of the N-type column region can be greatly increased to reduce the on-resistance of the device without sacrificing the breakdown voltage. In general, the P-type column region needs to be connected to the source electrode, otherwise, holes in the P-type column region cannot be complemented in the switching process, and thus problems such as an increase in dynamic resistance are caused. However, when the superjunction MOSFET is turned on in the reverse direction, the P-type column region injects a large amount of unbalanced carriers into the N-type column region, which significantly increases the reverse recovery charge, resulting in an increase in the switching loss of the system. In the reverse recovery process of the super-junction MOSFET, unbalanced carriers at the bottom of the chip are extracted in the initial stage of reverse recovery due to the existence of the P-type column region, so that the softness factor of the reverse recovery of the device is reduced. The reduction of the softness factor of the reverse recovery causes a large dI/dt, which in turn causes voltage overshoot and strong oscillations of the parasitic RLC loop, and more seriously causes the burning out of the superjunction MOSFET device.
Currently, the reverse recovery softness factor is increased by decreasing the unbalanced carrier concentration in the superjunction at reverse conduction to reduce the reverse recovery charge. Electrons and heavy metal irradiation are generally adopted to directly reduce the service life of unbalanced carriers, so that the concentration of the unbalanced carriers in the super-junction MOSFET body is reduced. However, electron and heavy metal irradiation are adopted, so that the service life of carriers is reduced, the leakage current of the device is increased, the electron mobility of the surface of the chip is reduced due to irradiation, the area of the chip of the device is increased, and the manufacturing and processing cost and the time cost of the chip are increased due to an irradiation process. In addition, the unbalanced carrier concentration in the super junction MOSFET is reduced by reducing the injection efficiency of the PN junction, i.e., integrating an N-type schottky diode on the chip surface, integrating a P-type schottky diode on the chip back surface, or integrating a channel diode in the channel. However, the integration of an N-type schottky diode on the surface of the chip or a P-type schottky diode on the back of the chip increases the leakage current by more than 1 order of magnitude, and the process complexity is also increased. Integrating the channel diode sacrifices a portion of the electron channel, thereby increasing the on-resistance and increasing the difficulty of the device manufacturing process.
Therefore, there is a need for a superjunction MOSFET that can greatly optimize the reverse recovery characteristics without increasing the on-resistance, process difficulty, and leakage current of the device.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a super-junction MOSFET and a method for manufacturing the same, which are used for solving the problems of increasing on-resistance, process difficulty, leakage current and cost when the reverse recovery characteristic of the super-junction MOSFET is optimized in the prior art.
To achieve the above and other related objects, the present invention provides a superjunction MOSFET including:
a first conductivity type substrate;
a first conductive type buffer region stacked on an upper surface of the substrate;
a first conductive type column disposed on an upper surface of the buffer region and extending in a direction away from the substrate, the first conductive type column including a first column region and a second column region stacked on the first column region;
the second conductive type column is arranged on the upper surface of the buffer area and positioned on two sides of the first column area, the side wall of the second conductive type column is adjacent to the side wall of the first column area, and the upper surface of the second conductive type column is flush with the upper surface of the first column area;
a second conductive type body region stacked on an upper surface of the second conductive type column, wherein the upper surface of the body region is flush with the upper surface of the second column region, and a side wall of the body region is adjacent to a side wall of the second column region;
a source region of a first conductivity type located on an upper surface of the body region, the source region being spaced a predetermined distance from the first conductivity type column;
the grid electrode structure is positioned on the upper surfaces of the body region and the second column region, and two ends of the grid electrode structure extend to the upper part of the source region;
a plurality of spaced apart trenches extending through the source region and at least into the body region;
the source electrode covers the exposed surfaces of the grid structure, the source region and the body region and fills the groove, the drain electrode covers the bottom surface of the substrate, the contact type of the source electrode and the source region is ohmic contact, and the contact type of the body region and the source electrode is Schottky contact.
Optionally, the doping concentration of the substrate is lower than the doping concentration of the buffer region, and the doping concentration of the buffer region is lower than the doping concentration of the first conductive type column.
Optionally, a barrier height of the schottky contact between the body region and the source is not higher than 0.7eV.
Optionally, the trench penetrates the source region and extends into the body region, and the bottom of the trench is spaced from the bottom surface of the body region by a preset distance.
Optionally, the superjunction MOSFET further includes at least one first conductivity type doped region in the body region or the second conductivity type pillar.
Optionally, the first conductivity type doped region is located below the trench, a reverse breakdown point of the superjunction MOSFET is located at the first conductivity type doped region, and a distance of the first conductivity type doped region from a bottom of the trench is less than 2 μm.
Optionally, the trench penetrates the body region and a bottom surface of the trench is flush with a bottom surface of the body region or extends into the second conductivity type pillar.
Optionally, the superjunction MOSFET further includes at least one first conductivity type doped region in the second conductivity type pillar.
Optionally, the first conductivity type doped region is located below the trench, a reverse breakdown point of the superjunction MOSFET is located at the first conductivity type doped region, and a distance of the first conductivity type doped region from a bottom of the trench is less than 2 μm.
Optionally, the gate structure includes a gate dielectric layer and a gate, and the gate dielectric layer wraps the gate.
The invention also provides a manufacturing method of the super junction MOSFET, which comprises the following steps:
providing a first conductive type substrate, and forming a first conductive type buffer area on the upper surface of the substrate;
forming a first conductive type first column region and second conductive type columns positioned on two sides of the first column region on the upper surface of the buffer region, wherein the side walls of the second conductive type columns are adjacent to the side walls of the first column region, and the upper surface of the first column region is flush with the upper surface of the second conductive type columns;
forming a first conductive type second column region on the upper surface of the first column region to form a first conductive type column, forming a second conductive type body region which is positioned on the upper surface of the second conductive type column and is adjacent to the side wall of the second column region on two sides of the second column region, wherein the upper surface of the body region is flush with the upper surface of the second column region;
forming a first conductive type source region in an upper surface layer of the body region, wherein the source region is spaced from the first conductive type column by a preset distance;
forming a grid structure on the upper surfaces of the first conductive type column and the body region, wherein two ends of the grid extend to the upper part of the source region;
forming a groove penetrating the source region and extending to at least the body region from the bottom in the source region, forming a source electrode covering the gate structure, the source region and the exposed surface of the body region and filling the groove, and forming a drain electrode covering the bottom surface of the substrate, wherein the contact type of the source electrode and the source region is ohmic contact, and the contact type of the source electrode and the body region is Schottky contact.
Optionally, the method further includes forming a first conductivity type doped region in the body region or the second conductivity type pillar under the trench.
Optionally, the first conductivity type doped region is located below the source electrode and is in electrical contact with the source electrode, and after the trench is formed, ion implantation is performed on the bottom of the trench to form the first conductivity type doped region before the source electrode is formed.
As described above, in the super-junction MOSFET and the method for manufacturing the same, schottky contact and ohmic contact are formed between the source electrode and the body region and between the source electrode and the source region respectively, and the source electrode penetrates through the source region and extends into at least the body region, so that unbalanced carriers stored in a junction region between the second conductive type column and the first conductive type column and between the second conductive type column and the buffer region are prevented from being injected into the source electrode when the device is turned on in a reverse direction by using the schottky barrier layer formed between the source electrode and the body region, the number of unbalanced carriers injected into the device is reduced, the reverse recovery softness factor of the device is increased, and the leakage current of the device is not increased; at least one first conductive type doped region is arranged in the second reverse conductive type column or the body region, the first conductive type doped region and the body region or the second conductive type column are mutually compensated, so that the charge storage amount of a PN junction region between the body region or the second conductive type column and the first conductive type column is reduced, and then the reverse recovery softness factor of the device is further increased; the first conductive type doped region is positioned below the source electrode extending to the body region or the second conductive type column, the doping concentration of the first conductive type doped region and the distance between the first conductive type doped region and the source electrode are regulated so that a stronger electric field is formed between the first conductive type doped region and the source electrode, and the surface of one surface of the first conductive type doped region, which is far away from the source electrode, forms charge aggregation, so that the reverse breakdown point of the device is positioned at the first conductive type doped region, the risk of starting a parasitic triode in the device is reduced, and the avalanche tolerance of the device is increased. In addition, the method for forming the first conductive type doped region in the second conductive type body region and forming the Schottky contact between the body region and the source electrode so as to increase the reverse recovery softness factor of the device can be applied to IGBT devices, and has high industrial utilization value.
Drawings
Fig. 1 is a schematic cross-sectional view showing a structure of a super junction MOSFET of the present invention.
Fig. 2 is a schematic cross-sectional view showing another structure of the super junction MOSFET of the present invention.
Fig. 3 is a schematic cross-sectional view showing a structure in which the bottom of the trench is located in the body region and the body region is provided with the first conductivity type doped region in the super junction MOSFET of the present invention.
Fig. 4 is a schematic cross-sectional view showing a structure in which the bottom of the trench is located in the second conductivity type pillar and the first conductivity type doped region is provided in the second conductivity type pillar in the super junction MOSFET of the present invention.
Fig. 5 is a schematic cross-sectional view of the super-junction MOSFET of the present invention, in which the bottom of the trench is located in the body region and the first conductivity type doped region is located at the bottom of the trench.
Fig. 6 is a schematic cross-sectional view showing a structure in which the bottom of the trench is located in the second conductivity type pillar and the first conductivity type doped region is located at the bottom of the trench in the super junction MOSFET of the present invention.
Fig. 7 is a process flow diagram of a method of fabricating a superjunction MOSFET of the present invention.
Description of element reference numerals
1. Substrate and method for manufacturing the same
2. Buffer zone
3. First conductivity type column
31. First column region
32. Second column zone
4. Second conductivity type column
41. Doped region of first conductivity type
5. Body region
6. Source region
7. Gate structure
71. Gate dielectric layer
72. Grid electrode
8. Groove(s)
9. Source electrode
10. Drain electrode
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
Please refer to fig. 1 to 7. It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
Example 1
The present embodiment provides a super-junction MOSFET, as shown in fig. 1 and 2, which are a schematic cross-sectional structure of one structure of the super-junction MOSFET and a schematic cross-sectional structure of another structure of the super-junction MOSFET, respectively, including a first conductive type substrate 1, a first conductive type buffer region 2, a first conductive type column 3, a second conductive type column 4, a second conductive type body region 5, a first conductive type source region 6, a gate structure 7, a trench 8, a source 9 and a drain 10, wherein the buffer region 2 is stacked on the upper surface of the substrate 1; the first conductive type column 3 is disposed on the upper surface of the buffer region 2 and extends in a direction away from the substrate 1, and the first conductive type column 3 includes a first column region 31 and a second column region 32 stacked on the first column region 31; the second conductive type pillars 4 are disposed on the upper surface of the buffer region 21 and located on both sides of the first pillar region 31, the sidewalls of the second conductive type pillars 4 are adjacent to the sidewalls of the first pillar region 31, and the upper surface of the second conductive type pillars 4 is flush with the upper surface of the first pillar region 31; the body region 5 is stacked on the upper surface of the second conductive type column 4, and the upper surface of the body region 5 is flush with the upper surface of the second column region 32, and the side wall of the body region 5 is adjacent to the side wall of the second column region 32; the source region 6 is located on the upper surface layer of the body region 5, and the source region 6 is spaced from the first conductive type column 3 by a preset distance; the gate structure 7 is located on the upper surfaces of the body region 5 and the second column region 6, and two ends of the gate structure 7 extend to the upper side of the source region 6; a plurality of trenches 8 are spaced apart and extend through the source region 6 and into the body region 5; the source electrode 9 covers the exposed surfaces of the gate structure 7, the source region 6 and the body region 5 and fills the trench 8, the drain electrode 10 covers the bottom surface of the substrate 1, the contact type of the source electrode 9 and the source region 6 is ohmic contact, and the contact type of the body region 5 and the source electrode 9 is schottky contact.
Specifically, the first conductivity type includes one of an N-type or a P-type, the second conductivity type includes one of an N-type or a P-type, and the first conductivity type is opposite to the second conductivity type.
Specifically, the material of the substrate 1 includes silicon or other suitable semiconductor materials. In this embodiment, the substrate 1 is N-type silicon.
Specifically, the thickness of the substrate 1 may be set according to practical situations, and is not limited herein.
As an example, the doping concentration of the substrate 1 is higher than that of the buffer region 2 to raise the withstand voltage value of the device, and the doping concentration of the first conductivity type pillar 3 is higher than that of the buffer region 2 to lower the on-resistance of the device.
Specifically, the thickness of the buffer area 2 may be set according to practical situations, which is not limited herein; the thickness of the first pillar region 31 may be set according to practical situations, and is not limited herein.
Specifically, the thickness of the second column region 32 may be set according to practical situations, which is not limited herein.
Specifically, the size of the body 5 may be set according to practical situations, which is not limited herein.
Specifically, the source region 6 is heavily doped, so the contact type between the source 9 and the source region 6 is ohmic contact, and the higher the doping concentration of the source region 6 is, the smaller the contact resistance between the source region 6 and the source 9 is.
As an example, the barrier height of the schottky contact between the body region 5 and the source 9 is not higher than 0.7eV to prevent affecting the width of the conduction channel in the body region 5 and thus affecting the conduction of the device.
Specifically, the body region 5 is lightly doped so that schottky contact is formed between the body region 5 and the source electrode 9, and the lower the doping concentration of the body region 5 is, the higher the barrier height between the body region 5 and the source electrode 9 is, and the barrier height between the body region 5 and the source electrode 9 can be regulated by regulating the doping concentration of the body region 5.
Specifically, when the super-junction MOSFET is turned on reversely, the schottky contact between the body region 5 and the source electrode 9 is biased reversely, so as to limit the injection of unbalanced carriers into the source electrode 9 of the PN junction region between the second conductive type pillar 4 and the first pillar region 31 and the buffer region 2, so that the number of unbalanced carriers injected into the source electrode is reduced, and the reverse recovery softness factor of the device is increased; when the superjunction MOSFET is turned on in the forward direction, the schottky contact between the source electrode 9 and the body region 5 is biased in the forward direction, the contact resistance is small, the increase of the leakage current (current generated between the gate electrode and the source electrode) of the device is not caused, and the source electrode 9 forms a conduction loop through the source region 6, the body region 5, the first conductivity type pillar 3, the buffer region 2, the substrate 1 and the drain electrode 10, and the conduction resistance of the device is not affected because the contact between the source region 6 and the source electrode 9 is ohmic contact.
Specifically, the side walls of the trenches 8 are spaced apart from the side walls of the first conductivity type pillars 3 by a predetermined distance.
As an example, the trench 8 penetrates the source region 9 and extends into the body region 5, and the bottom of the trench 8 is spaced apart from the bottom surface of the body region 5 by a predetermined distance.
In particular, the distance between the bottom of the trench 8 and the bottom surface of the body region 5 may be set according to practical situations, which is not limited herein.
As an example, as shown in fig. 3, a schematic cross-sectional structure of the trench 8 of the superjunction MOSFET is shown, in which the bottom of the trench is located in the body region 5 and a first conductivity type doped region is provided in the body region 5, and the superjunction MOSFET further includes at least one first conductivity type doped region 41 located in the body region 5 or the second conductivity type pillar 4.
Specifically, the first conductive type doped region 41 is located in the body region 5, the body region 5 and the first conductive type doped region 41 compensate each other, so that the charge storage amount of the PN junction region between the body region 5 and the second column region 32 is reduced, the reverse recovery softness factor of the device is further reduced, and the body region 5 and the first conductive type doped region 41 compensate each other, so that the resistance value of the body region 5 is improved, and the reverse breakdown voltage resistance value of the device is further improved.
As an example, the first conductivity-type doped region 41 is located below the trench 8, the reverse breakdown point of the superjunction MOSFET is located at the first conductivity-type doped region 41, and the first conductivity-type doped region 41 is less than 2 μm from the bottom of the trench 8.
Specifically, the first conductivity type doped region 41 is located below the trench 8 and in the body region 5 or the second conductivity type column 4, and the distance between the first conductivity type doped region 41 and the bottom of the trench 8, the doping concentration of the first conductivity type doped region 41, and the doping concentration of the body region 5 or the second conductivity type column 4 are regulated, so that a stronger electric field is formed between the first conductivity type doped region 41 and the source electrode 9 when the device is connected with a reverse voltage, and charge accumulation occurs at a PN junction of one side of the first conductivity type doped region 41 away from the source electrode 9, so that a reverse breakdown point of the device is controlled to be located at the first conductivity type doped region 41, thereby reducing the risk of parasitic transistor opening in the device and increasing avalanche resistance of the device.
As an example, the trench 8 penetrates the body region 5 and the bottom surface of the trench 8 is flush with the bottom surface of the body region 5 or extends into the second conductivity type pillar 4.
Specifically, the trench 8 is flush with the bottom surface of the body region 5 or extends into the second conductivity type pillar 4, and a schottky contact is also formed between the source electrode 9 and the second conductivity type pillar 4 to reduce the reverse recovery softness factor of the device.
As an example, as shown in fig. 4, a schematic cross-sectional structure of the super-junction MOSFET is shown when the trench bottom surface of the super-junction MOSFET is flush with the body region bottom surface and the first conductivity type doped region 41 is disposed in the second conductivity type pillar, and the super-junction MOSFET further includes at least one first conductivity type doped region 41 located in the second conductivity type pillar 4.
Specifically, the second conductive type column 4 and the first conductive type doped region 41 compensate each other, so as to reduce the charge storage amount of the PN junction region between the second conductive type column 4 and the first conductive type column 3 and the buffer region 2, further reduce the reverse recovery softness factor of the device, and the second conductive type column 4 and the first conductive type doped region 41 compensate each other, so that the resistance value of the second conductive type column 4 is improved, and further the reverse breakdown voltage resistance value of the device is improved.
As an example, the first conductivity-type doped region 41 is located below the trench 8, the reverse breakdown point of the superjunction MOSFET is located at the first conductivity-type doped region 41, and the first conductivity-type doped region 41 is less than 2 μm from the bottom of the trench 8.
Specifically, the first conductive type doped region 41 is located below the trench 8 and in the second conductive type column 4, the doping concentration of the first conductive type doped region 41, the doping concentration of the second conductive type column 4 between the source 9 and the first conductive type doped region 41, and the distance between the first conductive type doped region 41 and the bottom of the trench 8 are regulated, so that a stronger electric field is formed between the first conductive type doped region 41 and the source 9 when the device is connected with a reverse voltage, and a charge accumulation occurs at a PN junction of one side of the first conductive type doped region 41 away from the source 9, so that a reverse breakdown point of the device is controlled to be located at the first conductive type doped region 41, thereby reducing the risk of parasitic transistor opening in the device and increasing avalanche resistance of the device.
As an example, the gate structure 7 includes a gate dielectric layer 71 and a gate 72, and the gate dielectric layer 71 wraps the gate 72.
Specifically, two ends of the gate 72 are located above the source region 6 to control opening and closing of a conductive channel in the body region 5 between the source region 6 and the second column region 32.
In particular, the method of forming a schottky contact between the body region and the source region in the second conductivity type body region to increase the device reverse recovery softness factor can be applied to an IGBT device.
Specifically, as shown in fig. 5 and 6, when the bottom of the trench 8 is located in the body region 5 and the first conductivity type doped region 41 is located at the bottom of the trench 8, and when the bottom of the trench 8 is located in the second conductivity type column 4 and the first conductivity type doped region 41 is located at the bottom of the trench 8, the first conductivity type doped region 41 may be formed after the trench 8 is formed, so as to reduce the difficulty of the manufacturing process.
The super junction MOSFET of this embodiment, by setting the contact type of the body region 5 and the source region 9 to schottky contact and the contact type of the source region 6 and the source region 9 to ohmic contact, and making the source region 9 penetrate the source region 6 and extend at least into the body region 5, uses the schottky barrier at the contact between the source region 9 and the body region 5 to limit the injection of unbalanced carriers into the source region 9 in the junction region between the body region 5 and the second conductivity type pillar 4 and the first conductivity type pillar 3 and the buffer region 2, thereby increasing the reverse recovery softness factor of the device without increasing the leakage current of the device; at least one first conductivity type doped region 41 is arranged in the body region 5 or the second conductivity type column 4, and the first conductivity type doped region 41 and the body region 5 or the second conductivity type column 4 are mutually compensated to reduce the charge storage amount of the PN junction regions between the second conductivity type column 4 and the body region 5 and the first conductivity type column 3 and the buffer region 2, so that the reverse recovery softness factor of the device is increased; in addition, when the first conductivity type doped region 41 is located below the bottom of the trench 8, by adjusting the doping concentration of the first conductivity type doped region 41, the distance between the first conductivity type doped region 41 and the source electrode 9, and the doping concentration of the body region 5 between the first conductivity type doped region 41 and the source electrode 9, a stronger electric field is formed between the source electrode 9 and the first conductivity type doped region, and the side of the first conductivity type doped region 41 away from the source electrode 9 generates charge accumulation, so that the reverse breakdown point of the device is located at the first conductivity type doped region 41, thereby reducing the risk of parasitic transistor turn-on in the device, increasing the avalanche resistance of the device, and the method of forming the first conductivity type doped region in the second conductivity type body region and forming schottky contact between the body region and the source electrode can be applied to an IGBT device to increase the reverse recovery softness factor of the device.
Example two
The embodiment provides a method for manufacturing a super junction MOSFET, as shown in fig. 7, which is a process flow chart of the method for manufacturing the super junction MOSFET, and includes the following steps:
s1: providing a first conductive type substrate, and forming a first conductive type buffer area on the upper surface of the substrate;
s2: forming a first conductive type first column region and second conductive type columns positioned on two sides of the first column region on the upper surface of the buffer region, wherein the side walls of the second conductive type columns are adjacent to the side walls of the first column region, and the upper surface of the first column region is flush with the upper surface of the second conductive type columns;
s3: forming a first conductive type second column region on the upper surface of the first column region to form a first conductive type column, forming a second conductive type body region which is positioned on the upper surface of the second conductive type column and is adjacent to the side wall of the second column region on two sides of the second column region, wherein the upper surface of the body region is flush with the upper surface of the second column region;
s4: forming a first conductive type source region in an upper surface layer of the body region, wherein the source region is spaced from the first conductive type column by a preset distance;
s5: forming a grid structure on the upper surfaces of the first conductive type column and the body region, wherein two ends of the grid extend to the upper part of the source region;
s6: forming a groove penetrating the source region and extending to the body region from the bottom of the groove in the source region, forming a source electrode covering the gate structure, the source region and the exposed surface of the body region and filling the groove, and forming a drain electrode covering the bottom surface of the substrate, wherein the contact type of the source electrode and the source region is ohmic contact, and the contact type of the source electrode and the body region is Schottky contact.
The step S1 is executed: a first conductivity type substrate is provided, and a first conductivity type buffer region is formed on the upper surface of the substrate.
Specifically, the method of forming the buffer region includes chemical vapor deposition or other suitable methods.
Executing the step S2 and the step S3: forming a first conductive type first column region and second conductive type columns positioned on two sides of the first column region on the upper surface of the buffer region, wherein the side walls of the second conductive type columns are adjacent to the side walls of the first column region, and the upper surface of the first column region and the upper surface of the second conductive type columns; forming a first conductive type second column region on the upper surface of the first column region to form a first conductive type column, forming second conductive type body regions which are positioned on the upper surface of the second conductive type column and are adjacent to the side walls of the second column region on two sides of the second column region, wherein the upper surface of the body regions is flush with the upper surface of the second column region.
Specifically, the method for forming the second conductive type column and the first column region includes forming a plurality of layers of first column region semiconductor layers sequentially stacked upward on the upper surface of the buffer region, and forming the first column region and the second conductive type column in a designated region of the semiconductor layer after each layer of the first column region semiconductor layers is formed until the thicknesses of the first column region and the second conductive type column reach a preset thickness.
Specifically, the method for forming the first pillar region semiconductor layer includes chemical vapor deposition or other suitable methods.
Specifically, the thickness of the first pillar semiconductor layer may be selected according to practical situations, which is not limited herein.
Specifically, the method of forming the second conductivity type pillars includes ion implantation or other suitable method; the method of forming the first column region includes ion implantation or other suitable method.
Specifically, after the first pillar region and the second conductive type pillar are formed, a first semiconductor layer is formed on the upper surface of the first pillar region semiconductor layer, the second pillar region is formed in the first semiconductor layer above the first pillar region to obtain the first conductive type pillar, and the body region is formed in the first semiconductor layer above the second conductive type pillar.
Specifically, the method of forming the first semiconductor layer includes chemical vapor deposition or other suitable methods.
Specifically, the thickness of the first semiconductor layer may be selected according to practical situations, which is not limited herein.
Specifically, the method of forming the second column region includes ion implantation or other suitable method; methods of forming the body region include ion implantation or other suitable methods.
Executing the step S4 and the step S5: forming a first conductive type source region in an upper surface layer of the body region, wherein the source region is spaced from the first conductive type column by a preset distance; and forming a gate structure on the first conductive type column and the upper surface of the body region, wherein two ends of the gate extend to the upper part of the source region.
Specifically, the method of forming the source region includes ion implantation or other suitable method; the size and doping concentration of the source region may be selected according to practical situations, and are not limited herein.
Specifically, after the source region is formed in the body region, a first isolation layer and a conductive material layer are sequentially formed on the upper surface of the first semiconductor layer, the first isolation layer and the conductive material layer are etched to obtain a gate isolation layer and a gate electrode, and then a second isolation layer is formed on the exposed surfaces of the gate electrode and the gate isolation layer to obtain a gate dielectric layer comprising the gate isolation layer and the second isolation layer and a gate structure comprising the gate dielectric layer and the gate electrode.
Specifically, the thickness of the first isolation layer may be selected according to practical situations, which is not limited herein; the thickness of the conductive material layer formed may be selected according to practical situations, and is not limited herein.
Specifically, the method for forming the first isolation layer includes a thermal oxidation method, a chemical vapor deposition method, or other suitable methods.
Specifically, the material of the first isolation layer includes silicon dioxide or other suitable dielectric materials.
Specifically, the method of forming the conductive material layer includes chemical vapor deposition, physical vapor deposition, or other suitable methods.
Specifically, the material of the conductive material layer includes polysilicon or other suitable conductive materials.
Specifically, the method of forming the second isolation layer includes a thermal oxidation method, a chemical vapor deposition method, or other suitable methods.
Specifically, the material of the second isolation layer includes silicon dioxide, silicon nitride or other suitable materials. In this embodiment, the materials of the first isolation layer and the second isolation layer are silicon dioxide.
Specifically, the method for forming the gate isolation layer includes one of dry etching and wet etching, and may be other suitable methods.
Specifically, the method for forming the gate electrode includes one of dry etching and wet etching, and may be other suitable methods.
Specifically, the method for forming the trench includes one of dry etching and wet etching, and may be other suitable methods.
As an example, the method for manufacturing a super junction MOSFET further includes a step of forming a first conductivity type doped region in the body region or the second conductivity type pillar.
Specifically, when the first conductivity type doped region is formed in the second conductivity type pillar, forming the first conductivity type doped region at a preset position of the first pillar semiconductor layer, and continuing to form the first semiconductor layer or the first pillar semiconductor layer; and when the first conductive type doped region is formed in the body region, forming the first conductive type doped region at a preset position of the first semiconductor layer, and continuing to form the first semiconductor layer.
Specifically, the method of forming the first conductivity type doped region includes ion implantation or other suitable method.
Specifically, the location and size of the first conductivity type doped region may be selected according to practical situations, which are not limited herein; the doping concentration of the first conductivity type doped region may be selected according to practical situations, and is not limited herein.
As an example, the first conductivity type doped region is located below the trench and is in electrical contact with the source electrode, and ion implantation is performed on the bottom of the trench to form the first conductivity type doped region after the trench is formed and before the source electrode is formed.
Specifically, the method for forming the source electrode includes sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition, or other suitable methods.
Specifically, the method for forming the drain electrode includes sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition, or other suitable methods.
In the method for manufacturing the super-junction MOSFET of this embodiment, after the trench penetrating the source region and extending at least to the body region is formed, the first conductivity type doped region is directly formed in the body region or the second conductivity type column at the bottom of the trench, so that the difficulty in manufacturing the device is not increased while the reverse recovery softness factor of the device is increased.
In summary, in the super-junction MOSFET and the method for manufacturing the same, the source penetrates the source region and extends into at least the body region, schottky contact is formed between the source and the body region, the schottky barrier layer between the source and the body region is used to reduce the number of unbalanced carriers injected into the source when the device is turned on reversely, so that the reverse recovery softness factor of the device is increased, and the leakage current of the device is not increased; at least one first conductive type doped region and the body region or the second conductive type column are arranged in the body region or the second conductive type column of the device to compensate each other, so that the number of unbalanced carriers in a junction region between the body region and the second conductive type column and between the first conductive type column and the buffer region is reduced, the reverse recovery softness factor of the device is further increased, when the first conductive type doped region is positioned in the body region or the second conductive type column below the bottom of the trench, the concentration of the first conductive type doped region, the distance between the first conductive type doped region and the source electrode and the doping concentration between the first conductive type doped region and the source electrode are adjusted, the charge aggregation is generated on one surface of the first conductive type doped region far away from the source electrode, and then the reverse breakdown point of the device is adjusted to the first conductive type doped region, so that the starting of a parasitic triode in the device is inhibited, and the avalanche resistance of the device is improved; when the first conductive type doped region is positioned in the body region at the bottom of the groove or in the second conductive type column, the first conductive type doped region can be formed directly after the groove is formed, so that the reverse recovery softness factor of the device is increased, and meanwhile, the manufacturing process difficulty of the device is not increased; in addition, the method of forming the first conductivity type doped region in the second conductivity type body region and forming the schottky contact between the body region and the source electrode can be applied to the IGBT device to increase the device reverse recovery softness factor. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.
Claims (13)
1. A superjunction MOSFET comprising:
a first conductivity type substrate;
a first conductive type buffer region stacked on an upper surface of the substrate;
a first conductive type column disposed on an upper surface of the buffer region and extending in a direction away from the substrate, the first conductive type column including a first column region and a second column region stacked on the first column region;
the second conductive type column is arranged on the upper surface of the buffer area and positioned on two sides of the first column area, the side wall of the second conductive type column is adjacent to the side wall of the first column area, and the upper surface of the second conductive type column is flush with the upper surface of the first column area;
a second conductive type body region stacked on an upper surface of the second conductive type column, wherein the upper surface of the body region is flush with the upper surface of the second column region, and a side wall of the body region is adjacent to a side wall of the second column region;
a source region of a first conductivity type located on an upper surface of the body region, the source region being spaced a predetermined distance from the first conductivity type column;
the grid electrode structure is positioned on the upper surfaces of the body region and the second column region, and two ends of the grid electrode structure extend to the upper part of the source region;
a plurality of spaced apart trenches extending through the source region and at least into the body region;
the source electrode covers the exposed surfaces of the grid structure, the source region and the body region and fills the groove, the drain electrode covers the bottom surface of the substrate, the contact type of the source electrode and the source region is ohmic contact, and the contact type of the body region and the source electrode is Schottky contact.
2. The superjunction MOSFET of claim 1, wherein: the doping concentration of the substrate is lower than that of the buffer region, and the doping concentration of the buffer region is lower than that of the first conductive type column.
3. The superjunction MOSFET of claim 1, wherein: the barrier height of the schottky contact between the body region and the source is not higher than 0.7eV.
4. The superjunction MOSFET of claim 1, wherein: the trench penetrates through the source region and extends into the body region, and the bottom of the trench is spaced from the bottom surface of the body region by a preset distance.
5. The superjunction MOSFET of claim 4, wherein: the superjunction MOSFET also includes at least one doped region of the first conductivity type located in the body region or the second conductivity type pillar.
6. The superjunction MOSFET of claim 5, wherein: the first-conductivity-type doped region is located below the trench, a reverse breakdown point of the superjunction MOSFET is located at the first-conductivity-type doped region, and a distance from the first-conductivity-type doped region to the bottom of the trench is less than 2 μm.
7. The superjunction MOSFET of claim 1, wherein: the trench penetrates the body region and a bottom surface of the trench is flush with a bottom surface of the body region or extends into the second conductivity type column.
8. The superjunction MOSFET of claim 7, wherein: the superjunction MOSFET also includes at least one doped region of the first conductivity type located in the second conductivity type pillar.
9. The superjunction MOSFET of claim 8, wherein: the first-conductivity-type doped region is located below the trench, a reverse breakdown point of the superjunction MOSFET is located at the first-conductivity-type doped region, and a distance from the first-conductivity-type doped region to the bottom of the trench is less than 2 μm.
10. The superjunction MOSFET of claim 1, wherein: the grid structure comprises a grid dielectric layer and a grid electrode, and the grid dielectric layer wraps the grid electrode.
11. The manufacturing method of the super junction MOSFET is characterized by comprising the following steps of:
providing a first conductive type substrate, and forming a first conductive type buffer area on the upper surface of the substrate;
forming a first conductive type first column region and second conductive type columns positioned on two sides of the first column region on the upper surface of the buffer region, wherein the side walls of the second conductive type columns are adjacent to the side walls of the first column region, and the upper surface of the first column region is flush with the upper surface of the second conductive type columns;
forming a first conductive type second column region on the upper surface of the first column region to form a first conductive type column, forming a second conductive type body region which is positioned on the upper surface of the second conductive type column and is adjacent to the side wall of the second column region on two sides of the second column region, wherein the upper surface of the body region is flush with the upper surface of the second column region;
forming a first conductive type source region in an upper surface layer of the body region, wherein the source region is spaced from the first conductive type column by a preset distance;
forming a grid structure on the upper surfaces of the first conductive type column and the body region, wherein two ends of the grid extend to the upper part of the source region;
forming a groove penetrating the source region and extending to at least the body region from the bottom in the source region, forming a source electrode covering the gate structure, the source region and the exposed surface of the body region and filling the groove, and forming a drain electrode covering the bottom surface of the substrate, wherein the contact type of the source electrode and the source region is ohmic contact, and the contact type of the source electrode and the body region is Schottky contact.
12. The method for manufacturing the super junction MOSFET according to claim 11, wherein: the method for manufacturing the super junction MOSFET further comprises the step of forming a first conductive type doped region in the body region or the second conductive type column.
13. The method for manufacturing the super junction MOSFET according to claim 12, wherein: the first conductive type doped region is positioned below the groove and is electrically contacted with the source electrode, and after the groove is formed, ion implantation is performed on the bottom of the groove to form the first conductive type doped region before the source electrode is formed.
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