CN213424747U

CN213424747U - Voltage-resistant large-current chip thermistor

Info

Publication number: CN213424747U
Application number: CN202022457867.3U
Authority: CN
Inventors: 张健; 吴建万; 温子松; 于立新
Original assignee: Huizhou Darong Electronic Technology Co ltd
Current assignee: Huizhou Darong Electronic Technology Co ltd
Priority date: 2020-10-29
Filing date: 2020-10-29
Publication date: 2021-06-11
Anticipated expiration: 2030-10-29

Abstract

A pressure-resistant large-current chip thermistor comprises a conduction assembly and a welding assembly, wherein the conduction assembly comprises a central interlayer, two separation layers, two first conductive layers, two second conductive layers and two conduction bodies, two ends of the central interlayer are respectively connected with the two conduction bodies, the two first conductive layers are arranged on two sides of the central interlayer in a one-to-one correspondence mode, the two separation layers are arranged on the two first conductive layers in a one-to-one correspondence mode, the two second conductive layers are arranged on the two separation layers in a one-to-one correspondence mode, the welding assembly comprises two insulation layers, two first welding discs and two second welding discs, the two first welding discs are connected with the two conduction bodies in a one-to-one correspondence mode, the two second welding discs are connected with the two conduction bodies in a one-to-one correspondence mode, and more conductive paths can be formed between the two conduction bodies when the welding assembly is electrified, therefore, the device can bear larger voltage and current and effectively prevent the device from being damaged.

Description

Voltage-resistant large-current chip thermistor

Technical Field

The utility model relates to a paster thermistor technical field especially relates to a withstand voltage heavy current paster thermistor.

Background

Thermistors are temperature sensitive elements and are classified into positive temperature coefficient thermistors (PTC) and negative temperature coefficient thermistors (NTC) according to their temperature coefficients. Thermistors are typically temperature sensitive and exhibit different resistance values at different temperatures. A positive temperature coefficient thermistor (PTC) has a higher resistance value at a higher temperature, and a negative temperature coefficient thermistor (NTC) has a lower resistance value at a higher temperature.

For PTC, according to the material, the material is divided into ceramic thermistor and polymer thermistor, and the polymer thermistor, also called self-recovery fuse, is usually connected in series to the circuit for use, when the temperature rises due to the fault such as short circuit, the polymer thermistor will be in the crystalline state to block the conductive network formed by the internal conductive particles, thereby achieving the purpose of breaking, when the temperature drops, the polymer will eliminate the crystalline state to enable the conductive particles to reform the conductive network into the conductive network to be in the conductive state, the polymer thermistor has small size and low resistance, and at the same time, the reaction is fast and widely accepted, however, the polymer thermistor on the market at present is difficult to bear large voltage and large current, when large voltage and large current appear in the circuit, the polymer thermistor is easy to be burned out, thereby the operation of replacing the polymer thermistor is needed, therefore, the effect that the polymer thermistor can be conducted repeatedly is lost, and the polymer thermistor can damage a circuit even when being burnt, so that potential safety hazards are brought.

SUMMERY OF THE UTILITY MODEL

The utility model aims at overcoming the weak point among the prior art, providing a withstand voltage heavy current paster thermistor that can bear the heavy current of big voltage, can switch on repeatedly safely, prevent to be burnt out.

The purpose of the utility model is realized through the following technical scheme:

a voltage-resistant large-current chip thermistor comprises:

the conduction assembly comprises a central interlayer, two separation layers, two first conductive layers, two second conductive layers and two conduction bodies, wherein the two conduction bodies are arranged in opposite directions, two ends of the central interlayer are respectively connected with the two conduction bodies, the two first conductive layers are arranged on two sides of the central interlayer in a one-to-one correspondence manner, the two first conductive layers are connected with one of the conduction bodies, the two separation layers are arranged on the two first conductive layers in a one-to-one correspondence manner, the two separation layers are connected with the central interlayer, the two second conductive layers are arranged on the two separation layers in a one-to-one correspondence manner, and the two second conductive layers are connected with the other conduction body; and

the welding subassembly, the welding subassembly includes two insulating layers, two first welding coils and two second welding coils, two the insulating layer one-to-one sets up in two on the second conducting layer, two first welding coils set up respectively in one of them on the both ends of insulating layer, and two first welding coils one-to-one and two the conduction body coupling, two the second welding coils set up respectively in another on the both ends of insulating layer, and two second welding coils one-to-one and two the conduction body coupling.

In one embodiment, the thickness of the central interlayer is 0.6-0.8 mm.

In one embodiment, the thickness of the central spacer layer is 0.7 mm.

In one embodiment, the first conductive layer and the second conductive layer are both copper foil layers.

In one embodiment, a protrusion is disposed on an end of the insulating layer, and the first bonding pad is located on the protrusion.

In one embodiment, the central barrier layer and the separation layer are both carbon fiber plates.

In one embodiment, the vias are copper plated layers.

In one embodiment, a semicircular groove is formed in an end portion of the central interlayer, and the conduction body is accommodated in the semicircular groove.

In one embodiment, a plurality of convex particles are arranged on the first welding disk, and a space is arranged between every two convex particles.

In one embodiment, the insulating layer is a polypropylene layer.

Compared with the prior art, the utility model discloses at least, following advantage has:

the utility model relates to a pressure-resistant large-current chip thermistor, which comprises a conduction assembly and a welding assembly, wherein the conduction assembly comprises a central interlayer, two separation layers, two first conductive layers, two second conductive layers and two conduction bodies, the two conduction bodies are oppositely arranged, two ends of the central interlayer are respectively connected with the two conduction bodies, the two first conductive layers are correspondingly arranged on two sides of the central interlayer one by one, and are respectively connected with one of the conduction bodies, the two separation layers are correspondingly arranged on the two first conductive layers one by one, and are respectively connected with the central interlayer, the two second conductive layers are correspondingly arranged on the two separation layers one by one, and are respectively connected with the other conduction body, the welding assembly comprises two insulation layers, two first welding discs and two second welding discs, the two insulation layers are correspondingly arranged on the two second conductive layers one by one, two first welding discs are arranged at two ends of one insulating layer respectively, the two first welding discs are in one-to-one correspondence with the two conduction bodies and are connected with the two conduction bodies, the two second welding discs are arranged at two ends of the other insulating layer respectively, the two second welding discs are in one-to-one correspondence with the two conduction bodies and are connected with the two conduction bodies, and when the two conduction bodies are electrified, more conduction passages can be formed between the two conduction bodies, so that larger voltage and current can be borne, and the two conduction bodies are effectively prevented from being damaged.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are required to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention, and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts.

Fig. 1 is a schematic structural diagram of a voltage-withstanding large-current chip thermistor according to an embodiment of the present invention;

fig. 2 is a schematic cross-sectional structure view of the voltage-resistant large-current chip thermistor shown in fig. 1.

Detailed Description

In order to facilitate understanding of the present invention, the present invention will be described more fully hereinafter with reference to the accompanying drawings. The preferred embodiments of the present invention are shown in the drawings. The invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

It will be understood that when an element is referred to as being "secured to" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present. The terms "vertical," "horizontal," "left," "right," and the like as used herein are for illustrative purposes only and do not represent the only embodiments.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

It is noted that as used herein, reference to an element being "connected" to another element also means that the element is "in communication" with the other element, and fluid can be in exchange communication between the two.

Referring to fig. 1, a voltage-withstanding large-current chip thermistor 10 includes a conducting assembly 100 and a welding assembly 200, wherein the welding assembly 200 is disposed on the conducting assembly 100.

Referring to fig. 1 and 2, the conductive assembly 100 includes a central spacer 110, two separation layers 120, two first conductive layers 130, two second conductive layers 140 and two conductive vias 150, the two conductive vias 150 are oppositely disposed, two ends of the central spacer 110 are respectively connected to the two conductive vias 150, the two first conductive layers 130 are correspondingly disposed on two sides of the central spacer 110, the two first conductive layers 130 are respectively connected to one of the conductive vias 150, the two separation layers 120 are correspondingly disposed on the two first conductive layers 130, the two separation layers 120 are respectively connected to the central spacer 110, the two second conductive layers 140 are correspondingly disposed on the two separation layers 120, and the two second conductive layers 140 are respectively connected to the other conductive via 150.

It should be noted that the central interlayer 110 is a layered structure, and the first conductive layer 130 is respectively attached to two side surfaces of the central interlayer 110, in an embodiment, the first conductive layer 130 is a copper foil layer; in one embodiment, the central barrier layer 110 is a fiberboard having first conductive layers 130 attached to both sides of the fiberboard; in one embodiment, the central interlayer 110 may also be a mixture of polyethylene and metal particles, and the mixture of polyethylene and metal particles is coated between two copper foil layers to form a structure in which the first conductive layers 130 are respectively disposed on two sides of the central interlayer 110, it should be noted that, in this case, the structure of the central interlayer 110 and the two first conductive layers 130 is plate-shaped, then the conductive vias 150 are respectively disposed on two ends of the structure of the plate-shaped central interlayer 110 and the two first conductive layers 130, and both the two first conductive layers 130 are connected to one of the conductive vias 150, in one embodiment, the conductive vias 150 are copper-plated layers, for example, the conductive vias 150 may be copper layers formed by an electroplating process, so that the conductive vias 150 are in conduction with the two first conductive layers 130; further, two separation layers 120 are disposed on the two first conductive layers 130 in a one-to-one correspondence, specifically, the separation layers 120 are tightly attached to the first conductive layers 130, in an embodiment, the separation layers 120 and the central separation layer 110 are made of the same material, and may be made of a fiber board, or may be made of a plate-shaped structure formed by a mixture of polyethylene and metal particles, and it should be noted that, since the central separation layer 110 is formed between the two first conductive layers 130 by a coating production process, and the two first conductive layers 130 require one conductive body 150 disposed therein to be connected, in order to prevent the two first conductive layers 130 from being connected to the other conductive body 150, an insulating groove 131 needs to be formed on the first conductive layer 130 before the separation layers 120 are attached to the first conductive layers 130, so that, when the separation layers 120 are attached to the first conductive layers 130, the separation layer 120 is also partially filled into the insulation groove 131, so that a gap between interlayers can be prevented; further, two second conductive layers 140 are disposed on two separation layers 120 in a one-to-one correspondence, specifically, the second conductive layers 140 are closely attached to the separation layers 120, in an embodiment, the second conductive layers 140 are also copper foil layers, the second conductive layers 140 are connected to another conductive body 150, it should be noted that the conductive bodies 150 connected to the second conductive layers 140 and the first conductive layers 130 are not identical, and therefore, the second conductive layers 140 are also provided with isolation grooves 141, and in an embodiment, the isolation grooves 141 and the insulation grooves 131 are both formed by using an etching process.

Referring to fig. 1 and fig. 2 again, the welding assembly 200 includes two insulating layers 210, two first bonding pads 220 and two second bonding pads 230, the two insulating layers 210 are disposed on the two second conductive layers 140 in a one-to-one correspondence manner, the two first bonding pads 220 are disposed on two ends of one of the insulating layers 210 respectively, the two first bonding pads 220 are connected to the two conductive bodies 150 in a one-to-one correspondence manner, the two second bonding pads 230 are disposed on two ends of the other insulating layer 210 respectively, and the two second bonding pads 230 are connected to the two conductive bodies 150 in a one-to-one correspondence manner.

It should be noted that the insulating layer 210 is attached to an outer side wall of the second conductive layer 140, and the insulating layer 210 is used to isolate the second conductive layer 140 from contacting with the outside, so as to protect the second conductive layer 140; further, the first bonding pads 220 are disposed on the insulating layers 210, specifically, two first bonding pads 220 are disposed on one of the insulating layers 210, the two first bonding pads 220 are respectively located at two ends of the insulating layer 210, the two first bonding pads 220 are connected to the two conductive bodies 150 in a one-to-one correspondence, two second bonding pads 230 are similarly mounted on the other insulating layer 210, the two second bonding pads 230 are respectively located at two ends of the insulating layer 210, and the second bonding pads 230 are similarly connected to the two conductive bodies 150 in a one-to-one correspondence, so that the two first bonding pads 220 and the two second bonding pads 230 are utilized, the high-current voltage-withstanding chip thermistor 10 of the present application can be mounted on any surface, and the problem of wrong mounting direction is not generated.

It should be noted that, when two conductive bodies 150 are connected in series to a circuit by using two first bonding pads 220 or two second bonding pads 230, if the circuit operates normally and no fault such as short circuit occurs, the temperature of the high-current voltage-withstanding chip thermistor 10 of the present application does not increase, at this time, the two conductive bodies 150 can realize circuit conduction by using conductive particles in the central interlayer 110 and the two separation layers 120, specifically, since one conductive body 150 is provided with two first conductive layers 130, and the other conductive body 150 is connected with two second conductive layers 140, conductive particles between the two first conductive layers 130 and the two second conductive layers 140 can respectively form conductive paths, that is, the conductive area per unit area is increased, so that the high-current voltage-withstanding chip thermistor 10 of the present application can bear higher voltage and current, to prevent damage by large voltage and large current.

In one embodiment, the thickness of the central barrier layer 110 is 0.6-0.8 mm, specifically, the thickness of the central barrier layer 110 may be 0.7mm, and further, the thickness of the separation layer 120 is the same as that of the central barrier layer 110.

Referring to fig. 2 again, in one embodiment, a protrusion 211 is disposed on an end of the insulating layer 210, and the first bonding pad 220 is disposed on the protrusion 211. It should be noted that, by providing the protrusion 211 at the end of the insulating layer 210 and then disposing the first soldering land 220 on the protrusion 211, when the high-current voltage-withstanding chip thermistor 10 of the present application is mounted on a circuit board, the insulating layer 210 at the side close to the circuit board can be ensured to keep a certain distance from the circuit board, so that the heat dissipation of the high-current voltage-withstanding chip thermistor 10 of the present application is facilitated.

Referring to fig. 1 again, in one embodiment, a semicircular groove is formed at an end of the central spacer 110, and the conductive body 150 is accommodated in the semicircular groove. In one embodiment, the conductive via 150 is formed by a plating process, and the conductive via 150 is used to connect the two first conductive layers 130 or the second conductive layers 140, and in one embodiment, the high-current voltage-resistant chip thermistor 10 of the present application is processed by drilling, and then the conductive via 150 is formed by plating copper on the wall of the drilled hole by the plating process, so that the conductive via 150 is accommodated in the wall of the semicircular groove.

Referring to fig. 1 and fig. 2 again, in one embodiment, a plurality of bumps 221 are disposed on the first bonding pad 220, and a space is disposed between the bumps 221. Note that, since the plurality of bumps 221 are provided on the first bonding pad 220, and in one embodiment, the structure equivalent to the bumps 221 is provided on the second bonding pad 230, the high-current withstand voltage chip thermistor 10 of the present invention can be bonded more firmly when it is bonded to a circuit board.

The above-mentioned embodiments only represent some embodiments of the present invention, and the description thereof is specific and detailed, but not to be construed as limiting the scope of the present invention. It should be noted that, for those skilled in the art, without departing from the spirit of the present invention, several variations and modifications can be made, which are within the scope of the present invention. Therefore, the protection scope of the present invention should be subject to the appended claims.

Claims

1. A withstand voltage large current chip thermistor is characterized by comprising:

2. The voltage-resistant large-current chip thermistor according to claim 1, wherein the thickness of the central interlayer is 0.6-0.8 mm.

3. The voltage-resistant high-current chip thermistor according to claim 2, wherein the thickness of the central spacer layer is 0.7 mm.

4. The voltage-resistant high-current chip thermistor according to claim 1, wherein the first conductive layer and the second conductive layer are both copper foil layers.

5. The voltage-resistant high-current chip thermistor according to claim 1, wherein a protrusion is provided on an end of the insulating layer, and the first bonding pad is located on the protrusion.

6. The voltage-resistant high-current chip thermistor according to claim 1, wherein the central barrier layer and the separation layer are both carbon fiber plates.

7. The voltage-resistant high-current chip thermistor according to claim 1, wherein the via is a copper plated layer.

8. The voltage-resistant large-current chip thermistor according to claim 1, wherein a semicircular groove is formed at an end of the central interlayer, and the conductor is accommodated in the semicircular groove.

9. The voltage-resistant large-current chip thermistor according to claim 1, wherein a plurality of bumps are provided on the first bonding pad, and a space is provided between the bumps.

10. The voltage-resistant high-current chip thermistor according to claim 1, wherein the insulating layer is a polypropylene layer.