CN213342249U

CN213342249U - LIN network simulation system

Info

Publication number: CN213342249U
Application number: CN202022578585.9U
Authority: CN
Inventors: 贺云龙; 王云柯
Original assignee: Chongqing Sumarte Technology Development Co ltd
Current assignee: Chongqing Sumarte Technology Development Co ltd
Priority date: 2020-11-10
Filing date: 2020-11-10
Publication date: 2021-06-01
Anticipated expiration: 2030-11-10

Abstract

The utility model discloses a LIN network simulation system, AND gate is connected through two way LIN passageways on MCU, and the isolator is connected to the AND gate output, and LIN transceiver, LIN transceiver and LIN bus connection are connected to the isolator. The invention can realize that the main mode channel only sends the frame head, the auxiliary mode channel monitors and only provides the response function. In the slave mode, the system receives the frame header and generates interruption, thereby solving the problem that the frame header is not generated when the master mode sends the frame header; the LIN network can be well simulated under the condition of a single node, the LIN channel of the master mode serves as a master node, the LIN channel of the slave mode serves as a slave node, and when the master node continuously sends a frame header, the slave node is always in a monitoring state and performs corresponding processing according to the received interrupt generated by the frame header; in an actual LIN network, the last generated LIN node in the present application may serve as a host node of the network, and is used to schedule the transmission order of frames on the bus, monitor data, process errors, and the like, by sending a frame header.

Description

LIN network simulation system

Technical Field

The utility model relates to an automobile bus technical field especially relates to a LIN network simulation system and data transmission method.

Background

In the simulation and measurement of the PowerPC57xx series MCU on the LIN network, if this method is implemented by a LIN channel of the MCU that supports both master and slave modes, from a software configuration level, the channel is configured either as master or slave. When the channel is used as a host node, an internal implementation mechanism of the channel cannot separate the host node into a master task and a slave task, when the host node is required to provide a response, a frame header and data must be sent simultaneously, that is, the frame header and the response cannot be provided respectively, and the frame header and a frame data field cannot be interrupted respectively. If the frame header and the data are sent simultaneously, the timestamp can be marked only at the moment when one frame of message is finished, so that the recorded timestamp is not accurate.

Therefore, those skilled in the art are dedicated to developing an LIN network simulation system specifically for the PowerPC57xx series MCU, which can effectively solve the problem that the PowerPC57xx series MCU cannot separate the master and slave tasks of the host node during LIN network communication, and can not only virtualize the whole LIN network, but also complement the real LIN network.

SUMMERY OF THE UTILITY MODEL

In view of the above-mentioned defect of the prior art, the technical problem to be solved in the utility model is to provide a LIN network simulation system to PowerPC57xx series MCU specially, can effectively solve PowerPC57xx series MCU and can not provide the detached problem of the principal and subordinate task of host node when LIN network communication, the master channel of node provides the message head in this application, and the slave channel can be configured into arbitrary slave node and provide the response. In an actual network, the node can serve as a master node to provide a message header and also serve as a slave node to provide a response. Thus, the whole LIN network can be virtualized, and the real LIN network can be supplemented.

In order to achieve the purpose, the utility model provides a LIN network simulation system connects an AND gate through two way LIN passageways on MCU, the AND gate output is connected with the isolator, the isolator is connected to LIN transceiver, LIN transceiver and LIN bus connection.

Preferably, the TX pins of the two LIN channels are connected to the and gate, and are connected to the TXD terminal of the LIN transceiver through the isolator.

Preferably, RX pins of the two LIN channels are directly connected to RXD terminals of the LIN transceiver through the isolators.

Preferably, the MCU also comprises a GPIO pin output control module, and the VIA pin and the VIB pin of the GPIO pin output control module are respectively connected to the two GPIO pins of the MCU.

The utility model has the advantages that: the utility model discloses can realize that the master mode passageway only sends the frame head, monitor from the mode passageway, only provide the response, receive the frame head under the slave mode and will produce the interrupt, solve master mode and send the frame head and do not produce the problem of interrupt; the LIN network can be well simulated under the condition of a single node, the LIN channel of the master mode serves as a master node, the LIN channel of the slave mode serves as a slave node, and when the master node continuously sends a frame header, the slave node is always in a monitoring state and performs corresponding processing according to the received interrupt generated by the frame header; in an actual LIN network, the last generated LIN node in the application can serve as a host node of the network, and is used for scheduling the transmission sequence of frames on a bus, monitoring data, processing errors and the like by sending a frame header; the bus can also flexibly act as a slave node to realize the scheduling of the master node on the bus and provide response.

Drawings

Fig. 1 is a schematic structural diagram of an embodiment of the present invention.

Fig. 2 is a circuit structure diagram of an embodiment of the present invention.

Detailed Description

The present invention will be further explained with reference to the drawings and examples.

As shown in fig. 1 and 2, in the LIN network simulation system, an and gate U36 is connected to an MCU through two LIN channels (the MCU is provided with a pin supporting LIN, and can be directly connected to the MCU), in this embodiment, an and gate U36 directly uses a 74LVC1GO8 chip, an output end of an and gate U36 is connected to an isolator U38, an isolator U38 uses an ADuM1201BRZ chip, an isolator U38 is connected to a LIN transceiver U37, an LIN transceiver U37 uses a MAX13021ASA + chip, and an LIN transceiver U37 is connected to a LIN bus.

The TX pins of the two LIN channels are connected to an and gate U36, and to the TXD terminal of LIN transceiver U37 through an isolator U38. That is, the TX pins of the two LIN channels are output through an and gate, through which connection the voltage level at the terminal of LIN transceiver U37 TXD is determined by the output terminal of and gate U36. The RX pins of the two LIN channels are directly connected to the RXD terminal of the LIN transceiver U37 through isolators, so that the RX pin level of the LIN channel is determined by the output terminal of the LIN transceiver U37.

This application still includes GPIO pin output control module U4O, adopts ADuM1200ARZ chip in this application, for an isolation chip, on its VIA pin and VIB pin were connected to MCU's two GPIO pins respectively. The VIA pin input is output through a VOA pin of an isolator, the level of the VIA pin input controls a sleep function, the VIB pin input is output through a VOB pin of the isolator, and the level of the VIB pin input controls whether the VIA pin is pulled up or not. The VIA pin and the VIB pin can play a role in electrical isolation from the VOA pin and the VOB pin through the isolators, so that circuits of different physical parts are not interfered, and the level of the output of the VIA pin and the VIB pin is consistent with the level of the GPIO pin on the MCU.

In the application, the LIN transceiver U37 supports a sleep mode (a sleep pin of the transceiver U37 is connected to one GPIO pin of a main chip), and whether the LIN transceiver U37 enters a low power consumption state is determined by outputting a high level and a low level through the GPIO pin.

In the application, the LIN bus is also connected with a controllable pull-up circuit, and whether the level of the LIN bus needs to be pulled up to a 12V power supply or not can be selected according to different configurations of master nodes and slave nodes. The pull-up circuit is connected with one GPIO pin of the MCU, and controls whether the LIN bus is pulled up or not by outputting high and low levels through the GPIO pin.

The LIN network simulation system can be realized by the following method:

1) two LIN channels are arranged and connected to the MCU, wherein one LIN channel supporting a master is used as a master task of a node to provide a frame header, and the other LIN channel supporting a slave is used as a slave task of the node to provide a response;

2) the TX pins of the two LIN channels are output through the same AND gate and then reach an LIN transceiver through an isolator;

3) directly connecting RX pins of the two LIN channels to an LIN transceiver through an isolator;

4) the LIN transceiver converts the received signal into a LIN node, which is connected to the LIN bus.

In the present application, one LIN node (hereinafter referred to as "this node") is implemented by two LIN channels, where one LIN channel is a master mode and the other LIN channel is a slave mode. When two channels are used simultaneously, a virtual LIN network can be simulated, in which: the channel configured as the main mode serves as a main node of the virtual network and provides a message header; the channel configured as a slave mode can act as any slave node and respond differently to the request of the master node. In a practical network, this LIN node acts as a master node in the LIN network when two channels are used simultaneously, wherein the channel configured as master mode performs the master task: providing a message header; the channel configured as slave mode performs the slave tasks: a response is provided. When only channels configured as slave are used, this node can act as a slave in the LIN network, providing responses to other nodes in the LIN network. The purpose of independently opening the master task and the slave task of a node is achieved, the master task and the slave task can respectively generate interrupt when the frame header and the data are provided, and different things are interrupted according to independent interrupt processing.

In the application, two LIN channels are used as one LIN node, wherein one LIN channel is configured as a master mode and used for fixing a sending frame header, and the frame header sent by the master mode LIN channel includes a synchronous interval segment, a synchronous segment and a pid (protected identifier) segment. The other LIN channel is configured to receive frame headers from the mode and to send or receive acknowledgements, the acknowledgements provided from the mode LIN channel comprising data segments and checksum segments. A Header receive interrupt is generated after the frame Header is received from the mode, and can be used to record the timestamp of the frame or to handle a series of things. LIN channels configured as slave mode, may have a different schedule than the master node: including a schedule for sending responses, a schedule for receiving responses, and scheduling the processing of different PIDs. When the frame header is received, whether a response needs to be sent or received or neither a response is received or sent is judged according to the agreed PID. While diagnostic functions may be implemented according to the schedule.

The foregoing has described in detail preferred embodiments of the present invention. It should be understood that numerous modifications and variations can be devised by those skilled in the art in light of the teachings of the present invention without undue experimentation. Therefore, the technical solutions that can be obtained by a person skilled in the art through logic analysis, reasoning or limited experiments based on the prior art according to the concepts of the present invention should be within the scope of protection defined by the claims.

Claims

1. A LIN network simulation system is characterized in that: the MCU is connected with an AND gate through two LIN channels, the output end of the AND gate is connected with an isolator, the isolator is connected to an LIN transceiver, and the LIN transceiver is connected with an LIN bus.

2. The LIN network simulation system of claim 1, wherein: TX pins of the two LIN channels are connected with the AND gate and are connected to the TXD end of the LIN transceiver through the isolator.

3. The LIN network simulation system of claim 1, wherein: RX pins of the two LIN channels are directly connected to RXD ends of the LIN transceivers through the isolators.

4. The LIN network simulation system of claim 1, wherein: and the GPIO pin output control module is also included, and the VIA pin and the VIB pin of the GPIO pin output control module are respectively connected to the two GPIO pins of the MCU.