CN213342248U

CN213342248U - Domain controller based on time sensitive network transmission

Info

Publication number: CN213342248U
Application number: CN202022432556.1U
Authority: CN
Inventors: 肖文平; 胡世荣
Original assignee: Shanghai Hinge Electronic Technologies Co Ltd
Current assignee: Shanghai Hinge Electronic Technologies Co Ltd
Priority date: 2020-10-28
Filing date: 2020-10-28
Publication date: 2021-06-01
Anticipated expiration: 2030-10-28

Abstract

The utility model provides a domain controller based on time sensitive network transmission, include: multilayer PCB board, SOC system level chip, memory, MCU chip, sensitive network switch of the first time, the sensitive network connector of the first time, the sensitive network switch of second time, the sensitive network connector of second time, CAN chip, LIN chip, the utility model discloses set up time sensitive network switch and a plurality of different time sensitive network assorted high-speed interface, made it CAN satisfy the demand of high-speed high bandwidth in the intelligence internet access. In addition, the multilayer PCB structure is 10 layers, different chips are placed in the corresponding PCB layer structure, a high-density domain controller board is directly synthesized by the traditional core board and the main board, and the high cost caused by secondary chip mounting and the adoption of a BTB connector in the synthesis process is avoided.

Description

Domain controller based on time sensitive network transmission

Technical Field

The utility model relates to an intelligent automobile domain controller especially relates to a domain controller based on time sensitive network transmission.

Background

With the continuous development of scientific technology, automobiles develop towards intellectualization, comfort and individualization, the traditional automobile network with a distributed architecture is difficult to meet the requirements of the current automobile development, the automobiles are required to be assembled with dozens of sensors for intellectualization and comfort, for example, the automobiles are required to be provided with vehicle-mounted cameras, laser radars, millimeter wave radars, inertial sensors and the like for intelligent driving, so that a large number of sensors need to transmit a large amount of data, the traditional CAN bus is difficult to meet the requirements of bandwidth transmission, in addition, the number of sensors CAN increase the number of ECUs, in order to reduce the cost, the current proposal that a centralized automobile network architecture CAN be adopted in the future, and a high-performance domain controller is adopted to control the ECUs and reduce the wiring harness cost. The existing domain controller product is still mainly based on CAN bus network transmission, a core board and a mainboard are adopted on hardware to form the domain controller product through a BTB connector, the core PCB comprises 10 layers of 3-step and the mainboard is a 6-layer through hole, the core board is mainly provided with an MCU and an SOC device, has strong expansibility and CAN be installed on different mainboards to enable the core board to have different functions and meet the customization requirements of different customers, but the product needs to be pasted twice, the cost of the BTB connector is high, the service life of the BTB connector CAN be influenced in a simulation test, such as a road surface pothole environment, and the service life of the BTB connector is low in a vibration test. In order to solve the problems of the defects in the prior art, it is necessary to provide a domain controller with high speed, long service life and low cost to solve the defects in the prior art.

SUMMERY OF THE UTILITY MODEL

The utility model provides a domain controller based on time sensitive network transmission specifically includes: the PCB comprises a plurality of layers of PCBs, a chip assembly and a connector assembly, wherein the chip assembly and the connector assembly are arranged on the PCBs;

the chip assembly at least includes: the system comprises an SOC (system on chip), a memory and an MCU (microprogrammed control unit) chip, wherein the SOC chip is connected with the MCU and the memory;

the connector assembly includes at least: the system comprises a first time-sensitive network switch, a first time-sensitive network connector, a second time-sensitive network switch and a second time-sensitive network connector, wherein the first time-sensitive network switch is connected with the first time-sensitive network connector, and the second time-sensitive network switch is connected with the first time-sensitive network connector;

the first time-sensitive network switch is connected with the SOC, and the second time-sensitive network switch is respectively connected with the MCU chip and the SOC.

A domain controller based on time sensitive network transmission, further the connector assembly further comprising: the display screen connector is connected with the display screen connecting chip; the camera connector is connected with the camera connecting chip; the chip comprises a first connector and a first connector chip, wherein the first connector is connected with the first connector chip, and the second connector is connected with the second connector chip.

A domain controller based on time sensitive network transmission, further, the first time sensitive network connector comprises 2 1000base-Tx interfaces, 1 100base-T1 interfaces, 1 100base-Tx interfaces; the second time-sensitive network connector comprises: 4 100base-T1 interfaces and 4 1000base-T1, wherein each interface works independently;

in the first time-sensitive network switch and the second time-sensitive network switch, the data flow synchronization adopts an IEEE802.1AS-REV synchronization protocol, and the data flow control adopts IEEE802.1Qbv and IEEE802. Qch.

A domain controller based on time-sensitive network transmission is further disclosed, wherein a first connector comprises a CAN interface and an LIN interface, a second connector comprises a CAN interface and an LIN interface, a first connector chip comprises a CAN chip and an LIN chip, the second connector comprises a CAN chip and an LIN chip, the CAN interface in the first connector is connected with the CAN chip of the first connector, and the LIN interface in the first connector is connected with the LIN chip of the first connector; the CAN interface in the second connector is connected with a CAN chip of the second connector, and the LIN interface in the second connector is connected with an LIN chip of the second connector;

the camera connector comprises two paths of CSI interfaces, the camera connecting chip comprises two paths of serial-parallel conversion chips, and the CSI interfaces are connected with the serial-parallel conversion chips;

the display screen connector comprises two LVDS interfaces, the display screen connecting chip comprises two serializer chips, and each LVDS interface is connected with the corresponding serializer chip.

A domain controller based on time-sensitive network transmission further comprises an EMMC chip and a QFIflash, wherein the EMMC chip and the QFIflash are respectively connected with an SOC (system on a chip); the memory includes a plurality of DDRs.

The utility model provides a domain controller based on time sensitive network transmission, further, multilayer PCB board is provided with a plurality of putting different chip subassemblies and distinguishes, specifically includes: the CAN-LIN placing area is positioned above the PCB, the power supply placing area is positioned on the left side of the PCB, the MCU placing area is positioned on the right side, the SOC and memory placing area and the camera placing area are positioned on the upper right position, the time-sensitive network switch placing area is positioned on the lower position, and the EMMC and display screen connecting chip placing area is positioned on the lower right position;

the system comprises a CAN-LIN placing area, an SOC and memory placing area, a camera connecting chip placing area, a time-sensitive network switch placing area, an EMMC and display screen connecting chip placing area, a display screen connecting chip placing area and a display screen connecting chip placing area, wherein the CAN-LIN placing area is used for placing a CAN-LIN connector and a CAN-LIN connector chip, the MCU placing area is used for placing an MCU chip, the SOC and memory placing area is used for placing an SOC chip and a memory chip, the camera connecting chip placing area is used for connecting a camera connecting chip and a camera connector, the time-sensitive network switch placing area is used for placing a;

the multilayer PCB comprises 10 layers from L1 to L10 from top to bottom, wherein L1 is a top layer, and L10 is a bottom layer.

A domain controller based on time-sensitive network transmission further comprises power supply wiring and a ground plane corresponding to a power supply placing area, high-speed lines and RGMII high-speed signal wiring corresponding to a time-sensitive network switch placing area, a reference L2 layer meets high-speed signal impedance control, and the rest placing areas are low-speed signal wiring and a ground plane; at layer L2: the corresponding SOC and memory placement area are used for routing high-speed signals of the memory, and impedance control is met by referring to the L1 layer and the L3 layer.

A domain controller based on time sensitive network transmission further comprises a L4 layer, a corresponding SOC and a memory placing area are high-speed signal wiring, and an L3 layer and an L5 layer are referred to meet impedance control; the CSI high-speed signal routing is carried out in a corresponding camera connecting chip placing area, and impedance control is met by referring to the L2 layer and the L5 layer; the corresponding time-sensitive network switch is provided with RGMII high-speed signal wiring in the placement area, the reference L2 layer and the reference L5 layer meet impedance control, and the rest placement areas are low-speed signal wiring and a ground plane.

A domain controller based on time sensitive network transmission further comprises a L7 layer, a corresponding SOC and a memory placing area are high-speed signal wiring, and the reference L6 and L8 layers meet impedance control; the corresponding MCU placing area is provided with CAN \ LIN \ DR \ ADC signal routing;

the corresponding time-sensitive network switch arrangement area is a low-speed signal wire and a high-speed differential signal wire, and the differential signal reference L6 and L9 layers meet impedance control.

A domain controller based on time sensitive network transmission is further provided, wherein an L3 layer is a ground plane, an L5 layer is a power plane and a ground plane, an L6 layer is a power plane and a ground plane, an L9 layer is a part of power supply and low-speed signal routing, and the rest is the ground plane; the L10 layer is the power decoupling capacitor and the remaining peripheral circuit traces.

Has the advantages that:

the utility model provides a domain controller based on time sensitive network transmission directly can reduce cost with the domain controller board of the synthetic high density of traditional nuclear core plate and mainboard, improves practical reliability. Meanwhile, a time sensitive network switch and a plurality of interfaces matched with different time sensitive networks are arranged, so that the requirements of high speed and high bandwidth in the intelligent network connection can be met. In addition, the traditional CAN interface and LIN interface are configured, so that the system has downward compatibility and meets the requirements of different application scenes. In addition, by adopting a multi-layer PCB structure, the high-speed signal line is provided with an interference-free environment particularly aiming at the structural design that the SOC and the time sensitive network switch and the time sensitive network placing area are placed on different layers.

Drawings

Other features, objects, and advantages of the invention will become more apparent upon reading the attached drawings in reference to embodiments of the invention:

fig. 1 is a schematic diagram of a domain controller structure of a time-sensitive network according to an embodiment of the present invention.

Fig. 2 is a schematic diagram of a placement area structure of a PCB corresponding to a domain controller of a time-sensitive network according to an embodiment of the present invention.

Detailed Description

Hereinafter, the present invention will be described with reference to fig. 1 to 2, wherein the present invention is based on a time-sensitive network transmission domain controller. The following examples will assist those skilled in the art in further understanding the present invention, but are not intended to limit the invention in any way; it should be noted that, for those skilled in the art, many variations and modifications may be made without departing from the spirit of the invention; these all belong to the protection scope of the present invention.

The present embodiment provides a domain controller based on time-sensitive network transmission, referring to fig. 1 and fig. 2, specifically including: the PCB comprises a plurality of layers of PCBs, a chip assembly and a connector assembly, wherein the chip assembly and the connector assembly are arranged on the PCBs; the chip assembly at least includes: the system comprises an SOC (system on chip), a memory and an MCU (microprogrammed control unit) chip, wherein the SOC chip is connected with the MCU and the memory;

The SOC may be selected from BCM 5637, CellCepon 820, R-Car M3, or other available models.

The connector assembly further includes: the display screen connector is connected with the display screen connecting chip; the camera connector is connected with the camera connecting chip; the chip comprises a first connector and a first connector chip, wherein the first connector is connected with the first connector chip, and the second connector is connected with the second connector chip.

The first time-sensitive network connector comprises 2 1000base-Tx interfaces, 1 100base-T1 interfaces, 1 100base-Tx interfaces; the second time-sensitive network connector comprises: 4 100base-T1 interfaces and 4 1000base-T1, wherein each interface works independently;

Specifically, still include the power supply module, the power supply module includes: overload protection, switch, power chip, power supply module are used for supplying power to the equipment on the PCB.

Specifically, the implementation provides a plurality of different interfaces of the time-sensitive network connector, and can support cameras with different transmission rates, such as a camera, a laser radar, a millimeter wave radar and the like, and also support a traditional ethernet interface, such as a 100base-Tx interface, and in a research and development test stage, the domain controller of the present invention can be directly accessed to a device with an ethernet for debugging.

The time-sensitive network switch supports gigabit and hundred-gigabit Ethernet interfaces and can meet different scenes of intelligent driving.

The first connector comprises a CAN interface and an LIN interface, the second connector comprises a CAN interface and an LIN interface, the first connector chip comprises a CAN chip and an LIN chip, the second connector comprises a CAN chip and an LIN chip, the CAN interface in the first connector is connected with the CAN chip of the first connector, and the LIN interface in the first connector is connected with the LIN chip of the first connector; the CAN interface in the second connector is connected with a CAN chip of the second connector, and the LIN interface in the second connector is connected with an LIN chip of the second connector;

In this embodiment, since the conventional CAN protocol transmission has high reliability, and the vehicle still has signals transmitted by the CAN protocol in a short period, in order to be compatible with the ECU of the conventional CAN protocol, the CAN interface is still designed in this embodiment. The LIN interface is used for window control and door control, and the LIN interface is still reserved in the embodiment. In addition, according to different scenarios, in the first connector chip, the CAN chip may select a TJA1044 chip, and includes a CAN PHY in a multi-band standby mode (standby mode) based on a basic CAN transceiver, and in the second connector chip, the CAN chip employs a CAN PHY in a multi-band sleep mode (sleep mode) based on a CAN standby mode, which is TJA 1043.

An optional CAN chip may be a fault tolerant CAN (FT CAN, or low speed CAN) transceiver using TJA 1055.

The chip assembly also comprises an EMMC chip and a QFIflash, and the EMMC chip and the QFIflash are respectively connected with the SOC system level chip; the memory includes a plurality of DDR, which may be LPDDR4 or LPDDR 5.

In the time-sensitive network switch, transmission data comprises a diagnosis data stream, an audio-video data stream and a state control message data stream, wherein the diagnosis data provides diagnosis and firmware upgrading based on a DoIP protocol and a UDS protocol. The audio and video data stream has higher real-time requirement, an AVB protocol stack is adopted, SOME/IP and SOME/IP-SD protocol stacks are adopted for control or state information data stream, TSN-based transmission is adopted for control stream, and the transmission time accuracy of data is ensured. The AVB protocol stack includes: IEEE802.1AS, IEEE802.1Qav, IEEE802.1Qat, IEEE802.1BA, IEEE1722 and IEEE1722.1 protocols adopt AVB protocol stack to make multimedia data transmission reach real-time and synchronous requirements.

The multilayer PCB board is provided with a plurality of district of putting different chip subassemblies, refers to fig. 2, specifically includes: the CAN-LIN placing area is positioned above the PCB, the power supply placing area is positioned on the left side of the PCB, the MCU placing area is positioned on the right side, the SOC and memory placing area and the camera placing area are positioned on the upper right position, the time-sensitive network switch placing area is positioned on the lower position, and the EMMC and display screen connecting chip placing area is positioned on the lower right position;

the multilayer PCB comprises 10 layers, from top to bottom, L1 layers to L10 layers, L1 layers, L10 layers, 10 layers of 3-stage process is adopted for the PCB, and the design and signal power supply structure layout of each lamination are as follows:

L1 PCIE,100BASE,1000BASE；

L2 DDR；

L3 GND；

L4 DDR,RGMII,CSI,LVDS,EMMC,SD，OTHER；

L5 VCC,GND；

L6 VCC,GND；

L7 DDR，CAN,LIN,USB,OTHER；

L8 GND；

L9 OTHER；

L10

in the L1 layer, the corresponding power supply placing areas are power supply wires and a ground plane, the corresponding time sensitive network switch placing areas are high-speed lines and RGMII high-speed signal wires, the reference L2 layer meets high-speed signal impedance control, and the rest placing areas are low-speed signal wires and a ground plane; at layer L2: the corresponding SOC and memory placement area are used for routing high-speed signals of the memory, and impedance control is met by referring to the L1 layer and the L3 layer.

In the L4 layer, high-speed signal wiring corresponding to the SOC and the memory placing area is adopted, and the reference L3 layer and the reference L5 layer meet impedance control; the CSI high-speed signal routing is carried out in a corresponding camera connecting chip placing area, and impedance control is met by referring to the L2 layer and the L5 layer; the corresponding time-sensitive network switch is provided with RGMII high-speed signal wiring in the placement area, the reference L2 layer and the reference L5 layer meet impedance control, and the rest placement areas are low-speed signal wiring and a ground plane.

In the L7 layer, high-speed signal wiring corresponding to the SOC and the memory placing area is adopted, and impedance control is met by referring to the L6 layer and the L8 layer; the corresponding MCU placing area is provided with CAN \ LIN \ DR \ ADC signal routing;

The L3 layer is a ground plane, the L5 layer is a power plane and a ground plane, the L6 layer is a power plane and a ground plane, the L9 layer is a part of power supply and low-speed signal routing, and the rest is the ground plane; the L10 layer is the power decoupling capacitor and the remaining peripheral circuit traces.

The above is only the preferred embodiment of the present invention, and not the scope of the present invention, all the equivalent structures or equivalent flow changes made by the contents of the specification and the drawings or the direct or indirect application in other related technical fields are included in the patent protection scope of the present invention.

Claims

1. A domain controller based on time sensitive network transmission, comprising: the PCB comprises a plurality of layers of PCBs, a chip assembly and a connector assembly, wherein the chip assembly and the connector assembly are arranged on the PCBs;

2. A domain controller based on time sensitive network transport as claimed in claim 1, wherein the connector assembly further comprises: the display screen connector is connected with the display screen connecting chip; the camera connector is connected with the camera connecting chip; the chip comprises a first connector and a first connector chip, wherein the first connector is connected with the first connector chip, and the second connector is connected with the second connector chip.

3. A domain controller based on time-sensitive network transmission according to claim 2, characterized in that the first time-sensitive network connector comprises 2 1000base-Tx interfaces, 1 100base-T1 interfaces, 1 100base-Tx interfaces; the second time-sensitive network connector comprises: 4 100base-T1 interfaces and 4 1000base-T1, wherein each interface works independently;

4. The domain controller based on time-sensitive network transmission as claimed in claim 2, wherein the first connector comprises a CAN interface, a LIN interface, the second connector comprises a CAN interface and a LIN interface, the first connector chip comprises a CAN chip and a LIN chip, the second connector comprises a CAN chip and a LIN chip, the CAN interface in the first connector is connected with the CAN chip in the first connector, and the LIN interface in the first connector is connected with the LIN chip in the first connector; the CAN interface in the second connector is connected with a CAN chip of the second connector, and the LIN interface in the second connector is connected with an LIN chip of the second connector;

5. The domain controller based on time-sensitive network transmission of claim 1, wherein the chip assembly further comprises an EMMC chip and a QFIflash, the EMMC chip and the QFIflash being respectively connected to the SOC system-on-chip; the memory includes a plurality of DDRs.

6. The domain controller based on time-sensitive network transmission as claimed in claim 1, wherein the multi-layer PCB board is provided with a plurality of placement areas for placing different chip components, specifically comprising: the CAN-LIN placing area is positioned above the PCB, the power supply placing area is positioned on the left side of the PCB, the MCU placing area is positioned on the right side, the SOC and memory placing area and the camera placing area are positioned on the upper right position, the time-sensitive network switch placing area is positioned on the lower position, and the EMMC and display screen connecting chip placing area is positioned on the lower right position;

7. The domain controller based on time-sensitive network transmission of claim 6, wherein at layer L1, the corresponding power source placing areas are power source wires and ground planes, the corresponding time-sensitive network switch placing areas are high-speed lines and RGMII high-speed signal wires, the reference layer L2 satisfies high-speed signal impedance control, and the rest placing areas are low-speed signal wires and ground planes; at layer L2: the corresponding SOC and memory placement area are used for routing high-speed signals of the memory, and impedance control is met by referring to the L1 layer and the L3 layer.

8. The domain controller based on time-sensitive network transmission of claim 6, wherein at layer L4, corresponding SOC and memory placement areas are high-speed signal traces, and impedance control is satisfied with reference to layer L3 and layer L5; the CSI high-speed signal routing is carried out in a corresponding camera connecting chip placing area, and impedance control is met by referring to the L2 layer and the L5 layer; the corresponding time-sensitive network switch is provided with RGMII high-speed signal wiring in the placement area, the reference L2 layer and the reference L5 layer meet impedance control, and the rest placement areas are low-speed signal wiring and a ground plane.

9. The domain controller based on time-sensitive network transmission of claim 6, wherein at layer L7, corresponding SOC and memory placement areas are high-speed signal traces, and reference layers L6 and L8 satisfy impedance control; the corresponding MCU placing area is provided with CAN \ LIN \ DR \ ADC signal routing;

10. The domain controller based on time-sensitive network transmission of claim 6, wherein at layer L3 is ground plane, layer L5 is power plane and ground plane, layer L6 is power plane and ground plane, layer L9 is part of power and low-speed signal traces, and the rest is ground plane; the L10 layer is the power decoupling capacitor and the remaining peripheral circuit traces.