CN213305377U - Reset circuit based on discrete logic device - Google Patents
Reset circuit based on discrete logic device Download PDFInfo
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- CN213305377U CN213305377U CN202022064734.XU CN202022064734U CN213305377U CN 213305377 U CN213305377 U CN 213305377U CN 202022064734 U CN202022064734 U CN 202022064734U CN 213305377 U CN213305377 U CN 213305377U
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Abstract
A reset circuit based on a discrete logic device is used for resetting an integrated circuit and comprises a control circuit, a first logic circuit and a second logic circuit, wherein the control circuit receives a power-on signal of a power supply voltage and outputs a dog feeding signal; the watchdog circuit is connected with the control circuit, receives the dog feeding signal and outputs a reset signal and an overflow signal; the first logic circuit is connected with the watchdog circuit, receives the overflow signal and outputs an overflow reset signal; the second logic circuit is connected with the first logic circuit and the watchdog circuit, receives the overflow reset signal, and outputs a manual reset signal to the watchdog circuit to indicate the watchdog circuit to output the reset signal; and the buffer circuit is connected with the watchdog circuit and receives a reset signal so as to reset the integrated circuit. By arranging the reset circuit based on the discrete logic device, the problems of complex operation and high cost caused by the fact that the conventional reset method needs self-editing software for burning are solved.
Description
Technical Field
The present application relates to the field of electronic circuit technology, and more particularly, to a reset circuit based on discrete logic devices.
Background
At present, with the rapid development of network data, the transmission rate is faster and faster, the exchange of data capacity is larger and larger, and the requirement on the product performance of an enterprise network or an access network switch is higher, so that the product design complexity is higher, and for a more complex product, a reliable reset circuit is very important for a system. The traditional reset method is mainly realized by a logic circuit with higher integration level, however, the reset method usually needs self-editing software, and the software is burned into a system in the production process, so that the operation is more complex and the production cost is higher.
Therefore, the traditional reset method has the problems of complex operation and high cost due to the fact that self-editing software is needed for burning.
SUMMERY OF THE UTILITY MODEL
The application aims to provide a reset circuit based on a discrete logic device, and aims to solve the problems that the traditional reset method is complex in operation and high in cost due to the fact that self-editing software is needed for burning.
A first aspect of an embodiment of the present application provides a reset circuit based on a discrete logic device, configured to reset an integrated circuit, including:
the control circuit is used for receiving a power-on signal of the power supply voltage and outputting a dog feeding signal;
the watchdog circuit is connected with the control circuit and used for receiving the dog feeding signal, outputting a reset signal when the level signal of the dog feeding signal is a rising edge or a falling edge, and outputting an overflow signal when the level signal of the dog feeding signal is kept unchanged within a preset time range;
the first logic circuit is connected with the watchdog circuit and used for receiving the overflow signal and outputting an overflow reset signal;
the second logic circuit is connected with the first logic circuit and the watchdog circuit and used for receiving the overflow reset signal and outputting a manual reset signal to the watchdog circuit, wherein the manual reset signal indicates the watchdog circuit to output a reset signal;
and the buffer circuit is connected with the watchdog circuit and the integrated circuit and used for receiving the reset signal so as to reset the integrated circuit.
In one embodiment, the method further comprises:
and the trigger circuit is connected with the second logic circuit and used for receiving a trigger signal and outputting a trigger reset signal to the second logic circuit so as to indicate the second logic circuit to output the manual reset signal.
In one embodiment, the control circuit is connected with the second logic circuit;
the control circuit is further configured to output a global reset signal to the second logic circuit to instruct the second logic circuit to output the manual reset signal.
In one embodiment, the second logic circuit is a three-input and gate circuit;
the first input end of the second logic circuit is connected with the first logic circuit, the second input end of the second logic circuit is connected with the trigger circuit, the third input end of the second logic circuit is connected with the control circuit, and the output end of the second logic circuit is connected with the watchdog circuit.
In one embodiment, the control circuit is connected with the first logic circuit;
the control circuit is further configured to output a mask reset signal to the first logic circuit to mask the overflow reset signal output by the first logic circuit.
In one embodiment, the first logic circuit is a two-input or gate circuit;
the first input end of the first logic circuit is connected with the watchdog circuit, the second input end of the first logic circuit is connected with the control circuit, and the output end of the first logic circuit is connected with the second logic circuit.
In one embodiment, the method further comprises:
and the third logic circuit is connected with the watchdog circuit and used for receiving the reset signal so as to reset the integrated circuit.
In one embodiment, the method further comprises:
and the register circuit is connected with the control circuit and the third logic circuit and is used for receiving the single trigger signal sent by the control circuit and outputting a single reset signal to the third logic circuit.
In one embodiment, the third logic circuit is a four-channel and gate circuit.
In one embodiment, the buffer circuit is an 8-channel buffer;
the input end of the buffer circuit is connected with the watchdog circuit, and the output end of the buffer circuit is connected with the integrated circuit.
Compared with the prior art, the embodiment of the utility model beneficial effect who exists is: according to the reset circuit based on the discrete logic device, the control circuit sends the dog feeding signal to the watchdog circuit to realize power-on reset; a trigger circuit sends a trigger reset signal to realize key reset; sending a global reset signal through a control circuit to realize global reset; a single signal is sent through a control circuit, and single reset of a certain integrated circuit is realized; sending a shielding reset signal through a control circuit, shielding the overflow reset signal, and closing the reset function of the overflow signal; according to the scheme, the hardware is used for leading the system reset, the single chip or system global reset is realized, the performance is reliable, and the driving capability is more stable.
Drawings
Fig. 1 is a schematic block diagram illustrating a structure of a reset circuit based on a discrete logic device according to an embodiment of the present application;
fig. 2 is a schematic block diagram illustrating a structure of a reset circuit based on a discrete logic device according to another embodiment of the present application;
fig. 3 is a schematic block diagram of a reset circuit based on a discrete logic device according to another embodiment of the present application.
Detailed Description
In order to make the technical problems, technical solutions and advantageous effects to be solved by the present application clearer, the present application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
It should be noted that the terms "first" and "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.
Referring to fig. 1, a schematic block diagram of a reset circuit based on discrete logic devices according to an embodiment of the present application is shown, for convenience of description, only the relevant portions of the embodiment are shown, and the detailed description is as follows:
in one embodiment, a reset circuit based on discrete logic device for resetting an integrated circuit includes a control circuit 101, a watchdog circuit 102, a first logic circuit 103, a second logic circuit 104, and a buffer circuit 105.
And the control circuit 101 is connected with the power supply and used for outputting the dog feeding signal.
Specifically, the control circuit 101 is implemented by a Micro Controller Unit (MCU), such as a single chip microcomputer; the control circuit 101 is connected with the key 109, the key 109 is pressed, the power supply supplies power supply voltage to the control circuit 101, and the control circuit 101 receives a power-on signal of the power supply voltage, so that the watchdog circuit 102 is sent with a watchdog feeding signal.
The watchdog circuit 102 is connected to the control circuit 101, and is configured to receive the watchdog feeding signal and output a reset signal and an overflow signal.
Specifically, the watchdog circuit 102 is connected to a first serial port pin GPIO1 of the control circuit 101 through a counter input pin WDI; when the dog feeding signal is a rising edge or a falling edge, a RESET output pin RESET of the watchdog circuit 102 outputs a RESET signal to realize power-on RESET of the RESET circuit; when the level signal of the dog feeding signal is kept unchanged within the preset time range, it indicates that the internal software program of the control circuit 101 is running away, and the counter output pin WDO of the watchdog circuit 102 outputs an overflow signal, which is a low level signal.
The first logic circuit 103 is connected to the watchdog circuit 102, and is configured to receive an overflow signal and output an overflow reset signal; and a second logic circuit 104, connected to the first logic circuit 103 and the watchdog circuit 102, for receiving the overflow reset signal and outputting a manual reset signal to the watchdog circuit 102, so that the watchdog circuit 102 outputs the reset signal.
Specifically, the first logic circuit 103 receives a low-level signal of the overflow signal and outputs an overflow RESET signal to the second logic circuit 104, the overflow RESET signal is a low-level signal, the second logic circuit 104 receives the low-level signal of the overflow RESET signal and simultaneously outputs a low-level signal, i.e., a manual RESET signal, and after receiving the manual RESET signal, the manual RESET pin MR _ RESET of the watchdog circuit 102 outputs the RESET signal through the RESET output pin RESET.
And a buffer circuit 105 connected to the watchdog circuit 102 and the integrated circuit for receiving a reset signal to reset the integrated circuit.
Specifically, the buffer circuit 105 is an 8-channel buffer, an input terminal of the buffer circuit 105 is connected to the RESET output pin RESET of the watchdog circuit 102, and receives a RESET signal, an output terminal of the buffer circuit 105 is connected to the integrated circuit, the buffer circuit 105 outputs the RESET signal to the integrated circuit, and RESETs the integrated circuit, and the integrated circuit is generally a chip such as a CPU, an LED, a flash, a PHY, or a MAC.
Referring to fig. 2, a schematic block diagram of a reset circuit based on discrete logic devices according to another embodiment of the present application is shown, for convenience of description, only the relevant portions of the embodiment are shown, and the detailed description is as follows:
in one embodiment, the method further comprises:
the trigger circuit 106 is connected to the second logic circuit 104, and configured to receive the trigger signal and output a trigger reset signal to the second logic circuit 104, so as to instruct the second logic circuit 104 to output the manual reset signal.
Specifically, the trigger circuit 106 is implemented by a trigger, an input end of the trigger circuit 106 is connected to the key 109, the key 109 is pressed to output a rising edge, that is, a trigger signal, the trigger circuit 106 receives the rising edge of the trigger signal and outputs a low-level signal with a certain width, that is, a trigger RESET signal, the second logic circuit 104 receives the low-level signal of the trigger RESET signal and outputs a low-level signal, that is, a manual RESET signal, and after receiving the manual RESET signal, the manual RESET pin MR _ RESET of the watchdog circuit 102 outputs the RESET signal through the RESET output pin RESET to RESET the integrated circuit, thereby implementing the key RESET of the RESET circuit; the trigger circuit 106 has the functions of waveform restoration, debouncing and output pulse width adjustment, and greatly enhances the reliability of the key input signal.
In one embodiment, the control circuit 101 is connected to the second logic circuit 104; the control circuit 101 outputs a global reset signal to the second logic circuit 104 to instruct the second logic circuit 104 to output a manual reset signal.
Specifically, the control circuit 101 outputs a low level signal, that is, a global RESET signal, through the second serial port pin GPIO2, the second logic circuit 104 receives the low level signal of the global RESET signal and outputs a low level signal, that is, a manual RESET signal, and after receiving the manual RESET signal, the manual RESET pin MR _ RESET of the watchdog circuit 102 outputs the RESET signal through the RESET output pin RESET to RESET the integrated circuit, thereby implementing the global RESET of the RESET circuit.
In one embodiment, the second logic circuit 104 is a three-input and gate circuit.
The first input terminal of the second logic circuit 104 is connected to the first logic circuit 103, the second input terminal of the second logic circuit 104 is connected to the generating circuit 106, the third input terminal of the second logic circuit 104 is connected to the control circuit 101, and the output terminal of the second logic circuit 104 is connected to the watchdog circuit 102.
Specifically, a first input terminal of the second logic circuit 104 receives the overflow reset signal sent by the first logic circuit 103, a second input terminal of the second logic circuit 104 receives the trigger reset signal of the trigger circuit 106, a third input terminal of the second logic circuit 104 receives the global reset signal of the control circuit 101, when any input terminal of the second logic circuit 104 receives a low level signal, an output terminal of the second logic circuit 104 outputs a low level signal, and at this time, the watchdog circuit 102 outputs a reset signal.
In one embodiment, the control circuit 101 is connected to the first logic circuit 103.
The control circuit 101 outputs a mask reset signal to the first logic circuit 103 to mask the overflow reset signal output by the first logic circuit 103; the first logic circuit 103 is a two-input or gate circuit, a first input terminal of the first logic circuit 103 is connected to the watchdog circuit 102, a second input terminal of the first logic circuit 103 is connected to the control circuit 101, and an output terminal of the first logic circuit 103 is connected to the second logic circuit 104.
Specifically, a first input terminal of the first logic circuit 103 receives an overflow signal of the watchdog circuit 102, and a second input terminal of the first logic circuit 103 receives a mask reset signal of the control circuit 101; when the system needs to close the watchdog function at the moment of power-on or the system tests to close the watchdog function, the control circuit 101 outputs a high-level signal through the third serial port pin GPIO3, namely, the reset signal is shielded, the first logic circuit 103 receives the high-level signal of the reset signal, at this time, the first logic circuit 103 outputs the high-level signal to the first input end of the second logic circuit 104, and no matter whether the watchdog overflows or not, the first logic circuit 103 outputs the high level, so that the overflow reset signal is shielded.
Referring to fig. 3, a schematic block diagram of a reset circuit based on discrete logic devices according to still another embodiment of the present application is provided, in which for convenience of description, only the relevant portions of the embodiment are shown, and the detailed description is as follows:
in one embodiment, the method further comprises:
a third logic circuit 107 is coupled to the watchdog circuit 102 for receiving a reset signal to reset the integrated circuit.
Specifically, the third logic circuit 107 is a four-channel and gate circuit, an input terminal of the third logic circuit 107 is connected to the RESET output pin RESET of the watchdog circuit 102, and receives a RESET signal, an output terminal of the third logic circuit 107 is connected to the integrated circuit, the third logic circuit 107 outputs the RESET signal to the integrated circuit to RESET the integrated circuit, and the third logic circuit 107 realizes output and function of the RESET signal and also plays a role in enhancing driving.
In one embodiment, the method further comprises:
the register circuit 108 is connected to the control circuit 101 and the third logic circuit 107, and is configured to receive a single trigger signal from the control circuit 101 and output a single reset signal to the third logic circuit 107.
Specifically, the register circuit 108 employs an I/O extension register, the number of bits of the register circuit 108 may be 8 bits, 16 bits or more, and is determined according to the reset requirement of the product design, the register circuit 108 includes an I2C interface, the register circuit 108 is connected to the I2C interface of the control circuit 101 through an I2C interface, the register circuit 108 may further provide a general-purpose remote I/O extension for most microcontrollers through an I2C interface, and the I/O can be enabled to output a low level or a high level by writing an I/O configuration bit.
The third logic circuit 107 comprises 5 input terminals and 4 output terminals, a fifth input terminal of the third logic circuit 107 is connected to the watchdog circuit 102 and receives the reset signal, and a first input terminal, a second input terminal, a third input terminal and a fourth input terminal of the third logic circuit 107 are connected to the register circuit 108 and are configured to receive a single reset signal; the first input terminal, the second input terminal, the third input terminal, and the fourth input terminal of the third logic circuit 107 respectively implement a logic and function with the fifth input terminal, and the first output terminal, the second output terminal, the third output terminal, and the fourth output terminal of the third logic circuit 107 respectively output a logic and result of the first input terminal, the second input terminal, the third input terminal, and the fourth input terminal.
When the reset function of a certain chip needs to be implemented independently, the control circuit 101 outputs a single trigger signal of the certain chip to the register circuit 108, modifies a register value corresponding to the chip, and outputs a low-level signal, i.e., a single reset signal, to a corresponding serial port, where a corresponding input terminal of the third logic circuit 107 receives the single reset signal and resets the chip through a corresponding output terminal.
With reference to fig. 1 to fig. 3, the reset circuit based on discrete logic device can implement the following reset function:
a power-on reset function: the control circuit 101 receives a power-on signal of the power supply voltage, the control circuit 101 outputs a dog feeding signal to the watchdog circuit 102, and the watchdog circuit 102 outputs a reset signal to the buffer circuit 105 and the third logic circuit 107 to reset the integrated circuit, so as to implement power-on reset.
The key reset function: when the key 109 is pressed, the trigger circuit 106 receives the trigger signal, the trigger circuit 106 sends a manual reset signal to the watchdog circuit 102 through the second logic circuit 104, and at this time, the watchdog circuit 102 outputs the reset signal to the buffer circuit 105 and the third logic circuit 107 to reset the integrated circuit, thereby realizing the key reset.
Global reset function: the control circuit 101 outputs a global reset signal to the second logic circuit 104, the second logic circuit 104 sends a manual reset signal to the watchdog circuit 102, and at this time, the watchdog circuit 102 outputs a reset signal to the buffer circuit 105 and the third logic circuit 107 to reset the integrated circuit, thereby realizing global reset.
Single reset function: the control circuit 101 outputs a single trigger signal to the register circuit 108, the register circuit 108 sends a single reset signal to the third logic circuit 107, and the third logic circuit 107 resets the corresponding chip through the corresponding output terminal, so that a single reset function is realized.
Overflow reset function: when the internal software program of the control circuit 101 runs off, the watchdog circuit 102 receives the overflow reset signal through the first logic circuit 103, and at this time, the watchdog circuit 102 outputs the reset signal to the buffer circuit 105 and the third logic circuit 107 to reset the integrated circuit, thereby realizing overflow reset.
Closing the overflow reset function: when the system needs to close the watchdog function at the moment of power-on or the system tests the watchdog function to be closed, the control circuit 101 sends a shielding reset signal to the first logic circuit 103, and at the moment, the first logic circuit 103 outputs the shielding reset signal to the first input end of the second logic circuit 104, so that the overflow reset signal is shielded.
In summary, the reset circuit based on the discrete logic device provided by the present application sends a dog feeding signal to the watchdog circuit 102 through the control circuit 101, so as to implement power-on reset; a trigger circuit 106 sends a trigger reset signal to reset the key; sending a global reset signal through the control circuit 101 to realize global reset; a single signal is sent through the control circuit 101 to realize single reset of a certain integrated circuit; the control circuit 101 sends a shielding reset signal to shield the overflow reset signal, so that the reset function of the overflow signal is closed; according to the scheme, the hardware is used for leading the system reset, the single chip or system global reset is realized, the performance is reliable, and the driving capability is more stable.
Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.
The above-mentioned embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present application and are intended to be included within the scope of the present application.
Claims (10)
1. A discrete logic device based reset circuit for resetting an integrated circuit, comprising:
the control circuit is used for receiving a power-on signal of the power supply voltage and outputting a dog feeding signal;
the watchdog circuit is connected with the control circuit and used for receiving the dog feeding signal, outputting a reset signal when the level signal of the dog feeding signal is a rising edge or a falling edge, and outputting an overflow signal when the level signal of the dog feeding signal is kept unchanged within a preset time range;
the first logic circuit is connected with the watchdog circuit and used for receiving the overflow signal and outputting an overflow reset signal;
the second logic circuit is connected with the first logic circuit and the watchdog circuit and used for receiving the overflow reset signal and outputting a manual reset signal to the watchdog circuit, wherein the manual reset signal is used for indicating the watchdog circuit to output a reset signal;
and the buffer circuit is connected with the watchdog circuit and the integrated circuit and used for receiving the reset signal so as to reset the integrated circuit.
2. The discrete logic device-based reset circuit of claim 1, further comprising:
and the trigger circuit is connected with the second logic circuit and used for receiving a trigger signal and outputting a trigger reset signal to the second logic circuit so as to indicate the second logic circuit to output the manual reset signal.
3. The discrete logic device based reset circuit of claim 2, wherein the control circuit is connected to the second logic circuit;
the control circuit is further configured to output a global reset signal to the second logic circuit to instruct the second logic circuit to output the manual reset signal.
4. The discrete logic device based reset circuit of claim 3, wherein the second logic circuit is a three-input AND gate circuit;
the first input end of the second logic circuit is connected with the first logic circuit, the second input end of the second logic circuit is connected with the trigger circuit, the third input end of the second logic circuit is connected with the control circuit, and the output end of the second logic circuit is connected with the watchdog circuit.
5. The discrete logic device based reset circuit of claim 1, wherein the control circuit is coupled to the first logic circuit;
the control circuit is further configured to output a mask reset signal to the first logic circuit to mask the overflow reset signal output by the first logic circuit.
6. The discrete logic device based reset circuit of claim 5, wherein the first logic circuit is a two input or gate circuit;
the first input end of the first logic circuit is connected with the watchdog circuit, the second input end of the first logic circuit is connected with the control circuit, and the output end of the first logic circuit is connected with the second logic circuit.
7. The discrete logic device-based reset circuit of claim 1, further comprising:
and the third logic circuit is connected with the watchdog circuit and used for receiving the reset signal so as to reset the integrated circuit.
8. The discrete logic device-based reset circuit of claim 7, further comprising:
and the register circuit is connected with the control circuit and the third logic circuit and is used for receiving the single trigger signal sent by the control circuit and outputting a single reset signal to the third logic circuit.
9. The discrete logic device based reset circuit of claim 7, wherein the third logic circuit is a four-channel AND gate circuit.
10. The discrete logic device-based reset circuit of claim 1, wherein the buffer circuit is an 8-channel buffer;
the input end of the buffer circuit is connected with the watchdog circuit, and the output end of the buffer circuit is connected with the integrated circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202022064734.XU CN213305377U (en) | 2020-09-18 | 2020-09-18 | Reset circuit based on discrete logic device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202022064734.XU CN213305377U (en) | 2020-09-18 | 2020-09-18 | Reset circuit based on discrete logic device |
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| Publication Number | Publication Date |
|---|---|
| CN213305377U true CN213305377U (en) | 2021-05-28 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202022064734.XU Active CN213305377U (en) | 2020-09-18 | 2020-09-18 | Reset circuit based on discrete logic device |
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| CN (1) | CN213305377U (en) |
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