CN213277404U - Novel LCOS display chip - Google Patents
Novel LCOS display chip Download PDFInfo
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- CN213277404U CN213277404U CN202120799436.7U CN202120799436U CN213277404U CN 213277404 U CN213277404 U CN 213277404U CN 202120799436 U CN202120799436 U CN 202120799436U CN 213277404 U CN213277404 U CN 213277404U
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Abstract
The utility model discloses a novel LCOS display chip, it includes signal reception module, ranks drive module, voltage conversion module and pixel array, external equipment is connected to signal reception module's input, the input of ranks drive module and voltage conversion module is connected respectively to signal reception module's output, the one end of pixel array is connected respectively through row drive circuit and row drive circuit to ranks drive module's output, the other end of pixel array is connected respectively through common electrode to voltage conversion module's output; the voltage conversion module comprises a DC-DC converter, a level converter and a driving circuit. The utility model discloses can produce the voltage or the negative voltage that are higher than chip power supply voltage value under the low supply voltage power supply condition, reduce the chip consumption when guaranteeing chip display effect.
Description
Technical Field
The utility model relates to a novel LCOS display chip belongs to display chip technical field.
Background
With the continuous development of microdisplay products such as AR and projection products, people pay more and more attention to the performance of microdisplay chips. The LCOS chip is a micro display chip, and when the LCOS chip is powered by a low power voltage, the display effect is poor, the display brightness is insufficient, and the power consumption of the chip is large, so that the display requirement cannot be met. In order to improve the display brightness of the LCOS display chip and reduce the power consumption of the chip, the structure of the existing LCOS display chip needs to be improved.
SUMMERY OF THE UTILITY MODEL
In order to improve LCOS display chip's demonstration luminance and reduce the consumption of chip, the utility model provides a novel LCOS display chip increases voltage conversion module on current LCOS display chip's basis, can adjust output voltage according to input signal, and then quick, accurate regulation display chip's demonstration luminance.
In order to solve the technical problem, the utility model discloses a following technical means:
the utility model provides a novel LCOS display chip, including signal reception module, ranks drive module, voltage conversion module and pixel array, signal reception module's input passes through high-speed interface connection external equipment, and signal reception module's output is connected respectively the one end of pixel array is connected respectively through line drive circuit and row drive circuit to ranks drive module's output, and pixel array's the other end is connected respectively through common electrode to voltage conversion module's output.
Further, the voltage conversion module comprises a DC-DC converter, a level converter and a driving circuit; the input end of the DC-DC converter is connected with an external power supply, the output end of the DC-DC converter and the output end of the signal receiving module are respectively connected with the input end of the level converter, the output end of the level converter is connected with the input end of the driving circuit, and the output end of the driving circuit is connected with the common electrode.
Further, the DC-DC converter includes a first MOS transistor, a PWM circuit, a second MOS transistor, a third MOS transistor, a first inductor, a fourth MOS transistor, a first resistor, a second resistor, a first capacitor, and a second capacitor; wherein, the D pole of the first MOS tube is connected with an external power supply, the G pole of the first MOS tube is connected with S1 of the PWM circuit, the S1 of the PWM circuit is sequentially connected with the G poles of the first MOS tube and the second MOS tube, the S2 of the PWM circuit is sequentially connected with the G poles of the third MOS tube and the fourth MOS tube, the S pole of the first MOS tube is respectively connected with one end of a first inductor and the D pole of the second MOS tube, the other end of the first inductor is respectively connected with the D pole of the third MOS tube and the D pole of the fourth MOS tube, the S pole of the third MOS tube is grounded, the RFB of the PWM circuit is respectively connected with one end of a first resistor and one end of a second resistor, the S pole of the second MOS tube is connected with the other end of a second resistor, and outputs a low voltage signal, the S pole of the fourth MOS transistor is connected with the other end of the first resistor and outputs a high voltage signal, and the first capacitor and the second capacitor are connected in series and then connected in parallel between the other end of the first resistor and the other end of the second resistor.
Further, the driving circuit comprises a fifth MOS transistor, a sixth MOS transistor, a seventh MOS transistor and an eighth MOS transistor; the G pole of the fifth MOS tube and the G pole of the seventh MOS tube are respectively connected with the output end of the level shifter, the D pole of the fifth MOS tube and the D pole of the seventh MOS tube are connected in series and then are respectively connected with the G pole of the sixth MOS tube and the G pole of the eighth MOS tube, the S pole of the fifth MOS tube is connected with the S pole of the sixth MOS tube, the S pole of the seventh MOS tube is connected with the S pole of the eighth MOS tube, and the D pole of the sixth MOS tube and the D pole of the eighth MOS tube are connected in series and then are connected with the common electrode.
Further, the signal receiving module comprises a high-speed interface, a digital-to-analog converter and I2And the high-speed interface adopts a lvds interface or a mipi interface.
Furthermore, the row-column driving module comprises a gating circuit, a levelshift circuit, a row driving circuit, a shift register, a buffer circuit and a column driving circuit.
Further, the common electrode is a semitransparent conductive electrode.
The following advantages can be obtained by adopting the technical means:
the utility model provides a novel LCOS display chip utilizes signal reception module to connect external equipment, acquires external control signal to external control signal converts, the utility model discloses the chip utilizes ranks drive module and voltage conversion module to provide drive signal and voltage signal for pixel array respectively, and then utilizes pixel array cooperation light emitting component to realize showing the function. The voltage conversion module in the utility model comprises a DC-DC converter and a level converter, a PWM circuit in the DC-DC converter can adjust the voltage by changing the duty ratio, ensure that the voltage or the negative voltage which is higher than the voltage value of a chip power supply is generated under the condition of low power supply voltage power supply, and improve the pressure difference between the high level and the low level of a micro display chip, thereby improving the brightness and the gray scale of the micro display chip; the level shifter can output different levels to meet different display requirements. The utility model discloses display chip passes through the input voltage that voltage conversion module changed the pixel cell, and change chip that can be quick, accurate shows luminance, reduces the chip consumption when guaranteeing chip display effect.
Drawings
Fig. 1 is a schematic structural diagram of a novel LCOS chip of the present invention;
fig. 2 is a schematic structural diagram of a row driver sub-module according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a column driver sub-module according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of a voltage conversion module according to an embodiment of the present invention;
fig. 5 is a schematic diagram of the input signal of the common electrode and the output signal of the voltage conversion module in the embodiment of the present invention;
fig. 6 is a schematic circuit diagram of a DC-DC converter according to an embodiment of the present invention;
fig. 7 is a schematic circuit diagram of a driving circuit according to an embodiment of the present invention;
in the figure, 1 is a signal receiving module, 2 is a row and column driving module, 3 is a voltage converting module, 4 is a pixel array, and 5 is a common electrode.
Detailed Description
The technical scheme of the utility model is further explained by combining the attached drawings as follows:
the utility model provides a novel LCOS shows chip, as shown in fig. 1, mainly include signal reception module 1, ranks drive module 2, voltage conversion module 3 and pixel array 4, including a plurality of pixel units in the pixel array, the pixel array is arranged on the chip bottom plate. The input end of the signal receiving module is connected with external equipment through a high-speed interface, the output end of the signal receiving module is respectively connected with the input ends of the row-column driving module and the voltage conversion module, the output end of the row-column driving module is respectively connected with one end of the pixel array through a row driving circuit and a column driving circuit, and the output end of the voltage conversion module is respectively connected with the other end of the pixel array through a common electrode 5.
The utility model discloses in the display chip, signal reception module mainly used receives the control signal of external equipment (if show driver chip a little) output to carry out processing such as digital analog conversion, level conversion to control signal, obtain distinguishable height level signal. The signal receiving module comprises a high-speed interface, a digital-to-analog converter and I2C circuit, etc., wherein the high-speed interface for connecting the signal receiving module and the external device can adopt a lvds interface, a mipi interface or other structures with high-speed data transmission function.
The high-low level signal output by the signal receiving module can be divided into a high-low level signal for driving and a high-low level signal for conversion according to different transmission directions. The high-low level signals for driving are transmitted to the row-column driving module through the lines, and the high-low level signals for conversion are transmitted to the voltage conversion module through the lines.
The row-column driving module can be further divided into a row driving submodule and a column driving submodule, and the structure of the row-column driving submodule is shown in fig. 2 and 3, the row driving submodule comprises a gating circuit, a levelshift circuit and a row driving circuit, wherein the gating circuit is an address gating circuit, and the row driving circuit is connected with the pixel units of each row in the pixel array on the chip bottom plate in a row unit; the column driving submodule comprises a shift register, a buffer circuit, a levelshift circuit and a column driving circuit, wherein the column driving circuit is connected with the pixel units of each column in the pixel array on the chip bottom plate in a column unit mode. After high and low level signals for driving are input into the row and column driving modules, the row and column driving sub-modules output voltages to one or more pixel units through electrical elements such as a selection switch, a booster and the like, and then the pixel units are driven to work.
The voltage conversion module can adjust and output voltage according to the high-low level signal for conversion, and when the signal receiving module outputs the high-level signal, the voltage conversion module performs voltage conversion operation based on an external power supply. In the embodiment of the present invention, as shown in fig. 4, the voltage conversion module includes a DC-DC converter, a level shifter and a driving circuit, wherein an input terminal of the DC-DC converter is connected to an external power source, an output terminal of the DC-DC converter and one end of the signal receiving module are respectively connected to a power source and a ground of the level shifter and the driving circuit, an output terminal of the level shifter is connected to an input terminal of the driving circuit, and an output terminal of the driving circuit is connected to the common electrode. When the voltage conversion module receives a high-level signal, the DC-DC converter is used for generating a direct-current voltage higher than a power supply voltage or a direct-current voltage lower than zero by using the voltage of an external power supply, the level converter performs level conversion on the high-level signal according to a common electrode input signal VCOM output by the signal receiving module to obtain a common electrode input signal which outputs the direct-current voltage with the high level higher than the power supply voltage and the direct-current voltage with the low level lower than zero, and the driving circuit inputs the converted common electrode input signal into a common electrode to supply power to the common electrode and the pixel unit; the common electrode input signal and the voltage conversion module output signal are shown in fig. 5.
As shown in fig. 6, the DC-DC converter includes a first MOS transistor M1, a PWM circuit, a second MOS transistor M2, a third MOS transistor M3, a first inductor L, a fourth MOS transistor M4, a first resistor R1, a second resistor R2, a first capacitor C1, and a second capacitor C2; wherein, the D pole of the first MOS transistor M1 is connected with an external power VIN, the G pole of the first MOS transistor M1 is connected with the S1 of the PWM circuit, namely, the power input end, the S1 of the PWM circuit is sequentially connected with the G poles of the first MOS tube and the second MOS tube, the S2 of the PWM circuit is sequentially connected with the G poles of the third MOS tube and the fourth MOS tube, the S pole of the first MOS tube M1 is respectively connected with one end of a first inductor L and the D pole of the second MOS tube M2, the other end of the first inductor L is respectively connected with the D pole of the third MOS tube M3 and the D pole of the fourth MOS tube M4, the S pole of the third MOS tube M3 is grounded, the RFB of the PWM circuit is respectively connected with one end of a first resistor and one end of a second resistor, the S pole of the second MOS tube M2 is connected with the other end of a second resistor R2, and outputs a low voltage signal VON, the S-pole of the fourth MOS transistor M4 is connected to the other end of the first resistor R1, and outputs a high voltage signal VOP, and the first capacitor C1 and the second capacitor C2 are connected in series and then connected in parallel between the other end of the first resistor R1 and the other end of the second resistor R2. Generally, M1 and M4 are P-type MOS tubes, and M2 and M3 are N-type MOS tubes; l, R1, R2 and C1, C2 are all off-chip elements.
When no external signal is input into the display chip, the DC-DC converter does not work, the PWM circuit enables the MOS tubes M1-M4 to be closed, when the DC-DC converter works, the switching time of the MOS tubes M1-M4 can be adjusted through the feedback voltage R _ FB between R1 and R2, and the voltage value of the output voltage of the DC-DC converter is changed. Specifically, when the DC-DC converter works, the PWM circuit may control M1 and M3 to be turned on by a pulse signal, M2 and M4 to be turned off, and the external power source VIN charges the first inductor L; after the inductor is charged, the PWM circuit can be controlled by the pulse signal to turn off M1 and M3, and at the same time, M2 and M4 are turned on, the first inductor L discharges to the load, and at this time, VOP can obtain a voltage VDDH higher than the power voltage, and VON can obtain a voltage VDDL lower than zero.
As shown in fig. 7, the driving circuit includes a fifth MOS transistor M5, a sixth MOS transistor M6, a seventh MOS transistor M7, and an eighth MOS transistor M8; the G pole of the fifth MOS transistor M5 and the G pole of the seventh MOS transistor M7 are respectively connected to the output end of the level shifter, the D pole of the fifth MOS transistor M5 and the D pole of the seventh MOS transistor M7 are connected in series and then are respectively connected to the G pole of the sixth MOS transistor M6 and the G pole of the eighth MOS transistor M8, the S pole of the fifth MOS transistor M5 is connected to the S pole of the sixth MOS transistor M6, the S pole of the seventh MOS transistor M7 is connected to the S pole of the eighth MOS transistor M8, and the D pole of the sixth MOS transistor M6 and the D pole of the eighth MOS transistor M8 are connected in series and then are connected to the common electrode. MOS tubes M5 and M6 are P-type MOS tubes, and MOS tubes M7 and M8 are N-type MOS tubes.
The utility model discloses the switching frequency of DC-DC converter can be adjusted according to DC-DC converter output feedback voltage R _ FB's size to the voltage conversion module of display chip, and then stabilizes the output voltage of DC-DC converter, can also change output voltage VOP and VON's size through changing feedback resistance R1, R2. The voltage conversion module can generate voltage or negative voltage higher than the voltage value of the chip power supply, and the voltage conversion module can improve the pressure difference between the high level and the low level of the micro display chip under the condition of low power supply voltage power supply, so that the brightness and the gray scale of the micro display chip are improved, and the power consumption of the chip is reduced while the display effect of the chip is ensured.
The embodiment of the utility model provides an in, the pixel unit still includes pixel electrode and pixel circuit, and the pixel electrode is connected with ranks drive module and common electrode electricity, and pixel circuit is used for connecting outside light emitting component, and when there is voltage signal input in the pixel electrode, pixel circuit can give outside light emitting component with voltage signal transmission, and then control light emitting component work, can control outside light emitting component's luminance according to input voltage size pixel unit.
The common electrode is a common terminal electrode connected with the other ends of all the pixel units in the pixel array, and the common electrode is a semitransparent conductive electrode and comprises ITO (indium tin oxide), a semitransparent metal simple substance, a semitransparent metal compound or other semitransparent conductive materials.
The utility model discloses can produce the voltage or the negative voltage that are higher than chip power supply voltage value under the low supply voltage power supply condition, change chip display brightness, and then reduce the chip consumption when guaranteeing chip display effect.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, a plurality of modifications and variations can be made without departing from the technical principle of the present invention, and these modifications and variations should also be considered as the protection scope of the present invention.
Claims (7)
1. The utility model provides a novel LCOS display chip, its characterized in that, includes signal reception module, ranks drive module, voltage conversion module and pixel array, signal reception module's input passes through high-speed interface connection peripheral equipment, and signal reception module's output is connected respectively rank drive module and voltage conversion module's input, rank drive module's output passes through row drive circuit and the one end of being connected the pixel array respectively of being listed as drive circuit, and the other end of pixel array is connected respectively through common electrode to voltage conversion module's output.
2. The novel LCOS display chip of claim 1, wherein said voltage conversion module comprises a DC-DC converter, a level shifter and a driving circuit; the input end of the DC-DC converter is connected with an external power supply, the output end of the DC-DC converter and the output end of the signal receiving module are respectively connected with the input end of the level converter, the output end of the level converter is connected with the input end of the driving circuit, and the output end of the driving circuit is connected with the common electrode.
3. The novel LCOS display chip of claim 2, wherein the DC-DC converter comprises a first MOS transistor, a PWM circuit, a second MOS transistor, a third MOS transistor, a first inductor, a fourth MOS transistor, a first resistor, a second resistor, a first capacitor and a second capacitor; wherein, the D pole of the first MOS tube is connected with an external power supply, the G pole of the first MOS tube is connected with S1 of the PWM circuit, the S1 of the PWM circuit is sequentially connected with the G poles of the first MOS tube and the second MOS tube, the S2 of the PWM circuit is sequentially connected with the G poles of the third MOS tube and the fourth MOS tube, the S pole of the first MOS tube is respectively connected with one end of a first inductor and the D pole of the second MOS tube, the other end of the first inductor is respectively connected with the D pole of the third MOS tube and the D pole of the fourth MOS tube, the S pole of the third MOS tube is grounded, the RFB of the PWM circuit is respectively connected with one end of a first resistor and one end of a second resistor, the S pole of the second MOS tube is connected with the other end of a second resistor, and outputs a low voltage signal, the S pole of the fourth MOS transistor is connected with the other end of the first resistor and outputs a high voltage signal, and the first capacitor and the second capacitor are connected in series and then connected in parallel between the other end of the first resistor and the other end of the second resistor.
4. The novel LCOS display chip of claim 2, wherein the driving circuit comprises a fifth MOS transistor, a sixth MOS transistor, a seventh MOS transistor and an eighth MOS transistor; the G pole of the fifth MOS tube and the G pole of the seventh MOS tube are respectively connected with the output end of the level shifter, the D pole of the fifth MOS tube and the D pole of the seventh MOS tube are connected in series and then are respectively connected with the G pole of the sixth MOS tube and the G pole of the eighth MOS tube, the S pole of the fifth MOS tube is connected with the S pole of the sixth MOS tube, the S pole of the seventh MOS tube is connected with the S pole of the eighth MOS tube, and the D pole of the sixth MOS tube and the D pole of the eighth MOS tube are connected in series and then are connected with the common electrode.
5. The LCOS display chip of claim 1, wherein the signal receiving module comprises a high speed interface, a digital-to-analog converter and I2And the high-speed interface adopts a lvds interface or a mipi interface.
6. The LCOS display chip of claim 1, wherein the row/column driving module comprises a gate circuit, a levelshift circuit, a row driving circuit, a shift register, a buffer circuit and a column driving circuit.
7. A novel LCOS display chip as claimed in claim 1 or 4 wherein the common electrode is a semi-transparent conducting electrode.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202120799436.7U CN213277404U (en) | 2021-04-19 | 2021-04-19 | Novel LCOS display chip |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202120799436.7U CN213277404U (en) | 2021-04-19 | 2021-04-19 | Novel LCOS display chip |
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| CN213277404U true CN213277404U (en) | 2021-05-25 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113725970A (en) * | 2021-08-30 | 2021-11-30 | 安徽华米信息科技有限公司 | Power supply method and device for wearable equipment and storage medium |
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- 2021-04-19 CN CN202120799436.7U patent/CN213277404U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113725970A (en) * | 2021-08-30 | 2021-11-30 | 安徽华米信息科技有限公司 | Power supply method and device for wearable equipment and storage medium |
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