CN213276522U

CN213276522U - Server mainboard and one-way server

Info

Publication number: CN213276522U
Application number: CN202022769602.7U
Authority: CN
Inventors: 孙瑛琪; 杨晓君; 柳胜杰; 李书通; 李晶晶
Original assignee: Chengdu Haiguang Integrated Circuit Design Co Ltd
Current assignee: Chengdu Haiguang Integrated Circuit Design Co Ltd
Priority date: 2020-11-25
Filing date: 2020-11-25
Publication date: 2021-05-25
Anticipated expiration: 2030-11-25

Abstract

The utility model provides a server mainboard and one-way server. The server mainboard is provided with a processor CPU chip and a baseboard management controller BMC chip, the BMC chip is used for controlling the CPU chip, the CPU chip is provided with a plurality of groups of high-speed interfaces with 16 channels, and the high-speed interfaces with 16 channels are configured into a composite interface supporting a plurality of transmission protocols. The utility model discloses a server mainboard can realize the nimble configuration of mainboard interface function.

Description

Server mainboard and one-way server

Technical Field

The utility model relates to a computer technology field especially relates to a server mainboard and one way server.

Background

The mainboard is the core of the server, and the performance of the mainboard directly determines the computing power of the server, so that it is important to select a CPU with excellent performance for the mainboard. The sea light CPU has wide application in the server mainboard.

With the technical development of the CPU chip design, more and more IO and the like are integrated on a single CPU chip, and the integration level of the server motherboard is higher and higher. Therefore, higher requirements are also put forward on the IO interface configuration of the CPU so as to realize the flexibility of the interface function of the mainboard.

SUMMERY OF THE UTILITY MODEL

In view of this, the utility model provides a server mainboard and one-way server can realize the nimble configuration of mainboard interface function.

In a first aspect, the present invention provides a server motherboard, be equipped with treater CPU chip and baseboard management controller BMC chip on the server motherboard, the BMC chip is used for right the CPU chip is controlled, wherein, the CPU chip has the high-speed interface of 16 routes of multiunit, and wherein the high-speed interface of 16 routes of a set of is configured to the composite interface that supports multiple transmission protocol.

Optionally, the high-speed interface of one of the 16-way sets is configured as a composite interface as follows:

the [0:3] path is configured to support a first sub-interface of SATA4 x;

the [4:7] lane is configured to support a second subinterface of XGBE 4 x;

the [8:11] lane is configured to support a third subinterface of PCIe x 4;

[12] the lane is configured to support a fourth subinterface of PCIe x 1;

[13] the lane is configured to support a fifth subinterface of PCIe x 1;

the [14:15] lane is configured to support the sixth subinterface of PCIe x 2.

Optionally, the first sub-interface is connected to 4 SATA connectors;

the second sub-interface is connected to 4 SFP + connectors;

the third sub-interface is connected to a gigabit network chip;

the fourth sub-interface is connected to the BMC chip;

the fifth sub-interface is connected to a first M.2 connector;

the sixth sub-interface is connected to a second m.2 connector.

Optionally, the gigabit network chip is I350, with a 2-way gigabit electrical port network.

Optionally, the other high-speed interfaces except the high-speed interface configured as the composite interface are configured as interfaces supporting PCIe x16, and are respectively connected to PCIe x16 slots.

Optionally, the CPU chip further includes a plurality of memory channels, and each memory channel is connected to 2 DIMM slots.

Optionally, the CPU chip is connected to a plurality of USB interfaces.

Optionally, the BMC chip is connected to the CPU chip through an LPC bus, a USB bus, and an SPI bus.

Optionally, the BMC chip is connected to a gigabit PHY chip, which is connected to a gigabit RJ45 interface for connecting a remote management platform through the gigabit RJ45 interface.

In a second aspect, the present invention provides a one-way server, including the above server motherboard.

The utility model provides a server mainboard and one-way server, the CPU chip on the mainboard have the high-speed interface in 16 passageways of multiunit, and wherein the high-speed interface in a set of 16 passageways is configured into the compound interface that supports multiple transmission protocol, for example this compound interface supports agreement such as SATA, PCIe, XGBE simultaneously, has realized the nimble configuration of mainboard interface.

Drawings

Fig. 1 is a schematic diagram of a connection relationship between partial interfaces of a CPU on a server motherboard according to an embodiment of the present invention;

fig. 2 is a schematic diagram of a connection relationship between partial interfaces of a CPU on a server motherboard according to an embodiment of the present invention;

fig. 3 is a schematic view of a connection relationship between a CPU and a BMC on a server motherboard according to an embodiment of the present invention;

fig. 4 is a schematic diagram of an overall structure of a server motherboard according to an embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.

An embodiment of the utility model provides a server motherboard is equipped with treater (CPU) chip and base plate Management Controller (BMC) chip on the server motherboard, and the CPU chip adopts Socket mounting means to install on the server motherboard.

The CPU chip has a plurality of sets of 16-lane high-speed interfaces, wherein a set of 16-lane high-speed interfaces is configured as a composite interface supporting multiple transport protocols. Because the interface can be joined in marriage, this compound interface can be with partial PCIe signal configuration into SATA signal, can insert the adapter card (PCIe gold finger directly links SATA connector) outside through the PCIe slot like this, expands SATA interface quantity.

Taking the CPU of haguang No. 3 as an example, as shown in fig. 1, the CPU chip has 8 groups of high-speed interfaces with 16 lanes, which are denoted as P0-P7, where P0 is split and used on the motherboard design, and is respectively used as PCIe, SATA and XGBE interfaces, and P1-P7 are used as PCIe interfaces. The BIOS software also needs to be configured to the corresponding interface protocol.

Specifically, the high-speed interface P0 is configured as defined below:

p0[0:3] is configured to support a first sub-interface of SATA4x, which connects to 4 SATA connectors that can interface with standard SATA disks.

P0[4:7] is configured to support a second sub-interface of XGBE 4x, which is connected to 4 SFP + connectors and can support 1G, 10G optical port connections.

P0[8:11] is configured to support a third subinterface of PCIe x4 connected to a gigabit network chip, such as an I350 AM2 network chip, supporting a 2 gigabit RJ45 interface. The BMC is also connected to the I350 AM2 through the NCSI, and the gigabit network of the CPU is shared, so that the management BMC can be accessed through the RJ45 connected to the I350 AM 2.

P0[12] is configured to support a fourth subinterface of PCIe x1, which is connected to the BMC chip.

P0[13] is configured to support a fifth subinterface of PCIe x1, which connects to the first M.2 connector; p0[14:15] is configured to support a sixth subinterface of PCIe x2, which is connected to a second M.2 connector, 2 M.2 connectors supporting 2 M.2 storage disks.

The 7 groups of high-speed interfaces P1-P7 are respectively connected with 1 PCIe4.0 x16 Slot (recorded as PCIe x16 Slot B-H), and can be inserted with a standard PCI card or a U.2NVME disk.

In addition, as shown in fig. 2, the CPU chip includes 16 memory channels, which are denoted as channels 0 to 15, each memory Channel is connected to 2 DDR4 DIMM slots, and at most 32 DDR4 DIMM memory banks can be plugged. The CPU chip is connected with 8 USB interfaces, and 8 USB interfaces support the USB3.0 standard, wherein the USB CON A connector can connect the USB port to the panel interface of the front panel through a 20pin cable, which is convenient for users to use. In addition, the system also comprises a Type-C connector interface CONE and a switch USB SW.

The BMC chip on the motherboard is responsible for system management and can control the CPU chip, as shown in fig. 3, the BMC chip is connected to the CPU chip via an LPC bus, a USB bus, and an SPI bus. The BMC chip is externally connected with a gigabit PHY chip, for example, RTL8211F, the gigabit PHY chip is externally connected with 1 gigabit RJ45 interface to serve as a remote management interface, and the remote management platform realizes management of the No. 3 Hai CPU server mainboard through a gigabit network.

The specific interconnection relationship between BMC and CPU is as follows:

interconnection of SPI buses: the CPU BIOS may be toggled to BMC, or to the CPU via SPI SW (signal switch). When the BIOS firmware is upgraded, the BIOS firmware is switched to be connected to the BMC. And switching to the CPU when the CPU server is normally started up and operated. Therefore, CPU BIOS firmware can be upgraded through the remote management platform, namely the remote management platform sends a new BIOS to the BMC through a gigabit RJ45 interface of the BMC, the BMC writes a BIOS chip again, then the CPU is switched to through the SPI SW, and the CPU is started to use the new BIOS firmware.

Interconnection of LPC bus: the LPC bus interconnected between the BMC and the CPU is used for transmitting the starting operation state information of the CPU, and after the information is transmitted to the BMC, the information is displayed through an LED PORT80 connected with the BMC. And is also connected to the CPLD to inform the CLPD of the current starting running state of the CPU.

USB bus interconnection: the USB bus interconnected between the BMC and the CPU is used to implement a remote KVM (keyboard, video, mouse), that is, the remote management platform is connected to the BMC through a BMC gigabit RJ45 network port, and then connected to the CPU through a USB port of the BMC.

In addition, the BMC chip is connected with 1 COM interface and used for being externally connected with serial equipment. The BMC chip is connected with 1 VGA interface, and is used as a display interface of the mainboard and externally connected with display equipment. The BMC chip is connected with an LED display interface LED port80 to display the state of the CPU. The BMC chip is connected with a FAN interface FAN CON [1:8] to control the FAN in the server chassis. The BMC chip is connected with the SD card interface and stores server log information. The BMC chip is connected with the BMC FW Flash, and the BMC firmware BMC FW of the BMC system is stored in the BMC FW Flash.

By combining the above fig. 1 to fig. 3, a schematic diagram of the overall structure of the server motherboard shown in fig. 4 can be obtained.

The embodiment of the utility model provides a still provide a single server, single server includes above-mentioned server mainboard.

The embodiment of the utility model provides a server mainboard and one-way server, CPU chip on the mainboard have the high-speed interface in 16 passageways of multiunit, and wherein the high-speed interface in a set of 16 passageways is configured into the compound interface that supports multiple transmission protocol, for example supports agreement such as SATA, PCIe, XGBE simultaneously, has realized the configurability of IO interface to the nimble configuration of mainboard interface has been realized.

The above description is only for the specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention should be covered by the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. The server mainboard is characterized in that a processor CPU chip and a baseboard management controller BMC chip are arranged on the server mainboard, and the BMC chip is used for controlling the CPU chip, wherein the CPU chip is provided with a plurality of groups of high-speed interfaces with 16 channels, and the high-speed interfaces with 16 channels in one group are configured to be composite interfaces supporting multiple transmission protocols.

2. The server motherboard of claim 1 wherein a set of 16-way high-speed interfaces are configured as a composite interface as follows:

the [0:3] path is configured to support a first sub-interface of SATA4 x;

the [4:7] lane is configured to support a second subinterface of XGBE 4 x;

the [8:11] lane is configured to support a third subinterface of PCIe x 4;

[12] the lane is configured to support a fourth subinterface of PCIe x 1;

[13] the lane is configured to support a fifth subinterface of PCIe x 1;

the [14:15] lane is configured to support the sixth subinterface of PCIe x 2.

3. Server board as in claim 2,

the first sub-interface is connected to 4 SATA connectors;

the second sub-interface is connected to 4 SFP + connectors;

the third sub-interface is connected to a gigabit network chip;

the fourth sub-interface is connected to the BMC chip;

the fifth sub-interface is connected to a first M.2 connector;

the sixth sub-interface is connected to a second m.2 connector.

4. The server motherboard of claim 3 wherein the gigabit network chip is I350 with a 2-way gigabit port network.

5. The server motherboard of claim 1 wherein the remaining high-speed interfaces other than the high-speed interface configured as a composite interface are configured to support PCIe x16 interfaces, respectively connected to PCIe x16 slots.

6. The server motherboard of claim 1 wherein the CPU chip further comprises a plurality of memory channels, each memory channel connected to 2 DIMM slots.

7. The server motherboard of claim 1 wherein the CPU chip is connected to a plurality of USB interfaces.

8. The server motherboard of claim 1 wherein the BMC chip is connected to the CPU chip via an LPC bus, a USB bus, and an SPI bus.

9. The server motherboard of claim 1 wherein the BMC chip is connected to a gigabit PHY chip that is connected to a gigabit RJ45 interface for connection to a remote management platform via the gigabit RJ45 interface.

10. A one-way server, characterized in that it comprises a server motherboard according to any of claims 1 to 9.