CN213275730U

CN213275730U - Isolation voltage input circuit of test system

Info

Publication number: CN213275730U
Application number: CN202022425528.7U
Authority: CN
Inventors: 王献伟; 徐东桂; 任敬哲
Original assignee: Guangzhou Weide Electric Equipment Co ltd
Current assignee: Guangzhou Weide Electric Equipment Co ltd
Priority date: 2020-10-27
Filing date: 2020-10-27
Publication date: 2021-05-25
Anticipated expiration: 2030-10-27

Abstract

The utility model discloses a test system's isolation voltage input circuit, including isolation circuit and the test circuit who is connected with isolation circuit, isolation circuit and test circuit are connected, isolation circuit includes that the power keeps apart chip J1, inductance L1, electric capacity C1, electric capacity C2 and electric capacity C3, the power keeps apart chip J1's Vin end and is connected with the 5V power after parallelly connected with electric capacity C1, the power keeps apart chip J1's GND end and the parallelly connected back ground connection of electric capacity C1, the power keeps apart chip J1's Vout end and inductance L1 series connection, inductance L1 is connected with test circuit after parallelly connected with electric capacity C2 and electric capacity C3 respectively, the power keeps apart chip J1's 0V end respectively with electric capacity C2, the parallelly connected back ground connection of electric capacity C3 and test circuit. The circuit isolates the input end from the test system through the power isolation chip J1, thereby avoiding the deviation of the external input voltage from damaging the whole test system and improving the reliability of the test system.

Description

Isolation voltage input circuit of test system

Technical Field

The utility model relates to the field of electronic technology, concretely relates to test system's isolation voltage input circuit.

Background

With the great popularization and use of servo motors, the demand of servo control systems is correspondingly increased, the quality and the reliability of different servo control systems are different, and under the background, a servo test system is developed, and the quality and the reliability of the servo control systems are tested through the servo test system, so that the quality of the servo control systems is distinguished. The servo test system can detect the problem of the servo control system, and then reads an actual voltage value through an ADC (analog to digital converter) circuit of the single chip microcomputer to be used as one of the bases for judging the quality of the servo motor driving board.

The existing test system mainly inputs the voltage to be measured into a circuit directly for measurement, then samples and calculates the actual voltage value through an ADC circuit, but the input voltage and the whole test circuit share the same ground in the process, and the whole test system can be damaged when the tested input voltage has deviation.

SUMMERY OF THE UTILITY MODEL

An object of the utility model is to provide a test system's isolation voltage input circuit protects test system, improves test system's reliability and suitability.

To achieve the purpose, the utility model adopts the following technical proposal:

the isolation voltage input circuit of the test system comprises an isolation circuit and a test circuit connected with the isolation circuit, wherein the isolation circuit comprises a power isolation chip J1, an inductor L1, a capacitor C1, a capacitor C2 and a capacitor C3, a Vin end of a power isolation chip J1 is connected with a 5V power supply after being connected with the capacitor C1 in parallel, a GND end of the power isolation chip J1 is connected with the capacitor C1 in parallel and then grounded, a Vout end of a power isolation chip J1 is connected with the inductor L1 in series, the inductor L1 is connected with the capacitor C2 and the capacitor C3 in parallel and then connected with the test circuit, and a 0V end of the power isolation chip J1 is connected with the capacitor C2, the capacitor C3 and the test circuit in parallel and then grounded.

As a preferable scheme of the isolation voltage input circuit of the test system, the test circuit comprises an isolation amplifier U1, a resistor R1, a resistor R2, a resistor R3, a capacitor C4, a capacitor C5 and a capacitor C6, the resistor R1 is connected with an external input voltage MMP1, the resistor R2 is respectively connected with the resistor R1 and the capacitor C4 in parallel and then connected with the resistor R3, the resistor R3 is connected IN parallel with the capacitor C5 and then connected with the IN + end of the isolation amplifier U1, the resistor R2, the capacitor C4, the capacitor C5, the IN-end of the isolation amplifier U1 and the GND1 end are connected IN parallel and then grounded, the capacitor C2 and the capacitor C3 are connected in parallel and then are connected with the VDD1 terminal of the isolation amplifier U1, the VDD2 end of the isolation amplifier U1 is connected with the capacitor C6 in parallel and then is connected with a 5V power supply, and the GND2 end of the isolation amplifier U1 is connected with the capacitor C6 in parallel and then is grounded.

As a preferable scheme of an isolation voltage input circuit of the test system, the power isolation chip J1 is B0505S-1W.

As a preferred solution for testing the isolated voltage input circuit of the system, the isolation amplifier U1 is AMC 1200.

As a preferable scheme of the isolated voltage input circuit of the test system, the resistance value of the resistor R1 is 49.5K Ω, the resistance value of the resistor R2 is 330 Ω, and the resistance value of the resistor R3 is 100 Ω.

As a preferable scheme of the isolated voltage input circuit of the test system, the capacitances of the capacitor C1, the capacitor C3 and the capacitor C6 are all 0.1 μ F, the capacitance of the capacitor C2 is 10 μ F, and the capacitances of the capacitor C4 and the capacitor C5 are all 10 nF.

The utility model has the advantages that: the utility model discloses add power isolation chip J1 and keep apart input and test system in the circuit, thereby avoid outside input voltage to appear the deviation and damage whole test system, improved test system's reliability, and because the isolation of chip J1 is kept apart to the power, the test voltage of input also does not confine to the connection measuring voltage on different places, the voltage at other different ground planes also can measure, has improved test system's suitability.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required to be used in the embodiments of the present invention will be briefly described below. It is obvious that the drawings described below are only some embodiments of the invention, and that for a person skilled in the art, other drawings can be obtained from these drawings without inventive effort.

Fig. 1 is a schematic circuit diagram of an isolation circuit of a test system according to an embodiment of the present invention.

Fig. 2 is a schematic circuit diagram of a test circuit of a test system according to an embodiment of the present invention.

Detailed Description

The technical solution of the present invention is further explained by the following embodiments with reference to the accompanying drawings.

Wherein the showings are for the purpose of illustration only and are shown by way of illustration only and not in actual form, and are not to be construed as limiting the present patent; for a better understanding of the embodiments of the present invention, some parts of the drawings may be omitted, enlarged or reduced, and do not represent the size of an actual product; it will be understood by those skilled in the art that certain well-known structures in the drawings and descriptions thereof may be omitted.

The same or similar reference numerals in the drawings of the embodiments of the present invention correspond to the same or similar parts; in the description of the present invention, it should be understood that if the terms "upper", "lower", "left", "right", "inner", "outer", etc. are used to indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, it is only for convenience of description and simplification of description, but it is not indicated or implied that the device or element referred to must have a specific orientation, be constructed in a specific orientation, and be operated, and therefore, the terms describing the positional relationship in the drawings are used only for illustrative purposes and are not to be construed as limiting the present patent, and the specific meaning of the terms will be understood by those skilled in the art according to the specific circumstances.

In the description of the present invention, unless otherwise explicitly specified or limited, the term "connected" or the like, if appearing to indicate a connection relationship between the components, is to be understood broadly, for example, as being either a fixed connection, a detachable connection, or an integral part; can be mechanically or electrically connected; they may be directly connected or indirectly connected through intervening media, or may be connected through one or more other components or may be in an interactive relationship with one another. The specific meaning of the above terms in the present invention can be understood in specific cases to those skilled in the art.

As shown in fig. 1 and 2, the embodiment of the present invention provides a test system's isolation voltage input circuit includes isolation circuit and with the test circuit that isolation circuit connects, isolation circuit includes power isolation chip J1, inductance L1, electric capacity C1, electric capacity C2 and electric capacity C3, power isolation chip J1's Vin end is connected with the 5V power after parallelly connected with electric capacity C1, power isolation chip J1's GND end is grounded with electric capacity C1 parallelly connected, power isolation chip J1's Vout end and inductance L1 series connection, inductance L1 is connected with test circuit after parallelly connected with electric capacity C2 and electric capacity C3 respectively, power isolation chip J1's 0V end is grounded with electric capacity C2, electric capacity C3 and test circuit parallelly connected back respectively.

For sampling the voltage of an ADC (Analog-to-digital converter) of the whole test system, the voltage at the input end of the test system is mostly a high voltage of 220V, so that the input voltage is isolated to avoid the input voltage from generating a deviation to damage the whole test system. The power isolation chip J1 is added to the circuit to isolate the input end from the test system, so that the deviation of the external input voltage is avoided, the whole test system is damaged, and the reliability of the test system is improved.

As a preferred embodiment of the present invention, the test circuit includes an isolation amplifier U1, a resistor R1, a resistor R2, a resistor R3, a capacitor C4, a capacitor C5 and a capacitor C6, the resistor R6 is connected to an external input voltage MMP 6, the resistor R6 is connected to the resistor R6 after being connected IN parallel to the resistor R6 and the capacitor C6, the resistor R6 is connected to an IN + terminal of the isolation amplifier U6 after being connected IN parallel to the capacitor C6, the resistor R6, the capacitor C6, the IN-terminal of the isolation amplifier U6, and a GND 6 terminal are connected to ground after being connected IN parallel to the capacitor C6, the VDD 6 terminal of the isolation amplifier U6 is connected to a VDD 6 terminal of the isolation amplifier U6 and a GND power supply, and the GND 6 terminal of the isolation amplifier U6 is connected to ground after being connected IN parallel to the capacitor C6.

The external input voltage MMP1 of this embodiment can select the high-voltage input, only needs to reduce external input voltage MMP1 through the resistance of adjustment divider resistance R1, reads through the ADC circuit after the rethread isolation amplifier U1 is enlarged, because the isolation effect of isolation circuit, external input voltage can not cause the influence to test system.

Compared with a test system without an isolation circuit, the present embodiment does not need to consider whether the accessed ground plane is consistent with the test system under the isolation effect of the power isolation chip J1, for example, the digital ground DGND in fig. 1 and the ground plane MMGND of the external voltage input terminal in fig. 2 are isolated, even if the two ground planes are different, the circuit is not affected, the measurement deviation problem caused by the inconsistency of the ground planes of the test system is avoided, the input test voltage is not limited to the connection measurement voltage of the different ground, the voltages of other different ground planes can be measured, and the applicability of the test system is improved.

In this embodiment, the power isolation chip J1 is B0505S-1W.

In this embodiment, isolation amplifier U1 is AMC 1200.

In the embodiment, the resistance of the resistor R1 is 49.5K Ω, the resistance of the resistor R2 is 330 Ω, and the resistance of the resistor R3 is 100 Ω.

In this embodiment, the capacitances of the capacitor C1, the capacitor C3 and the capacitor C6 are all 0.1 μ F, the capacitance of the capacitor C2 is 10 μ F, and the capacitances of the capacitor C4 and the capacitor C5 are all 10 nF.

A power isolation chip is added to the circuit as an input to isolate the amplifier ground plane and one of the entire test system. The amplifier chip U5 is damaged at best.

It should be understood that the above-described embodiments are merely illustrative of the preferred embodiments of the present invention and the technical principles thereof. It will be understood by those skilled in the art that various modifications, equivalents, changes, and the like can be made to the present invention. However, these modifications are within the scope of the present invention as long as they do not depart from the spirit of the present invention. In addition, certain terms used in the specification and claims of the present application are not limiting, but are used merely for convenience of description.

Claims

1. The isolation voltage input circuit of the test system is characterized by comprising an isolation circuit and a test circuit connected with the isolation circuit, wherein the isolation circuit comprises a power isolation chip J1, an inductor L1, a capacitor C1, a capacitor C2 and a capacitor C3, the Vin end of the power isolation chip J1 is connected with a 5V power supply after being connected in parallel with the capacitor C1, the GND end of the power isolation chip J1 is connected with the capacitor C1 in parallel and then grounded, the Vout end of the power isolation chip J1 is connected with the inductor L1 in series, the inductor L1 is connected with the capacitor C2 and the capacitor C3 in parallel and then connected with the test circuit, and the 0V end of the power isolation chip J1 is connected with the capacitor C2, the capacitor C3 and the test circuit in parallel and then grounded.

2. The isolated voltage input circuit of the test system of claim 1, the test circuit comprises an isolation amplifier U1, a resistor R1, a resistor R2, a resistor R3, a capacitor C4, a capacitor C5 and a capacitor C6, the resistor R1 is connected with an external input voltage MMP1, the resistor R2 is respectively connected with the resistor R1 and the capacitor C4 in parallel and then connected with the resistor R3, the resistor R3 is connected IN parallel with the capacitor C5 and then connected with the IN + end of the isolation amplifier U1, the resistor R2, the capacitor C4, the capacitor C5, the IN-end of the isolation amplifier U1 and the GND1 end are connected IN parallel and then grounded, the capacitor C2 and the capacitor C3 are connected in parallel and then are connected with the VDD1 terminal of the isolation amplifier U1, the VDD2 end of the isolation amplifier U1 is connected with the capacitor C6 in parallel and then is connected with a 5V power supply, and the GND2 end of the isolation amplifier U1 is connected with the capacitor C6 in parallel and then is grounded.

3. The isolated voltage input circuit of claim 1, wherein the power isolation chip J1 is B0505S-1W.

4. The isolated voltage input circuit of claim 2, wherein the isolation amplifier U1 is an AMC 1200.

5. The isolated voltage input circuit of claim 2, wherein the resistance of the resistor R1 is 49.5K Ω, the resistance of the resistor R2 is 330 Ω, and the resistance of the resistor R3 is 100 Ω.

6. The isolated voltage input circuit of claim 2, wherein the capacitance of said capacitor C1, said capacitor C3 and said capacitor C6 are all 0.1 μ F, the capacitance of said capacitor C2 is 10 μ F, and the capacitance of said capacitor C4 and said capacitance of said capacitor C5 are all 10 nF.