CN213212143U

CN213212143U - Wafer bearing table and wafer processing system

Info

Publication number: CN213212143U
Application number: CN202021141566.3U
Authority: CN
Inventors: 黄小华; 谢建; 黄�俊; 王凤娇; 陈际舟; 文朝军
Original assignee: CHENGDU SILAN SEMICONDUCTOR MANUFACTURING Ltd
Current assignee: CHENGDU SILAN SEMICONDUCTOR MANUFACTURING Ltd
Priority date: 2020-06-18
Filing date: 2020-06-18
Publication date: 2021-05-14
Anticipated expiration: 2030-06-18

Abstract

The application discloses wafer bearing platform and wafer processing system, in order to solve the back silicon slag problem after wafer epitaxy, promote the product quality after wafer epitaxy, this wafer bearing platform includes the loading face, the loading face includes the recess, the diameter of recess and the diameter phase-match of wafer, when making the wafer be located the loading face, the back of wafer only part position directly contacts with the loading face, the edge at the back of wafer is unsettled state, make the wafer will easily pile up and accumulate the back marginal zone unsettled of silicon slag when the transit, the influence of wafer that has been processed to wafer bearing platform and the wafer of treating processing has been avoided, help improving the quality and the performance of product.

Description

Wafer bearing table and wafer processing system

Technical Field

The utility model relates to a semiconductor silicon epitaxy technical field, concretely relates to wafer bearing platform and wafer processing system.

Background

With the rapid development of microelectronic technology, the integration density of electronic components and chips is increasing, the size is smaller and smaller, and the precision required by silicon epitaxy of wafers is higher and higher. Silicon epitaxy is the growth of a layer of crystal with the same crystal orientation as a substrate and with good lattice structure integrity and different resistivity and thickness on a silicon single crystal substrate with a certain crystal orientation. The back side silicon slag is a problem which is difficult to avoid in the field of silicon epitaxy, and the back side silicon slag is generated when silicon epitaxy occurs.

The silicon epitaxy process of the wafer is that silicon chloride is reduced by hydrogen at high temperature to generate a silicon simple substance, and the silicon simple substance is deposited on the surface of the wafer. The back silicon slag is formed by growing a silicon simple substance on the back of the wafer during the silicon epitaxy process of the wafer, and is mainly and intensively distributed in a ring-shaped zone with the width of about 5mm on the edge of the back of the wafer. After the silicon slag on the back is formed, the wafer is uneven, and the subsequent photoetching quality is seriously influenced. In part of the prior art, manual polishing is performed on the back surface of the wafer after silicon epitaxy is performed on the wafer, but the method seriously affects the cleanliness of the surface of the wafer, and more cleaning cost is required to be consumed for cleaning the polished wafer.

Through a large number of tests and theoretical analysis, the back silicon slag is found to have the following characteristics: 1. the wafer is intensively distributed in a ring-shaped belt with the width of about 5mm on the edge of the back of the wafer; 2. 2-3 parts of each wafer are densely distributed in a block shape, and the positions of the wafers are the same; 3. after the wafer bearing platform is cleaned, the back silicon slag disappears, but as the number of processed wafers increases, the back silicon slag gradually gathers. The characteristics of the back silicon slag are integrated, and the steps of transferring the wafers before and after epitaxy through the wafer bearing platform are combined, so that the following steps can be obtained: a small amount of silicon slag particles on the edge of the back surface of the wafer after the epitaxy are attached to the wafer bearing platform when the wafer bearing platform transfers, so that the bearing surface of the wafer bearing platform is polluted; when the equipment loads the next wafer, silicon slag particles remained on the wafer bearing table during the last transfer are adhered to the back surface of the wafer which is not subjected to epitaxy on the wafer bearing table; the severity of the silicon slag on the back surface after the extension is increased, more silicon slag particles fall on the wafer bearing platform during wafer taking, and the steps are repeated to form a vicious circle.

Therefore, in order to improve the product quality and control the production cost, a technical scheme capable of preventing and improving the silicon slag on the back surface of the wafer is an urgent problem to be solved at the present stage.

SUMMERY OF THE UTILITY MODEL

In view of the above problem, an object of the present invention is to provide a wafer supporting platform and wafer processing system, which can effectively reduce the influence of the back silicon slag of the processed wafer on the processed wafer by providing a groove on the supporting surface and suspending the back edge region of the wafer in the supporting platform. The method is beneficial to improving the quality and performance of silicon epitaxy, and further, a corresponding purging device can be arranged to purge the wafer bearing platform, so that the cleanness of the bearing surface is ensured.

In order to achieve the above object, according to an aspect of the present invention, there is provided a wafer bearing table, wherein the bearing surface of the wafer bearing table includes a groove, the size and position of the groove are matched with the wafer, so that the wafer is located on the bearing surface, and the edge of the wafer is in a suspension state.

Preferably, the groove is annular, and the cross-sectional width of the groove is not less than 2 mm.

Preferably, the depth of the groove is 2-4 mm.

Preferably, the wafer bearing table further comprises a notch, and the notch is matched with a mechanical arm to facilitate the placement and the picking of the wafer.

Preferably, the notch is any one of a rectangle, a rounded rectangle and a fan shape.

Preferably, the grooves comprise at least two groups, at least two groups of the grooves are concentrically arranged, and each group of the grooves is matched with a wafer with one size.

Preferably, the height of the bearing surface is gradually reduced from outside to inside by taking the groove as a boundary, and the height difference between the lowest and the highest of the bearing surface is not more than 1 mm.

Preferably, the bearing surface is divided into a plurality of regions by the grooves, and the heights of the regions of the bearing surface are the same.

Preferably, the wafer size suitable for the wafer bearing table comprises one or more of 5 inches, 6 inches, 8 inches and 12 inches.

Preferably, the wafer bearing table is further provided with a purging device for purging silicon slag falling off during wafer transfer.

According to the utility model discloses an on the other hand, the utility model discloses still provide a wafer processing system, a serial communication port, include:

the wafer to be processed is placed in the first wafer basket;

a first robot to move a wafer to be processed from the first wafer basket to a wafer table, and to move a processed wafer from the wafer table to a second wafer basket;

the wafer bearing platform comprises a bearing surface, the bearing surface comprises a groove, the diameter of the groove is matched with that of a wafer, the wafer is positioned on the bearing surface, and the edge of the wafer is in a suspended state;

the second mechanical arm moves the wafer to be processed from the wafer bearing table to the reaction chamber, and the second mechanical arm moves the processed wafer from the reaction chamber to the wafer bearing table;

the wafer processing device comprises a reaction cavity, a processing device and a control device, wherein a wafer to be processed is placed in the reaction cavity for processing;

and the processed wafer is placed in the second wafer basket.

Preferably, the groove is annular, and the width of the groove is not less than 2 mm.

Preferably, the depth of the groove is 2-4 mm.

The utility model provides a wafer bearing platform and wafer processing system, its loading end has the groove design, whole wafer bearing platform simple structure, through the recess on the loading end, the back marginal zone's of wafer unsettled has been realized, the back dross granule that has effectively cut off the processed wafer shifts to the on-the-shelf way of wafer bearing, the wafer that the processing was treated to the processed wafer has been reduced and has been caused the influence, the back dross that has prevented the processed wafer is infected with through the wafer bearing platform to the back of treating the wafer of processing, the back dross condition of the processed wafer has been showing and has been improved, make the silicon rate of scraping at the processed wafer back reduce to 1% from 80%, the quality level after the wafer extension has been promoted greatly. And the wafer bearing table is simple in structure, low in modification difficulty, free of influence on other equipment components, capable of greatly saving labor and cleaning cost, remarkably reducing production cost and suitable for large-scale application and popularization. Furthermore, the bearing platform of the bearing platform can be periodically swept by arranging the corresponding sweeping device, so that the accumulation of silicon slag is prevented, and the cleanness and the flatness of the bearing platform are ensured.

Drawings

The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

FIG. 1 is a schematic view of a wafer stage according to a first embodiment of the present invention;

FIG. 2 is a top view of a wafer stage according to a first embodiment of the present invention;

FIG. 3 is a left side view of the wafer stage according to the first embodiment of the present invention;

fig. 4 is a schematic view of a wafer processing system according to a first embodiment of the present invention;

fig. 5 is a flowchart illustrating a wafer processing system according to a first embodiment of the present invention;

FIG. 6 is a schematic view of a wafer stage according to a first embodiment of the present invention;

FIG. 7 is a schematic view of a wafer stage according to a second embodiment of the present invention;

Detailed Description

Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by the same or similar reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale.

The present invention is not limited to these embodiments. In the following detailed description of the present invention, certain specific details are set forth in detail. It will be apparent to those skilled in the art that the present invention may be practiced without these specific details. Well-known methods, procedures, and procedures have not been described in detail so as not to obscure the present invention.

The following detailed description of the embodiments of the present invention is provided with reference to the accompanying drawings and examples.

Fig. 1 to 3 are a perspective view, a plan view and a left side view of a wafer stage according to a first embodiment of the present invention. As shown in fig. 1, the stage 100 is, for example, cylindrical and has a size matching the size of the wafer, the stage 100 includes a carrying surface 110 for carrying the wafer, a step 120 is disposed on an edge region of the carrying surface 110, the step 120 has a shape of, for example, a circular ring in a top view, and the carrying surface 110 has a size matching the size of the wafer. Specifically, since the steps 120 are disposed on the edge region of the carrying surface 110, the wafer can be supported by the middle region of the carrying surface 110, and only the middle region of the back surface of the wafer directly contacts the carrying surface 110, so that the edge region of the back surface of the wafer is suspended. The wafer is extended by the existing epitaxial processing technology, a small amount of silicon slag often exists at the edge region at the back of the wafer after the extension, and the silicon slag in the edge region of the back of the wafer after the extension usually can be stained and adhered on the bearing surface 110 when the wafer is rotated, because the edge of the bearing surface 110 is provided with the step 120, thereby avoiding the silicon slag in the edge region of the back of the wafer which is processed from being stained on the bearing surface 110, effectively reducing the influence on the wafer borne by the follow-up wafer bearing platform 100 due to the fact that the bearing surface 110 is stained with the silicon slag, and lightening the severity of the silicon slag at the back of the wafer. Through a large number of experiments and theoretical analysis, it is found that the silicon slag on the back side of the processed wafer is generally concentrated in the annular zone of about 5mm in the edge area of the back side of the wafer, so that the width d of the step 120 is designed to be not less than 2mm, the depth h is designed to be 2-4mm, and preferably, the width d of the step 120 is 2-7mm, although the situation of different sizes of wafers may not be the same, and the width d of the step 120 can be adjusted according to the specific wafer size. As shown in fig. 2, one side of the wafer support 100 has a rectangular recess 130 with rounded corners extending through the entire top and bottom surfaces of the wafer support 100, and the shape and size of the recess match those of the robot facing the side to facilitate the robot's picking and placing of wafers on the support surface 110. Of course, the recess 130 may also be rectangular, scalloped, or the like. As shown in fig. 3, the step 120 is located at an edge region of the carrying surface 110, specifically, the depth h of the step 120 is, for example, 2-4mm, the thickness of the carrying table of the present embodiment is, for example, 8mm, when a processed wafer is placed on the carrying table 100, a middle region of a back surface of the wafer contacts with the carrying surface 110, and the edge region of the back surface of the wafer is suspended above the step 120, so that even if the edge region has a silicon slag falling off, the silicon slag can be temporarily contained in the step 120 to prevent the silicon slag from being contaminated on a back surface of a subsequent wafer, further, the step 120 can be periodically purged, and the carrying surface 110 and the step 120 can be periodically purged by designing a corresponding purging device on the carrying table 100, thereby ensuring the cleaning of the carrying table. The wafer table 100 described above may be suitable for carrying wafers of 5 inches, 6 inches, 8 inches, and 12 inches, for example.

Fig. 4 and 5 show a schematic diagram and a work flow diagram of a wafer processing system according to a first embodiment of the present invention, respectively. As shown in fig. 4, the stage 100 is applied to a wafer processing system, and particularly relates to an epitaxial growth process of a wafer, the wafer processing system includes: a first wafer basket 211, a second wafer basket 212, a first robot 210, a stage 100 in a transfer chamber 300, a second robot 220, and a reaction chamber 400. The material of the wafer stage 100 is, for example, high-purity quartz. The first robot 210 takes out the wafer to be processed from the first wafer basket 211, and the wafer enters the reaction chamber 400 through the transfer of the wafer bearing table 100 and the second robot 220 for epitaxial growth. The processed wafer is transferred to the second wafer basket 212 by the second robot 220, the wafer stage 100, and the first robot 210 in sequence. Further, as shown in fig. 5, in the wafer loading process, the wafer to be processed is loaded and transferred through the loading surface 110 of the wafer loading platform 100, and in the wafer taking process, the processed wafer is also loaded and transferred through the loading surface 110, and by the design of the step 120, the back edge area of the processed wafer is suspended at the wafer loading platform 100, so that the influence of the back silicon slag of the processed wafer on the wafer to be processed is effectively avoided. Further, a purging device can be arranged on the wafer bearing table 100 and used for purging the bearing surface 110 and the step 120 periodically, so that the accumulation of silicon slag is prevented, the bearing surface is guaranteed to be smooth and clean, and the stability of product quality is guaranteed.

Fig. 6 is a schematic view illustrating the wafer supporting platform according to the first embodiment of the present invention, wherein the wafer 1110 is transferred through the supporting surface 110 of the wafer supporting platform 100, and the edge area of the back surface of the wafer is suspended during the transferring process, so as to reduce the contamination of the silicon slag on the back surface of the wafer to the supporting surface 110. Certainly, the size of the wafer bearing table 100 may also be designed to be slightly smaller than the size of the wafer matched therewith, that is, the size of the bearing surface 110 is designed to be slightly smaller than the size of the wafer, so that the edge area of the wafer is suspended, and the specific structure is not described herein again. While the support surface 110 of the susceptor 100 of fig. 6 has a ring-shaped step 120 to suspend the edge region of the wafer back side of one dimension, the step 120 may be understood as a special case where the cavity is located in the edge-most region of the support surface, when the support surface 110 has two or more ring-shaped cavities with functions similar to those of the step 120, that is, the non-edge-most region of the support surface 110 has a ring-shaped cavity to accommodate wafers of various dimensions to suspend the edge region of the wafer back side of various dimensions.

As shown in fig. 7, the carrying surface 510 of the second embodiment of the present invention has, for example, 3 sets of grooves (the outermost step can be regarded as a special case where the groove is located at the outermost edge), a first groove 521, a second groove 522 and a third receiving groove 523. Specifically, the first notch 521 matches with, for example, an 8-inch wafer, the second notch 522 matches with, for example, a 6-inch wafer, and the third notch 523 matches with, for example, a 5-inch wafer. Of course, more sets of grooves may be added according to the size and design requirements of the wafer stage 500, and will not be described herein.

The bearing surface 510 in this embodiment is divided into a plurality of regions by the grooves, wherein the height of each region is flush, and further, the height of the bearing surface 510 may gradually decrease from outside to inside by taking the grooves as a boundary, that is, the height of the bearing surface 510 in the third groove 523 is the lowest, the height of the bearing surface 510 between the third groove 523 and the second groove 522 is the second highest, and the height of the bearing surface 510 between the second groove 522 and the first groove 521 is the highest. The height difference between the lowest and the highest of the bearing surfaces is not more than 1 mm. The level design of the carrying surface 510 facilitates the wafer picking operation.

To sum up, the embodiment of the utility model has following advantage or beneficial effect: the utility model provides a wafer bearing platform and wafer processing system, its loading end has the groove design, whole wafer bearing platform simple structure, through the recess on the loading end, the back marginal zone's of wafer unsettled has been realized, the back dross granule that has effectively cut off the processed wafer shifts to the on-the-shelf way of wafer bearing, the wafer that the processing was treated to the processed wafer has been reduced and has been caused the influence, the back dross that has prevented the processed wafer is infected with through the wafer bearing platform to the back of treating the wafer of processing, the back dross condition of the processed wafer has been showing and has been improved, make the silicon rate of scraping at the processed wafer back reduce to 1% from 80%, the quality level after the wafer extension has been promoted greatly. And the wafer bearing table is simple in structure, low in modification difficulty, free of influence on other equipment components, capable of greatly saving labor and cleaning cost, remarkably reducing production cost and suitable for large-scale application and popularization. Furthermore, the bearing platform of the bearing platform can be periodically swept by arranging the corresponding sweeping device, so that the accumulation of silicon slag is prevented, and the cleanness and the flatness of the bearing platform are ensured.

It should be noted that, in the description of the present invention, the terms "first" and "second" are only used for convenience in describing different components, and are not to be construed as indicating or implying a sequential relationship, relative importance or implicitly indicating the number of technical features indicated.

The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included within the protection scope of the present invention.

Claims

1. The utility model provides a wafer bearing platform, includes the loading end, its characterized in that, the loading end includes the recess, the diameter of recess and the diameter phase-match of wafer make the wafer is located on the loading end, the edge of wafer is unsettled state, wafer bearing platform still includes the notch, notch and manipulator phase-match are convenient for placing and picking up of wafer.

2. The stage of claim 1, wherein the groove is annular and has a width of no less than 2 mm.

3. The stage according to claim 1, wherein the depth of the groove is 2-4 mm.

4. The stage according to claim 1, wherein the recess is any one of a rectangle, a rounded rectangle, and a sector.

5. The wafer table of claim 1, wherein the grooves comprise at least two sets of grooves, at least two sets of grooves being concentrically arranged, each set of grooves matching a wafer of one size.

6. The stage according to claim 5, wherein the height of the bearing surface decreases gradually from the outside to the inside, with the recess as a boundary, and the difference in height between the lowest and highest of the bearing surface is no greater than 1 mm.

7. The stage of claim 5, wherein the grooves divide the bearing surface into a plurality of zones, the zones of the bearing surface having the same height.

8. The stage of claim 1, wherein the wafer sizes for which the stage is adapted include one or more of 5 inches, 6 inches, 8 inches, and 12 inches.

9. The wafer table of claim 1, wherein the wafer table is further provided with a purging device to purge silicon slag falling during wafer transfer.

10. A wafer processing system, comprising:

the wafer to be processed is placed in the first wafer basket;

and the processed wafer is placed in the second wafer basket.

11. The wafer processing system of claim 10, wherein the groove is annular and has a width of not less than 2 mm.

12. The wafer processing system of claim 10, wherein the depth of the groove is 2-4 mm.

13. The wafer processing system of claim 10, wherein the stage further comprises a notch that mates with a robot to facilitate placement and picking of wafers.

14. The wafer processing system of claim 13, wherein the notch is any one of rectangular, rounded rectangular, and scalloped.

15. The wafer processing system of claim 10, wherein the grooves comprise at least two sets of grooves arranged concentrically, each set of grooves matching a size of wafer.

16. The wafer processing system of claim 15 wherein the height of the bearing surface decreases from outside to inside with the recess as a boundary, the difference in height between the lowest and highest of the bearing surface being no greater than 1 mm.

17. The wafer processing system of claim 15 wherein the grooves divide the bearing surface into a plurality of zones, the zones of the bearing surface having the same height.

18. The wafer processing system of claim 10, wherein the wafer size for the stage comprises one or more of 5 inches, 6 inches, 8 inches, and 12 inches.

19. The wafer processing system of claim 10, wherein the wafer table is further provided with a purging device to purge silicon slag falling during wafer transfer.