CN213211655U - Display screen assembly and electronic equipment - Google Patents
Display screen assembly and electronic equipment Download PDFInfo
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- CN213211655U CN213211655U CN202022592518.2U CN202022592518U CN213211655U CN 213211655 U CN213211655 U CN 213211655U CN 202022592518 U CN202022592518 U CN 202022592518U CN 213211655 U CN213211655 U CN 213211655U
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Abstract
The application provides a display screen assembly and an electronic device. The display screen assembly comprises a display panel, a driving chip, a first testing unit, a first detecting unit and a first calculating unit. The driving chip is bound with the display panel through a plurality of first binding points to drive the display panel to work, the driving chip comprises a first testing pin and a second testing pin, one end of the first testing pin is electrically connected with one end of the second testing pin, and the other end of the first testing pin is electrically connected with the other end of the second testing pin through a first binding point and another first binding point. The first test unit is electrically connected with the first binding point and used for providing a first test voltage and a first test current. The first detection unit detects a voltage value of the second test pin to obtain a first voltage. The first calculation unit obtains a first resistance value of the first binding point according to the first test voltage, the first voltage and the first test current. The application provides every display screen subassembly all can detect the first resistance value of first binding point.
Description
Technical Field
The application relates to the technical field of electronics, especially, relate to a display screen subassembly and electronic equipment.
Background
Electronic devices such as mobile phones, computers, televisions, and the like generally include a display panel and a driving chip for driving the display panel to operate. The driver chip is typically bonded (bonded) to the display panel. The bonding position of the driving chip and the display panel has contact resistance, and the size of the contact resistance often influences the signal transmission from the driving chip to the display panel. The smaller contact resistance has smaller influence on the signal transmitted to the display panel by the driving chip, and the display effect of the display panel under the driving of the signal transmitted by the driving chip is better. The larger contact resistance has a larger influence on the signal transmitted to the display panel by the driving chip, and the display effect of the display panel under the driving of the signal transmitted by the driving chip is poorer. The large contact resistance may even cause problems of screen blooming, screen blacking, etc. of the display panel. Therefore, it is necessary to detect the contact resistance at the binding between the driving chip and the display panel. When detecting the contact resistance at the binding position between the driving chip and the display panel, the display panel is usually sampled and detected by using an external multimeter. However, the scheme cannot detect all electronic devices, and cannot detect the change of the contact resistance of the display panel and the driving chip after shipment or in the using process of the electronic devices.
SUMMERY OF THE UTILITY MODEL
The application provides a display screen assembly, the display screen assembly includes:
a display panel;
the driving chip is bound with the display panel through a plurality of first binding points and used for driving the display panel to work, the driving chip comprises a first testing pin and a second testing pin, one end of the first testing pin is electrically connected with one end of the second testing pin, and the other end of the first testing pin is electrically connected with the other end of the second testing pin through one of the first binding points and the other first binding point;
the first test unit is electrically connected with one first binding point and is used for providing a first test voltage and a first test current;
the first detection unit is used for detecting the voltage value of the second test pin to obtain a first voltage; and
and the first calculation unit obtains a first resistance value of the first binding point according to the first test voltage, the first voltage and the first test current.
The application also provides an electronic device, which comprises the display screen assembly.
The display screen assembly of this application can be real through configuration driver chip, first test unit, first detecting element, and first test pin, second test pin and the electric connection relation of two first binding points the calculation of the first resistance value of first binding point. In other words, each display screen assembly can realize the calculation of the first resistance value of the first binding point, and has higher detection efficiency. The first resistance value of the first binding point may be detected even after shipment of the display screen assembly or during use of an electronic device to which the display screen assembly is applied.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic view of an electronic device according to an embodiment of the present application.
Fig. 2 is a schematic view of a display screen assembly according to an embodiment of the present application.
Fig. 3 is a schematic circuit diagram of the display panel assembly shown in fig. 2.
Fig. 4 is a schematic view of a display screen assembly according to another embodiment of the present application.
Fig. 5 is a schematic circuit diagram of the display panel assembly shown in fig. 4.
Fig. 6 is a schematic structural diagram of a driving chip according to an embodiment of the present disclosure.
Fig. 7 is a circuit block diagram of the driving chip in fig. 6.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without inventive step, are within the scope of the present disclosure.
Reference herein to "an embodiment" or "an implementation" means that a particular feature, structure, or characteristic described in connection with the embodiment or implementation can be included in at least one embodiment of the application. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is explicitly and implicitly understood by one skilled in the art that the embodiments described herein can be combined with other embodiments.
It should be noted that the terms "first", "second", and the like in the description and claims of the present application and in the above-described drawings are used for distinguishing different objects and not for describing a particular order. Furthermore, the terms "include" and "have," as well as any variations thereof, are intended to cover non-exclusive inclusions.
Referring to fig. 1, fig. 1 is a schematic view of an electronic device according to an embodiment of the present disclosure. The electronic device 1 may be, but is not limited to, a mobile phone, a computer, a television, or the like including the display screen assembly 10. The electronic device 1 includes a display screen assembly 10, a middle frame 30, and a housing 50. The display screen assembly 10 is disposed on one side of the middle frame 30 and supported on the middle frame 30. The housing 50 is disposed at the other side of the middle frame 30, and is used for accommodating and fixing the display screen assembly 10 and the middle frame 30.
The display screen assembly 10 is a device that realizes a display function in the electronic device 1, and may display text, images, play videos, and the like. The specific structure of the display screen assembly 10 will be described in detail later. The material of the middle frame 30 is generally metal, such as aluminum magnesium alloy, and the middle frame 30 constitutes a ground pole in the electronic device 1. The material of the housing 50 may be metal or nonmetal, and is not limited herein. The display screen assembly 10 provided herein is described in detail below. It is to be understood that the above description of the components of the electronic device 1 other than the display screen assembly 10 and the positional relationship and connection relationship between the display screen assembly 10 and the other components is only for the purpose of understanding one possible application of the display screen assembly 10, and does not constitute a limitation to the display screen assembly 10 provided in this application.
Referring to fig. 2 and fig. 3 together, fig. 2 is a schematic view of a display screen assembly according to an embodiment of the present disclosure; fig. 3 is a schematic circuit diagram of the display panel assembly shown in fig. 2. The display screen assembly 10 includes a display panel 110, a driving chip 120, a first testing unit 130, a first detecting unit 140, and a first calculating unit 150. The driving chip 120 is bound to the display panel 110 by a plurality of first binding points 123, and the driving chip 120 is used for driving the display panel 110 to work. The driving chip 120 includes a first test pin 121 and a second test pin 122. One end of the first test pin 121 is electrically connected to one end of the second test pin 122, and the other end of the first test pin 121 is electrically connected to the other end of the second test pin 122 through one of the first binding points 123 and the other first binding point 123. The first test unit 130 is electrically connected to one of the first binding points 123 for providing a first test voltage and a first test current. The first detecting unit 140 is configured to detect a voltage value of the second test pin 122 to obtain a first voltage. The first calculating unit 150 obtains a first resistance value of the first binding point 123 according to the first test voltage, the first voltage and the first test current.
The display panel 110 may be a liquid crystal display panel 110 or an organic light emitting diode display panel. The driving chip 120 is configured to drive the display panel 110 to work, for example, the driving chip 120 is configured to generate signals such as a scan signal and a data signal, and transmit the scan signal and the data signal to the display panel 110 through a plurality of output pins 126 (see fig. 6) to drive the display panel 110 to work. The driving Chip 120 is bonded to the display panel 110 through a bonding process, for example, the driving Chip 120 is bonded to the display panel 110 through a Chip On Glass (COG) technology.
The first test pin 121, one of the first binding points 123, the other first binding point 123, and the second test pin 122 form a series loop. The current values are equal everywhere in the series circuit, i.e. equal to the first test current. When the first test voltage is applied through one of the first binding points 123 and flows to the second test pin 122, the first test voltage is lower than the first test voltage because the driver chip 120 has a contact resistance when bound to the display panel 110, that is, the first binding point 123 has a resistance. The difference between the first test voltage and the first voltage can be considered as the voltage value consumed by the whole loop. For the calculation of the resistance value of the first binding point 123, please refer to the following formula:
RCoG＝(Rtotal-R0) /2 (formula 1)
Wherein R isCoGA first resistance value of the first binding point 123; r0A resistor R for a line in the first loop electrically connecting the first test pin 121 and a first binding point 12301Plus a resistance R of the second test pin 122 and another first binding point 12302Of (i.e., R)0＝R01+R02) Wherein R is0Is a known number; rtotalIs the resistance value of the whole loop. Since the circuit electrically connecting the first test pin 121 and one first binding point 123 is a circuit on the display panel 110, and the circuit electrically connecting the second test pin 122 and another first binding point 123 is also a circuit on the display panel 110, R is a circuit on the display panel 1100Also referred to as the impedance of the lines on the display panel 110.
And for RtotalThe calculation formula is as follows:
Rtotal＝(U11-U12)/I1(formula 2)
Wherein, U11Is a first test voltage, U12Is a first voltage, I1Is a first test current.
As can be seen from the above description, the display panel assembly 10 of the present application can calculate the first resistance value of the first binding point 123 by configuring the driving chip 120, the first testing unit 130, the first detecting unit 140, and the electrical connection relationship among the first testing pin 121, the second testing pin 122, and the two first binding points 123. In other words, each display screen assembly 10 may effect the calculation of the first resistance value of the first binding point 123. The first resistance value of the first binding point 123 may be detected even after shipment of the display screen assembly 10 or during use of the electronic device 1 to which the display screen assembly 10 is applied.
It should be noted that, in the foregoing description, the driving chip 120 further outputs a signal to the display panel 110 through a part of the first binding points 123 in the plurality of first binding points 123, so as to drive the display panel 110 to operate.
It should be noted that, the display screen assembly 10 provided in the present application achieves the effect of detecting the first resistance value of the first binding point 123 by configuring the connection relationship between the display panel 110, the driving chip 120, the first testing unit 130, the first detecting unit 140, and the first calculating unit 150, and the present application does not improve the software algorithm for any one of the display panel 110, the driving chip 120, the first testing unit 130, the first detecting unit 140, and the first calculating unit 150 in the display screen assembly 10, and should not be understood as not complying with the requirement of the patent law on the object to be protected by the present invention.
Referring to fig. 2 again, in the present embodiment, the display panel 110 has a display region 1111 and a non-display region 1112, the non-display region 1112 is disposed around the periphery of the display region 1111, the non-display region 1112 has a first bonding region 1113, and the first test pin 121 and the second test pin 122 are both located in the first bonding region 1113.
The display region 1111 is a region having a display function, and the display region 1111 is a region in the display panel 110 in which images, characters, and video can be displayed. The non-display region 1112 refers to a region having no display function. The non-display region 1112 is generally disposed at a periphery of the display region 1111.
In this embodiment, the first test pin 121 and the second test pin 122 are disposed in the first bonding region 1113 in the non-display region 1112 and do not occupy the area of the display region 1111, so as not to affect the display of the display region 1111 of the display panel 110.
Referring to fig. 3, in the present embodiment, the number of the first test pins 121 is two, and the number of the second test pins 122 is two. One of the first test pins 121 and one of the second test pins 122 form a first test group 1201, the other of the first test pins 121 and the other of the second test pins 122 form a second test group 1202, and the first test group 1201 and the second test group 1202 are arranged at intervals.
In this embodiment, the first test group 1201 and the second test group 1202 may measure the first resistance value of the first binding point 123 at different positions so as to obtain the first resistance value of the first binding point 123 at different positions.
Optionally, the first test group 1201 is disposed on one side of the output pins 126 of the driver chip 120 for outputting scan signals and data signals, and the second test group 1202 is disposed on the other side of the output pins 126. In other words, the first test set 1201 and the second test set 1202 are disposed on opposite sides of the plurality of output pins 126. The above-mentioned positions of the first test set 1201 and the second test set 1202 may enable the first test set 1201 and the second test set 1202 to measure the first resistance value of the first binding point 123 of the edgemost output pin 126. The first test group 1201 and the second test group 1202 are disposed at positions that facilitate the arrangement and the disposition of the first test pins 121 and the second test pins 122. It is understood that, in other embodiments, the first test group 1201 and the second test group 1202 may also be disposed at other positions of the plurality of output pins 126, as long as the first test group 1201 and the second test group 1202 are disposed at intervals, and the first test pin 121 in the first test group 1201 is electrically connected to one binding point, and the second test pin 122 is electrically connected to another first binding point 123; similarly, the first test pins 121 in the second test group 1202 may be electrically connected to one first attachment point 123, and the second test pins 122 may be electrically connected to another first attachment point 123.
In this embodiment, the first test set 1201 and the second test set 1202 are symmetrically disposed. The first test group 1201 and the second test group 1202 are symmetrically arranged, so that the first test group 1201 and the second test group 1202 can be conveniently installed. It is understood that, in other embodiments, the first test set 1201 and the second test set 1202 may be arranged asymmetrically, as long as the first test set 1201 and the second test set 1202 are arranged at intervals.
Referring to fig. 4 and 5 together, fig. 4 is a schematic view of a display screen assembly according to another embodiment of the present application; fig. 5 is a schematic circuit diagram of the display panel assembly shown in fig. 4. In this embodiment, the display screen assembly 10 further includes a flexible circuit board 190, a second testing unit 160, a second detecting unit 170, and a second calculating unit 180. The display screen assembly 10 including the flexible circuit board 190, the second testing unit 160, the second detecting unit 170 and the second calculating unit 180 may be incorporated into the display screen assembly 10 provided in any of the foregoing embodiments. In the schematic diagram of the present embodiment, the display screen assembly 10 includes a flexible circuit board 190, a second testing unit 160, a second detecting unit 170, and a second calculating unit 180, which are combined into the foregoing schematic embodiment. The flexible circuit board 190 is configured to generate an original signal and transmit the original signal to the driving chip 120, and the driving chip 120 generates the driving signal according to the original signal. The flexible circuit board 190 is further provided with a third test pin 191 and a fourth test pin 192 at intervals. The flexible circuit board 190 is bound to the display panel 110 by a plurality of second binding points 193. One end of the third test pin 191 is electrically connected to one end of the fourth test pin 192, and the other end of the third test pin 191 is further electrically connected to a second binding point 193, a first binding point 123, another second binding point 193, and the other end of the fourth test pin 192 in sequence. The second test unit 160 is electrically connected to one of the second binding points 193 for providing a second test voltage and a second test current. The second detecting unit 170 is configured to detect a voltage value of the fourth test pin 192 to obtain a second voltage. The second calculating unit 180 obtains a second resistance value of the second binding point 193 according to the second test voltage, the second test current, the second voltage, and the first resistance value.
The third test pin 191, one second attachment point 193, one first attachment point 123, another second attachment point 193, and the fourth test pin 192 form a series loop. The current values at all points in the series circuit are equal, i.e. equal to the second test current. Since the driver chip 120 and the display panel 110 are bonded to each other to have a first resistance value, and the flexible circuit board 190 and the display panel 110 are bonded to each other to have a second resistance value, the second test voltage is added through the third bonding point and flows through the fourth test pin 192, and the second voltage measured at the fourth test pin 192 is necessarily smaller than the second test voltage.
RFOG＝(Rtotal-R0)/2-RCoG(formula 3)
Wherein R isFOGIs the second resistance value of second binding point 193.
As can be seen from the above description, the display panel assembly 10 of the present application can calculate the second resistance value of the second binding point 193 by configuring the electrical connection relationship among the driving chip 120, the second testing unit 160, the second detecting unit 170, the third testing pin 191, the fourth testing pin 192, the two first binding points 123 and the two second binding points. In other words, each display screen assembly 10 may effect the calculation of the second resistance value of the second binding point 193. The second resistance value of the second binding point 193 can be detected even after shipment of the display screen assembly 10 or during use of the electronic device 1 to which the display screen assembly 10 is applied.
It should be noted that, the display screen assembly 10 provided in the present application achieves the effect of detecting the second resistance value of the second binding point 193 by configuring the connection relationship of the display panel 110, the driving chip 120, the flexible circuit board 190, the second detecting unit 170, the second calculating unit 180, and the like, and the software algorithm improvement is not performed on any one of the components of the display panel 110, the driving chip 120, the flexible circuit board 190, the second detecting unit 160, the second detecting unit 170, and the second calculating unit 180 in the display screen assembly 10, and it should not be understood that the requirements of the patent law on the protection object of the present invention are not met.
Referring to fig. 4 again, the flexible circuit board 190 further has a second bonding region 1114, the second bonding region 1114 is spaced apart from the first bonding region 1113, and the third test pin 191 and the fourth test pin 192 are located in the second bonding region 1114.
In this embodiment, the third test pin 191 and the fourth test pin 192 are disposed in the second bonding region 1114 without occupying the area of the display region 1111, so as not to affect the display of the display region 1111 of the display panel 110.
Referring to fig. 5, in the present embodiment, the number of the third test pins 191 is two, and the number of the fourth test pins 192 is two. One of the third test pins 191 and one of the fourth test pins 192 form a third test group 1901, the other of the third test pins 191 and the other of the fourth test pins 192 form a fourth test group 1902, and the third test group 1901 and the fourth test group 1902 are arranged at intervals.
In this embodiment, the third test set 1901 and the fourth test set 1902 can measure the second resistance value of the second binding point 193 at different locations, so as to obtain the second resistance value of the second binding point 193 at different locations.
Optionally, the third test set 1901 is disposed on one side of the output pins 126 of the driver chip 120 for outputting scan signals and data signals, and the fourth test set 1902 is disposed on the other side of the output pins 126. In other words, the third test set 1901 and the fourth test set 1902 are disposed on opposite sides of the plurality of pins.
The above-mentioned positions of the third test set 1901 and the fourth test set 1902 can enable the third test set 1901 and the fourth test set 1902 to measure a second resistance value of a second binding point of the edge-most output pin 126. The third test group 1901 and the fourth test group 1902 are disposed at positions that facilitate the arrangement and the disposition of the third test pins 191 and the fourth test pins 192. It is understood that, in other embodiments, the third test group 1901 and the fourth test group 1902 may also be disposed at other positions of the plurality of output pins 126, as long as the third test group 1901 and the fourth test group 1902 are disposed at intervals, and the third test pin 191 in the third test group 1901 is electrically connected to one binding point, and the fourth test pin 192 is electrically connected to another second binding point 193; similarly, the third test pin 191 in the fourth test cluster 1902 need only be electrically connected to one second attachment point 193 and the fourth test pin 192 need only be electrically connected to another second attachment point 193.
In this embodiment, the third test set 1901 and the fourth test set 1902 are symmetrically disposed.
The third test set 1901 and the fourth test set 1902 are symmetrically disposed, so that the third test set 1901 and the fourth test set 1902 can be conveniently installed. It is understood that, in other embodiments, the third test set 1901 and the fourth test set 1902 may be disposed asymmetrically, as long as the third test set 1901 and the fourth test set 1902 are disposed at intervals.
In this embodiment, the first binding region 1113 and the second binding region 1114 are both located on the same side of the display region 1111. The first and second bonding regions 1113 and 1114 are located on the same side 12 of the display region 1111, thereby facilitating the setting of the first, second, third, and fourth test pins 121, 122, 191, and 192. It is understood that, in other embodiments, the first binding region 1113 and the second binding region 1114 can be located on different sides of the display region 1111.
Referring to fig. 6 and 7 together, fig. 6 is a schematic structural diagram of a driving chip according to an embodiment of the present disclosure; fig. 7 is a circuit block diagram of the driving chip in fig. 6. The driving chip 120 includes a driving unit 124 and a package 125, the driving unit 124 is disposed in the package 125, the driving unit 124 is used for driving the display panel 110 to operate, and the first testing unit 130, the first detecting unit 140, and the first calculating unit 150 are integrated in the package 125.
The integration of the first testing unit 130, the first detecting unit 140, and the first calculating unit 150 in the package 125 can be beneficial to improve the integration of the driving chip 120.
In addition, in other embodiments, the second testing unit 160, the second detecting unit 170 and the second calculating unit 180 can also be integrated in the package 125.
In other embodiments, the first testing unit 130, the first detecting unit 140, the first calculating unit 150, the second testing unit 160, the second detecting unit 170, and the second calculating unit 180 are integrated in the package 125.
Although embodiments of the present application have been shown and described, it is understood that the above embodiments are illustrative and not restrictive, and that those skilled in the art may make changes, modifications, substitutions and alterations to the above embodiments without departing from the scope of the present application, and that such changes and modifications are also to be considered as within the scope of the present application.
Claims (11)
1. A display screen assembly, the display screen assembly comprising:
a display panel;
the driving chip is bound with the display panel through a plurality of first binding points and used for driving the display panel to work, the driving chip comprises a first testing pin and a second testing pin, one end of the first testing pin is electrically connected with one end of the second testing pin, and the other end of the first testing pin is electrically connected with the other end of the second testing pin through one of the first binding points and the other first binding point;
the first test unit is electrically connected with one first binding point and is used for providing a first test voltage and a first test current;
the first detection unit is used for detecting the voltage value of the second test pin to obtain a first voltage; and
and the first calculation unit obtains a first resistance value of the first binding point according to the first test voltage, the first voltage and the first test current.
2. The display screen assembly of claim 1, wherein the display panel has a display area and a non-display area, the non-display area is surrounded by a periphery of the display area, the non-display area has a first bonding area, and the first test pin and the second test pin are both located in the first bonding area.
3. The display screen assembly of claim 2, wherein the number of the first test pins is two, the number of the second test pins is two, one of the first test pins and one of the second test pins form a first test group, the other of the first test pins and the other of the second test pins form a second test group, and the first test group and the second test group are spaced apart.
4. The display screen assembly of claim 3, wherein the first test set and the second test set are symmetrically disposed.
5. The display screen assembly according to any one of claims 2 to 4, wherein the display screen assembly further comprises a flexible circuit board, a second testing unit, a second detecting unit and a second calculating unit, the flexible circuit board is further provided with a third testing pin and a fourth testing pin which are spaced apart from each other, the flexible circuit board is bound with the display panel through a plurality of second binding points, one end of the third testing pin is electrically connected with one end of the fourth testing pin, and the other end of the third testing pin is further electrically connected with one second binding point, one first binding point, the other second binding point and the other end of the fourth testing pin in sequence;
the second test unit is electrically connected with the second binding point and is used for providing a second test voltage and a second test current;
the second detection unit is used for detecting the voltage value of the fourth test pin to obtain a second voltage;
and the second calculation unit obtains a second resistance value of the second binding point according to the second test voltage, the second test current, the second voltage and the first resistance value.
6. The display screen assembly of claim 5, wherein the flexible circuit board further has a second bonding region, the second bonding region being spaced apart from the first bonding region, the third test pin and the fourth test pin both being located in the second bonding region.
7. The display screen assembly of claim 6, wherein the number of the third test pins is two, the number of the fourth test pins is two, one of the third test pins and one of the fourth test pins form a third test group, the other of the third test pins and the other of the fourth test pins form a fourth test group, and the third test group and the fourth test group are arranged at intervals.
8. The display screen assembly of claim 7, wherein the third test set and the fourth test set are symmetrically disposed.
9. The display screen assembly of claim 6, wherein the first and second binding regions are both located on a same side of the display area.
10. The display screen assembly of claim 1, wherein the driving chip comprises a driving unit and an enclosure, the driving unit is disposed in the enclosure, the driving unit is configured to drive the display panel to operate, and the first testing unit, the first detecting unit, and the first calculating unit are integrated in the enclosure.
11. An electronic device, characterized in that the electronic device comprises a display screen assembly according to any one of claims 1-10.
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| CN202022592518.2U CN213211655U (en) | 2020-11-10 | 2020-11-10 | Display screen assembly and electronic equipment |
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| CN202022592518.2U CN213211655U (en) | 2020-11-10 | 2020-11-10 | Display screen assembly and electronic equipment |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113740607A (en) * | 2021-09-24 | 2021-12-03 | 深圳市华星光电半导体显示技术有限公司 | Resistance testing method and resistance testing device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113740607A (en) * | 2021-09-24 | 2021-12-03 | 深圳市华星光电半导体显示技术有限公司 | Resistance testing method and resistance testing device |
| CN113740607B (en) * | 2021-09-24 | 2023-11-28 | 深圳市华星光电半导体显示技术有限公司 | Resistance testing method and resistance testing device |
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