CN213184320U

CN213184320U - High-efficient N type HIBC solar cell

Info

Publication number: CN213184320U
Application number: CN202021948246.9U
Authority: CN
Inventors: 杜娟; 张敏; 卢刚
Original assignee: Yellow River Hydropower Photovoltaic Industry Technology Co ltd; Qinghai Huanghe Hydropower Development Co Ltd; Huanghe Hydropower Development Co Ltd; Photovoltaic Industry Technology Branch of Qinghai Huanghe Hydropower Development Co Ltd
Current assignee: Yellow River Hydropower Photovoltaic Industry Technology Co ltd; Qinghai Huanghe Hydropower Development Co Ltd; Huanghe Hydropower Development Co Ltd; State Power Investment Corp Ltd Huanghe Hydropower Development Co Ltd; Photovoltaic Industry Technology Branch of Qinghai Huanghe Hydropower Development Co Ltd
Priority date: 2020-09-08
Filing date: 2020-09-08
Publication date: 2021-05-11
Anticipated expiration: 2030-09-08

Abstract

The utility model discloses a high-efficient N type HIBC solar cell, including N type silicon substrate, first intrinsic amorphous silicon layer, N type amorphous silicon layer and subtract anti-layer, and second intrinsic amorphous silicon layer, doping amorphous silicon layer and contact layer, the thickness of N type silicon substrate is 160 ~ 190 μm; the thickness of the first intrinsic amorphous silicon layer is 1-15 nm; the thickness of the N-type amorphous silicon layer is 5-20 nm; the doped amorphous silicon layer comprises P-type amorphous silicon regions and N-type amorphous silicon regions which are alternately arranged at intervals; the thickness of the second intrinsic amorphous silicon layer is 1-15 nm; the thickness of the doped amorphous silicon layer is 0.1-0.4 μm, and the width of the P-type amorphous silicon region is 300-1000 μm; the width of the N-type amorphous silicon region is 80-220 μm, and the width of a gap between adjacent P-type amorphous silicon regions and N-type amorphous silicon regions is 10-50 μm. The utility model discloses aim at promoting the photoelectric conversion efficiency and the quality of battery.

Description

High-efficient N type HIBC solar cell

Technical Field

The utility model relates to a solar cell technical field especially relates to a high-efficient N type HIBC solar cell.

Background

The high-efficiency crystalline silicon solar cell includes: an HIT (Hetero-junction with amorphous silicon/crystalline silicon heterojunction) cell, an IBC (indirect back contact) cell, and the like. The HIT solar cell is a hybrid solar cell made of a crystalline silicon substrate and an amorphous silicon thin film, and has the advantages of symmetrical structure, low-temperature process, good illumination stability, double-sided power generation, good temperature characteristic, and much higher open-circuit voltage than that of a conventional cell, so that high photoelectric conversion efficiency can be obtained. The IBC battery has no electrode on the front side, and the electrode and the PN junction are both designed on the back side, so that the IBC battery completely eliminates the shading loss of the front electrode, thereby realizing the maximization of the number of incident photons, increasing the short-circuit current density of the battery and having high conversion efficiency.

The HIBC (heterojunction-junction back Contact Cell) is a Cell which applies the HIT technology to the IBC structure, and is the combination of the design concepts of HIT and IBC two high-efficiency silicon-based solar cells. Compared with an HIT (heterojunction with intrinsic conductive barrier) cell, the HIBC cell has the greatest characteristic that the front side of the HIBC cell is not provided with grid lines and electrodes, so that the light loss caused by the shielding of the grid lines and the electrodes on sunlight is greatly reduced, the HIBC cell is ensured to have high short-circuit current and high filling factor, and becomes a new development direction of a crystalline silicon cell.

SUMMERY OF THE UTILITY MODEL

In view of the above, the utility model provides a high-efficient N type HIBC solar cell to promote HIBC structure solar cell's photoelectric conversion efficiency and quality.

The utility model provides a concrete technical scheme does: a high efficiency N-type HIBC solar cell, comprising:

an N-type silicon substrate, the thickness of the N-type silicon substrate is 160-190 μm, and the doping concentration is 1 × 10¹⁵～5×10¹⁶cm^-3；

The first intrinsic amorphous silicon layer, the N-type amorphous silicon layer and the antireflection layer are sequentially laminated on the front surface of the N-type silicon substrate from inside to outside; wherein the thickness of the first intrinsic amorphous silicon layer is 1-15 nm; the thickness of the N-type amorphous silicon layer is 5-20 nm, and the doping concentration is 1 multiplied by 10¹⁵～1×10²¹cm^-3；

The second intrinsic amorphous silicon layer, the doped amorphous silicon layer and the contact layer are sequentially laminated on the back surface of the N-type silicon substrate from inside to outside, and the doped layer comprises P-type amorphous silicon regions and N-type amorphous silicon regions which are alternately arranged at intervals; wherein the thickness of the second intrinsic amorphous silicon layer is 1-15 nm; the thickness of the doped amorphous silicon layer is 0.1-0.4 μm, the width of the P-type amorphous silicon region is 300-1000 μm, and the doping concentration is 1 x 10¹⁷～1×10²¹cm^-3(ii) a The N-type amorphous silicon regionHas a width of 80 to 220 μm and a doping concentration of 5 × 10¹⁸～1×10²¹cm^-3And the width of a gap between the adjacent P-type amorphous silicon regions and the adjacent N-type amorphous silicon regions is 10-50 mu m.

Preferably, the thickness of the N-type silicon substrate is 160 μm, and the doping concentration is 3 × 10¹⁵；

The thickness of the first intrinsic amorphous silicon layer is 3 nm; the thickness of the N-type amorphous silicon layer is 5nm, and the doping concentration is 5 multiplied by 10¹⁸cm^-3；

The thickness of the second intrinsic amorphous silicon layer is 3nm, the thickness of the doped amorphous silicon layer is 0.2 μm, the width of the P-type amorphous silicon region is 800 μm, and the doping concentration is 1 × 10¹⁹cm^-3(ii) a The width of the N-type amorphous silicon region is 100 μm, and the doping concentration is 5 × 10¹⁹cm^-3And the gap width between the adjacent P-type amorphous silicon regions and the N-type amorphous silicon regions is 10 μm.

Preferably, the substrate further comprises a first lightly doped N layer arranged between the N-type silicon substrate and the first intrinsic amorphous silicon layer⁺And (3) a layer.

Preferably, the first lightly doped N⁺The doping concentration of the layer is between 1 × 10¹⁷～1×10¹⁸cm^-3The diffusion depth is 0.2 to 1 μm.

Preferably, the semiconductor device further comprises a second lightly doped N deposited on the back surface of the N-type silicon substrate⁺Layer of said second lightly doped N⁺The layer comprises a plurality of local doped N arranged at intervals⁺Regions of each of said local dopings N⁺The region is opposite to the N-type amorphous silicon region and two gaps adjacent to the N-type amorphous silicon region.

Preferably, the second lightly doped N⁺The doping concentration of the layer is between 1 × 10¹⁷～1×10¹⁸cm^-3The diffusion depth is 0.2 to 1 μm.

Preferably, the amorphous silicon substrate further comprises a hydrogenated amorphous silicon oxide layer arranged between the N-type silicon substrate and the second intrinsic amorphous silicon layer.

Preferably, the thickness of the hydrogenated amorphous silicon oxide layer is 1-10 nm.

Preferably, the contact layer is composed of a transparent conductive film layer and a metal electrode layer stack.

Compared with the prior art, the utility model discloses a high-efficient N type HIBC solar cell optimizes through the structure to N type HIBC solar cell, makes its photoelectric conversion rate can reach on 24%, very big promotion solar cell's photoelectric conversion efficiency and quality.

Drawings

Fig. 1 is a schematic diagram of an exemplary high efficiency N-type HIBC solar cell.

Detailed Description

Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the drawings are exemplary and intended to be used for explaining the present invention, and should not be construed as limiting the present invention, and all other embodiments obtained by those skilled in the art without creative efforts based on the embodiments of the present invention belong to the protection scope of the present invention.

In the description of the present invention, it is to be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "circumferential", "radial", and the like, indicate the orientation or positional relationship indicated based on the orientation or positional relationship shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore, should not be construed as limiting the present invention.

Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically limited otherwise.

In the present invention, unless otherwise expressly stated or limited, the terms "mounted," "connected," and "fixed" are to be construed broadly and may, for example, be fixedly connected, detachably connected, or integrally connected: either mechanically or electrically: they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present invention can be understood according to specific situations by those skilled in the art.

In the present disclosure, unless expressly stated or limited otherwise, the first feature "on" or "under" the second feature may comprise direct contact between the first and second features, or may comprise contact between the first and second features not directly. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly under and obliquely below the second feature, or simply meaning that the first feature is at a lesser elevation than the second feature.

Referring to fig. 1, the present invention exemplarily provides a high-efficiency N-type HIBC solar cell, which includes: the N-type silicon substrate comprises an N-type silicon substrate 1, a first intrinsic amorphous silicon layer 2, an N-type amorphous silicon layer 3, an anti-reflection layer 4, a second intrinsic amorphous silicon layer 5, a doped amorphous silicon layer 6 and a contact layer 7, wherein the first intrinsic amorphous silicon layer 2, the N-type amorphous silicon layer 3 and the anti-reflection layer 4 are sequentially stacked on the front surface of the N-type silicon substrate 1 from inside to outside, and the second intrinsic amorphous silicon layer 5, the doped amorphous silicon layer 6 and the contact layer 7 are. As shown in fig. 1, from bottom to top: the silicon substrate comprises a contact layer 7, an amorphous silicon-doped layer 6, a second intrinsic amorphous silicon layer 5, an N-type silicon substrate 1, a first intrinsic amorphous silicon layer 2, an N-type amorphous silicon layer 3 and an antireflection layer 4. The doped amorphous silicon layer 6 includes P-type amorphous silicon regions 61a and N-type amorphous silicon regions 61b alternately and at intervals, wherein a gap 61c is formed between adjacent P-type amorphous silicon regions 61a and N-type amorphous silicon regions 61 b.

Specifically, when the thickness of the N-type silicon substrate 1 is thick, the photo-generated carriers generated by the battery increase, the short-circuit current density increases, and the carrier recombination increases with the increase of the substrate thickness, so that the open-circuit voltage of the battery decreases. Therefore, in order to ensure the maximum cell efficiency, the thickness of the N-type silicon substrate 1 is 160-190 μm, and the doping concentration is 1 × 10¹⁵～5×10¹⁶cm^-3. Preferably, the N-type silicon substrate 1 has a thickness of 160 μm and a doping concentration of 3X 10¹⁵cm^-3This is because the cell efficiency increases and then decreases with increasing doping concentration of the substrate, when the thickness is 160 μm, the doping concentration is 3X 1016cm^-3The cell efficiency is the highest, and the N-type silicon substrate 1 with the thickness also meets the current development trend of thinning, reducing the cost and improving the efficiency.

Specifically, the thickness of the first intrinsic amorphous silicon layer 2 is 1-15 nm, the thickness of the N-type amorphous silicon layer 3 is 5-20 nm, and the doping concentration of the N-type amorphous silicon layer 3 is 1 × 10¹⁵～1×10²¹cm^-3. Preferably, the thickness of the first intrinsic amorphous silicon layer 2 is 3nm, the thickness of the N-type amorphous silicon layer 3 is 5nm, and the doping concentration of the N-type amorphous silicon layer 3 is 5 × 10¹⁸cm^-3。

Specifically, the thickness of the second intrinsic amorphous silicon layer 5 is 1-15 nm, the thickness of the doped amorphous silicon layer 6 is 0.1-0.4 μm, the width of the P-type amorphous silicon region 61a is 300-1000 μm, and the doping concentration is 1 × 10¹⁷～1×10²¹cm^-3(ii) a The width of the N-type amorphous silicon region 61b is 80-220 μm, and the doping concentration is 5 × 10¹⁸～1×10²¹cm^-3The gap width between the adjacent P-type amorphous silicon regions 61a and N-type amorphous silicon regions 61b is 10-50 μm. Preferably, the thickness of the second intrinsic amorphous silicon layer 5 is 3nm, the thickness of the doped amorphous silicon layer 6 is 0.2 μm, the width of the P-type amorphous silicon region 61a is 800 μm, and the doping concentration is 1 × 10¹⁹cm^-3(ii) a The width of the N-type amorphous Si region 61b is 100 μm and the doping concentration is 5X 10¹⁹cm^-3A gap width between the adjacent P-type amorphous silicon regions 61a and N-type amorphous silicon regions 61b is 10 μm.

The performance of the high-efficiency N-type HIBC solar cell obtained based on the method is as follows: jsc (short-circuit current) ═ 38.95mA/cm²Voc (open circuit voltage) is 7,41.7mV, FF (fill factor) is 84.7, and Eff (conversion efficiency) is 24.53%. Therefore, the photoelectric conversion efficiency of the high-efficiency N-type HIBC solar cell of the utility model reaches more than 24 percent.

The N-type amorphous silicon layer realizes field passivation, and has the defects that the generation rate of positive photo-generated carriers is high, the service life of the photo-generated carriers generated by light absorption of the amorphous silicon layer is very short, and effective photo-generated current is difficult to form, so that the short-circuit current density is reduced, the short-wave effect is reduced, and the optical loss is increased.

Therefore, the high-efficiency N-type HIBC solar cell of the present invention is provided with a first lightly doped N + layer 8 between the N-type silicon substrate 1 and the first intrinsic amorphous silicon layer 2 on the basis of the above structure. Illustratively, the doping concentration of the first lightly doped N + layer 8 is between 1 × 10¹⁷～1×10¹⁸cm^-3The diffusion depth is 0.2 to 1 μm. By arranging the first lightly doped N + layer 8 between the N-type silicon substrate 1 and the first intrinsic amorphous silicon layer 2, the first lightly doped N + layer 8 can realize partial field passivation function, the thickness of the N-type amorphous silicon layer 3 on the front surface can be reduced, and the light absorption and light loss of the N-type amorphous silicon layer 3 are reduced. Meanwhile, the first lightly doped N + layer 8 can also provide a transverse low-resistance conducting channel of a photon-generated carrier, so that the series resistance loss is reduced, the short-circuit current and the filling factor of the battery are improved, and the photoelectric conversion efficiency of the battery is effectively further improved.

Further, a second lightly doped N + layer 9 is deposited on the back surface of the N-type silicon substrate 1, the second lightly doped N + layer 9 includes a plurality of local doped N + regions 91 arranged at intervals, and each local doped N + region 91 is directly opposite to one N-type amorphous silicon region 61b and two gaps 61c adjacent to the N-type amorphous silicon region 61 b. That is, the width E3 of the local doped N + region 91 is equal to the sum of the width E1 of the N-type amorphous silicon region 61B and the width E2 of the gap 61c on two sides adjacent to the N-type amorphous silicon region 61B, i.e., E3 — E1+2E 2.

Illustratively, the doping concentration of the second lightly doped N + layer 9 is between 1 × 10¹⁷～1×10¹⁸cm^-3The diffusion depth is 0.2 to 1 μm. In this embodiment, the second lightly doped N + layer 9 enhances the field passivation effect of the back N-type amorphous silicon, reduces the recombination rate of photon-generated carriers, and improves the open-circuit voltage of the cell; on the other hand, a transverse low-resistance conductive channel of a photon-generated carrier is provided, so that series resistance loss is reduced, the filling factor of the cell is improved, and the photoelectric conversion efficiency of the cell is improved.

In addition, due to the introduction of the intrinsic amorphous silicon layer, the series resistance of the HIBC battery is increased, and the filling factor is reduced; epitaxial silicon is generated when the intrinsic amorphous silicon layer is deposited by adopting a plasma enhanced chemical vapor deposition process, so that the interface performance of the intrinsic amorphous silicon layer and the silicon substrate is damaged, the passivation capability is reduced, and the photoelectric conversion efficiency of the HIBC cell is reduced. For this, a hydrogenated amorphous silicon oxide layer 10 is disposed between the N-type silicon substrate 1 and the second intrinsic amorphous silicon layer 5. Illustratively, the hydrogenated amorphous silicon oxide layer 10 has a thickness of 1 to 10 nm. A hydrogenated amorphous silicon oxide layer 10 is arranged between an N-type silicon substrate 1 and a second intrinsic amorphous silicon layer 5 of the HIBC battery, so that the interface passivation effect of the HIBC battery is improved, the increase of series resistance and the reduction of filling factors of the HIBC battery caused by the introduction of the intrinsic amorphous silicon layer are restrained, and the photoelectric conversion efficiency of the HIBC battery is further improved.

Since the passivation layer and the carrier transport layer are amorphous silicon thin films, which results in very poor conductivity, it is preferable that the contact layer 7 is composed of a stack of a transparent conductive film layer 71 and a metal electrode layer 72 in order to conduct the emitted electricity. In order to increase the light transmission and reduce the reflection and absorption, the transparent conductive thin film layer 71 should have both high light transmittance and anti-reflection properties. At present, the technology of using indium tin oxide as the material of the transparent conductive film layer is mature, and the resistivity of indium tin oxide is low, but the temperature of the manufacturing process of the indium tin oxide transparent conductive film layer 71 requires 200 ℃, and an excessively high manufacturing temperature can damage the performance of the amorphous silicon thin film layer to further damage the PN junction in the manufacturing process, and influence the passivation effect of the amorphous silicon thin film layer on the substrate layer, thereby influencing the battery performance.

Therefore, the transparent conductive film layer 71 is a multilayer film structure which is stacked, and is arranged in the order of the grain size from the doped amorphous silicon layer 6 from small to large, the film layer close to the doped amorphous silicon layer 6 is processed into an integral film structure from the processing temperature below 200 ℃, and the film layer far from the doped amorphous silicon layer 6 is processed into an integral film structure from the processing temperature above 200 ℃. Illustratively, the transparent conductive film 71 includes a first film 71a and a second film 71b stacked together, the first film 71a is close to the doped amorphous silicon layer 6, the second film 71b is disposed on the first film 71a and away from the doped amorphous silicon layer 6, the first film is processed at a processing temperature below 200 ℃, and the second film 71b is processed at a processing temperature above 200 ℃.

Through processing out multilayer printing opacity conducting layer with the processing temperature that increases progressively, can use lower temperature when processing the printing opacity conducting layer of hugging closely doping amorphous silicon layer 6 like this, and can use higher temperature when processing remaining printing opacity conducting layer, PN junction can not be harmd to such technology, can not influence the passivation effect of amorphous silicon rete to the substrate layer, has obtained low carrier recombination rate and better PN junction performance from this, improves the open-circuit voltage and the fill factor of battery, and then improves the conversion efficiency of heterojunction battery piece. Meanwhile, the higher temperature can be used when the rest transparent conducting layer is processed, and a part of the transparent conducting layer is processed at the higher temperature, so that other overall performances of the transparent conducting layer can be ensured.

The utility model discloses a high-efficient N type HIBC solar cell optimizes through the structure to N type HIBC solar cell, makes its photoelectric conversion rate can reach on 24%, very big promotion solar cell's photoelectric conversion efficiency and quality.

In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.

The above only be the preferred embodiment of the utility model discloses a not consequently restriction the utility model discloses a patent range, all are in the utility model discloses a conceive, utilize the equivalent structure transform of what the content was done in the description and the attached drawing, or direct/indirect application all is included in other relevant technical field the utility model discloses a patent protection within range.

Claims

1. A high efficiency N-type HIBC solar cell, comprising:

the N-type silicon substrate is 160-190 microns thick;

the first intrinsic amorphous silicon layer, the N-type amorphous silicon layer and the antireflection layer are sequentially laminated on the front surface of the N-type silicon substrate from inside to outside; wherein the thickness of the first intrinsic amorphous silicon layer is 1-15 nm; the thickness of the N-type amorphous silicon layer is 5-20 nm;

the second intrinsic amorphous silicon layer, the doped amorphous silicon layer and the contact layer are sequentially laminated on the back surface of the N-type silicon substrate from inside to outside, and the doped amorphous silicon layer comprises P-type amorphous silicon regions and N-type amorphous silicon regions which are alternately arranged at intervals; wherein the thickness of the second intrinsic amorphous silicon layer is 1-15 nm; the thickness of the doped amorphous silicon layer is 0.1-0.4 mu m, and the width of the P-type amorphous silicon region is 300-1000 mu m; the width of the N-type amorphous silicon region is 80-220 mu m, and the width of a gap between the adjacent P-type amorphous silicon region and the N-type amorphous silicon region is 10-50 mu m.

2. The high efficiency N-type HIBC solar cell of claim 1 wherein the thickness of the N-type silicon substrate is 160 μ ι η;

the thickness of the first intrinsic amorphous silicon layer is 3 nm; the thickness of the N-type amorphous silicon layer is 5 nm;

the thickness of the second intrinsic amorphous silicon layer is 3nm, the thickness of the doped amorphous silicon layer is 0.2 μm, and the width of the P-type amorphous silicon region is 800 μm; the width of the N-type amorphous silicon region is 100 μm, and the width of a gap between the adjacent P-type amorphous silicon regions and the N-type amorphous silicon region is 10 μm.

3. The high efficiency N-type HIBC solar cell of claim 1, further comprising a first lightly doped N-type silicon substrate disposed between the N-type silicon substrate and the first intrinsic amorphous silicon layer⁺And (3) a layer.

4. The high efficiency N-type HIBC solar cell of claim 3, wherein the first lightly doped N-type⁺The diffusion depth of the layer is 0.2 to 1 μm.

5. The high efficiency N-type HIBC solar cell of claim 3, further comprising a second lightly doped N-type deposited on the back side of said N-type silicon substrate⁺Layer of said second lightly doped N⁺The layer comprises a plurality of local doped N arranged at intervals⁺Regions of each of said local dopings N⁺The region is opposite to the N-type amorphous silicon region and two gaps adjacent to the N-type amorphous silicon region.

6. The high efficiency N-type HIBC solar cell of claim 5, wherein the second lightly doped N-type⁺The diffusion depth of the layer is 0.2 to 1 μm.

7. The high efficiency N-type HIBC solar cell of claim 3 or 5, further comprising a hydrogenated amorphous silicon oxide layer disposed between said N-type silicon substrate and said second intrinsic amorphous silicon layer.

8. The high efficiency N-type HIBC solar cell of claim 7, wherein the thickness of said hydrogenated amorphous silicon oxide layer is 1-10 nm.

9. The high efficiency N-type HIBC solar cell of claim 1 wherein the contact layer is comprised of a transparent conductive film layer and a metal electrode layer stack.