CN213124447U - Thin film transistor, array substrate and display panel - Google Patents
Thin film transistor, array substrate and display panel Download PDFInfo
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- CN213124447U CN213124447U CN202022623894.3U CN202022623894U CN213124447U CN 213124447 U CN213124447 U CN 213124447U CN 202022623894 U CN202022623894 U CN 202022623894U CN 213124447 U CN213124447 U CN 213124447U
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Abstract
The present disclosure provides a thin film transistor, an array substrate and a display panel, the thin film transistor including: the semiconductor device comprises a substrate, a buffer layer, a grid electrode, a shielding layer, a grid insulating layer, an active layer and a source drain conducting layer, wherein the buffer layer is arranged on one side of the substrate; the gate is arranged on one side of the buffer layer, which is far away from the substrate, and the orthographic projection of the buffer layer on the substrate comprises an overlapping part overlapping with the orthographic projection of the gate on the substrate and a non-overlapping part positioned outside the overlapping part; the shielding layer is arranged on one side of the buffer layer, which is far away from the substrate, and the orthographic projection of the grid electrode on the substrate at least covers part of the non-overlapping part of the buffer layer in the orthographic projection on the substrate; the gate insulating layer is arranged on one side of the gate electrode, which is far away from the substrate, and the orthographic projection of the buffer layer, the gate electrode and the shielding layer on the substrate is covered by the orthographic projection of the gate insulating layer on the substrate; the active layer is arranged on one side of the gate insulating layer, which is far away from the substrate; the source-drain conducting layer is arranged on one side, away from the substrate, of the active layer. The thin film transistor provided by the disclosure avoids leakage current of the active layer caused by illumination passing through the buffer layer.
Description
Technical Field
The disclosure relates to the technical field of display, in particular to a thin film transistor, an array substrate and a display panel.
Background
A TFT-LCD (Thin film transistor liquid crystal display) is very popular as a display device having a high display effect and low power consumption. In order to meet the demand of the market for LCD, the panel factory needs to increase its own capacity continuously, and the 1+4Mask product will be changed to 0+4Mask design, i.e. ITO and Gate layer share one Mask, which is expected to increase the TV capacity by about 20%. Therefore, the introduction of the 0+4Mask technology into mass production becomes inevitable.
However, the 1+4Mask product will be transferred to the 0+4Mask design, which will cause the problem of silicon island leakage current.
It is to be noted that the information disclosed in the above background section is only for enhancement of understanding of the background of the present disclosure, and thus may include information that does not constitute prior art known to those of ordinary skill in the art.
Disclosure of Invention
An object of the present disclosure is to provide a thin film transistor, an array substrate and a display panel, which can prevent light from passing through a buffer layer to cause leakage current in an active layer.
According to an aspect of the present disclosure, there is provided a thin film transistor including:
a substrate;
the buffer layer is arranged on one side of the substrate;
the grid electrode is arranged on one side of the buffer layer, which is far away from the substrate, and the orthographic projection of the buffer layer on the substrate comprises an overlapping part which is overlapped with the orthographic projection of the grid electrode on the substrate and a non-overlapping part which is positioned outside the overlapping part;
the shielding layer is arranged on one side of the buffer layer, which is far away from the substrate, and the orthographic projection of the shielding layer on the substrate at least covers part of the non-overlapping part of the orthographic projection of the buffer layer on the substrate;
the grid insulating layer is arranged on one side of the grid electrode, which is far away from the substrate, and the orthographic projection of the grid electrode on the substrate covers the orthographic projection of the buffer layer, the grid electrode and the shielding layer on the substrate;
the active layer is arranged on one side, away from the substrate, of the gate insulating layer;
and the source drain conducting layer is arranged on one side of the active layer, which deviates from the substrate.
In an exemplary embodiment of the present disclosure, an orthographic projection of the blocking layer on the gate electrode on the substrate covers the non-overlapping portion in an orthographic projection of the buffer layer on the substrate.
In an exemplary embodiment of the disclosure, the shielding layer is disposed on a side of the gate electrode away from the substrate, and an orthographic projection of the gate electrode on the substrate covers the buffer layer and an orthographic projection of the gate electrode on the substrate.
In an exemplary embodiment of the present disclosure, an orthographic projection of the buffer layer on the substrate covers an orthographic projection of the gate electrode on the substrate.
In one exemplary embodiment of the present disclosure, the gate insulating layer includes:
the first sub-grid insulating layer is arranged on one side of the substrate and comprises an open area, and the buffer layer, the grid electrode and the shielding layer are positioned in the open area;
the second sub-gate insulating layer is arranged on one side, away from the substrate, of the first sub-gate insulating layer, and the orthographic projection of the gate electrode on the substrate covers the orthographic projection of the buffer layer, the gate electrode and the shielding layer on the substrate; the active layer is arranged on one side, away from the substrate, of the second sub-gate insulating layer.
In an exemplary embodiment of the disclosure, at least a partial area of the sidewall of the opening region is covered with the shielding layer.
In an exemplary embodiment of the present disclosure, the shielding layer is a metal shielding layer.
In an exemplary embodiment of the disclosure, the thickness of the shielding layer in a direction away from the substrate is
According to another aspect of the present disclosure, an array substrate is provided, which includes the thin film transistor described above.
According to still another aspect of the present disclosure, a display panel is provided, which includes the array substrate described above.
The thin film transistor provided by the disclosure is characterized in that the shielding layer is arranged, the orthographic projection of the grid electrode on the substrate at least covers the non-overlapping part of the partial buffer layer in the orthographic projection of the substrate, namely the part which is not covered by the grid electrode, and the shielding layer is matched with the grid electrode to form the covering of the buffer layer, so that when the thin film transistor is applied to a display panel, the light of a backlight source irradiates an active layer through the buffer layer, the active layer generates leakage current under illumination, the reliability and the product yield of the display panel applying the thin film transistor are improved, and the display panel can be manufactured by adopting a 0+4Mask process. In addition, by arranging the shielding layer, electromigration or metal (such as Cu) diffusion of the active layer can be avoided, so that the short circuit (DGS) defect of the grid line and the data line is improved.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and together with the description, serve to explain the principles of the disclosure. It is to be understood that the drawings in the following description are merely exemplary of the disclosure, and that other drawings may be derived from those drawings by one of ordinary skill in the art without the exercise of inventive faculty.
Fig. 1 is a schematic diagram of a thin film transistor provided in an embodiment of the present disclosure;
fig. 2 to 12 are process diagrams for manufacturing the thin film transistor according to the embodiment of fig. 1.
Detailed Description
Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and thus their detailed description will be omitted.
Although relative terms, such as "upper" and "lower," may be used in this specification to describe one element of an icon relative to another, these terms are used in this specification for convenience only, e.g., in accordance with the orientation of the examples described in the figures. It will be appreciated that if the device of the icon were turned upside down, the element described as "upper" would become the element "lower". When a structure is "on" another structure, it may mean that the structure is integrally formed with the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure via another structure.
The terms "a," "an," "the," "said" are used to indicate the presence of one or more elements/components/etc.; the terms "comprising" and "having" are intended to be inclusive and mean that there may be additional elements/components/etc. other than the listed elements/components/etc.; the terms "first" and "second" are used merely as labels, and are not limiting on the number of their objects.
At present, in order to increase the throughput of the panel factory, the 1+4Mask product is converted to the 0+4Mask design, i.e. the ITO (indium tin oxide) layer and the Gate (Gate) layer share one Mask. However, the 0+4Mask process always has the presence of an ITO layer Tail (the portion not covered by the Gate, with a single side width of about 1.2 μm to 1.5 μm). Because both ITO and Gate are conductive, in order not to increase Panel load, the bus width of Gate + ITO Tail should be consistent with the Gate line width of 1+4Mask process, i.e. 0+4Mask Gate metal line is narrower than 1+4Mask, so that the silicon island on the upper layer is closer to the Gate edge, the metal shading effect of the Gate layer is reduced, and finally the silicon island leakage current is higher due to illumination.
Embodiments of the present disclosure first provide a thin film transistor, as shown in fig. 1, including: the semiconductor device comprises a substrate 10, a buffer layer 20, a gate 30, a shielding layer 50, a gate insulating layer 40, an active layer 60 and a source-drain conducting layer 70, wherein the buffer layer 20 is arranged on one side of the substrate 10; the gate 30 is arranged on a side of the buffer layer 20 away from the substrate 10, and an orthographic projection of the buffer layer 20 on the substrate 10 comprises an overlapping part overlapping with an orthographic projection of the gate 30 on the substrate 10 and a non-overlapping part outside the overlapping part; the shielding layer 50 is arranged on a side of the buffer layer 20 away from the substrate 10, and at least a part of the non-overlapping part of the buffer layer 20 in the orthographic projection of the gate 30 on the substrate 10 is covered; the gate insulating layer 40 is arranged on one side of the gate 30, which is far away from the substrate 10, and the orthographic projection of the buffer layer 20, the gate 30 and the shielding layer 50 on the substrate 10 is covered by the orthographic projection on the substrate 10; the active layer 60 is arranged on the side of the gate insulating layer 40 away from the substrate 10; the source-drain conductive layer 70 is disposed on a side of the active layer 60 facing away from the substrate 10.
According to the thin film transistor provided by the disclosure, by arranging the shielding layer 50, the shielding layer 50 at least covers the non-overlapping part of the buffer layer 20 in the orthographic projection of the gate 30 on the substrate 10, namely the part of the buffer layer 20 which is not covered by the gate 30, and the shielding layer 50 and the gate 30 are matched to form the coverage of the buffer layer 20, when the thin film transistor is applied to a display panel, light of a backlight source is irradiated on the active layer 60 through the buffer layer 20, so that the active layer 60 (silicon island) generates leakage current under illumination, the reliability and the product yield of the display panel applying the thin film transistor are improved, and the display panel can be manufactured by adopting a 0+4Mask process. In addition, by providing the shielding layer 50, diffusion of a metal (e.g., Cu) can be prevented, thereby improving a short circuit (DGS) failure of the gate line and the data line.
Specifically, as shown in fig. 1, an orthographic projection of the buffer layer 20 on the substrate 10 covers an orthographic projection of the gate electrode 30 on the substrate 10. Due to the 0+4Mask process, there is a portion of the edge of the buffer layer 20 that is not covered by the gate electrode 30, and the width of the edge that is not covered by the gate electrode 30 is about 1.2 μm to 1.5 μm.
The material of the buffer layer 20 includes ITO (indium tin oxide), which is a transparent material, and the adhesive force of the gate 30 on the substrate 10 can be improved by the buffer layer 20, so that the gate 30 is prevented from falling off. Buffer layer 20 may also be other materials such as tantalum, titanium, molybdenum, niobium, or alloys thereof, as the present disclosure is not limited in this respect.
Specifically, as shown in fig. 1, the non-overlapping portion of the buffer layer 20 in the orthographic projection of the gate electrode 30 on the substrate 10 is covered by the shielding layer 50, that is, the shielding layer 50 completely covers the portion of the buffer layer 20 not covered by the gate electrode 30, and the shielding layer 50 and the gate electrode 30 cooperate to completely cover the buffer layer 20, so as to prevent light from passing through the buffer layer 20 and irradiating the active layer 60, further improve the shielding effect, further avoid the increase of the leakage current of the active layer 60, and further improve the reliability and the product yield of the display panel using the thin film transistor.
Specifically, as shown in fig. 1, the shielding layer 50 is disposed on a side of the gate 30 away from the substrate 10, and an orthographic projection of the gate 30 on the substrate 10 covers the buffer layer 20 and an orthographic projection of the gate 30 on the substrate 10, that is, the shielding layer 50 covers the gate 30 and the buffer layer 20. By covering the gate electrode 30 and the buffer layer 20 with the shielding layer 50, diffusion of a metal (e.g., Cu) can be prevented when the shielding layer 50 serves as a shield, thereby improving short circuit (DGS) failure of the gate line and the data line.
Specifically, as shown in fig. 1, the gate insulating layer 40 includes: a first sub-gate insulating layer 40 and a second sub-gate insulating layer 40. The first sub-gate insulating layer 40 is disposed on one side of the substrate 10 and includes an open region, and the cap buffer layer 20, the gate electrode 30 and the shielding layer 50 are disposed in the open region; the second sub-gate insulating layer 40 is arranged on one side of the first sub-gate insulating layer 40, which is far away from the substrate 10, and covers the orthographic projection of the buffer layer 20, the gate 30 and the shielding layer 50 on the substrate 10 in the orthographic projection of the gate 30 on the substrate 10; the active layer 60 is disposed on a side of the second sub-gate insulating layer 40 facing away from the substrate 10.
Specifically, as shown in fig. 1, at least a partial area of the sidewall of the opening region is covered with the shielding layer 50. By covering the shielding layer 50 on at least a partial region of the sidewall of the opening region, the light shielding effect of the shielding layer 50 can be further improved, thereby further preventing the increase of the leakage current of the active layer 60.
Illustratively, the material of the shielding layer 50 is at least one of copper, aluminum, molybdenum, titanium, chromium, and tungsten; in addition, the shielding layer 50 may be a single-layer metal structure, or a multi-layer metal structure, for example, a multi-layer metal of molybdenum, aluminum, and molybdenum, a multi-layer metal of titanium, copper, and titanium, or a multi-layer metal of molybdenum, titanium, and copper may be used, the material of the shielding layer 50 may also be a non-metal material, and the material of the shielding layer 50 may have a certain shielding effect on light.
Wherein, in the direction of the shielding layer 50 departing from the substrate 10, the thickness of the shielding layer 50 is
For example
Etc., not specifically listed here, but of course, the thickness of the shielding layer 50 may be smaller than that
Or greater than
The present disclosure is not so limited.
Next, a manufacturing process for forming the thin film transistor will be described in detail.
As shown in fig. 2, a substrate 10 is provided, and the substrate 10 may be a transparent substrate, such as a glass material, for example, soda lime glass, quartz glass, sapphire glass, etc. The buffer layer 20 and the gate electrode 30 are formed on the substrate 10 through a 0+4mask process. Wherein, the material of the gate 30 may include a metal, a conductive oxide, or a combination thereof, the metal may be titanium, platinum, ruthenium, gold, silver, molybdenum, aluminum, tungsten, copper, neodymium, chromium, tantalum, or an alloy thereof, or a combination thereof, the conductive oxide may be IZO, AZO, ITO, GZO, ZTO, or a combination thereof, the gate 30 may be formed by a Physical Vapor Deposition (PVD), a Chemical Vapor Deposition (CVD), a spin coating (spin coating), or a combination thereof;
as shown in fig. 3, the first gate insulating layer 410 may be formed by a physical vapor deposition method, a chemical vapor deposition method, a spin coating method, or a combination thereof, and the first gate insulating layer 410 covers the gate electrode 30 and the buffer layer 20. The material of the first gate insulating layer 410 may be silicon oxide, silicon oxynitride, silicon nitride, or other suitable insulating substances (e.g., organic polymer compounds), or a combination thereof;
as shown in fig. 4, a self-aligned first gate insulating layer 410Mask is performed on the basis of fig. 3, that is, a negative photoresist (PR glue) 80 is coated on the entire glass substrate, and during exposure, a Mask is not required, and only light with the same wavelength and the same intensity as those of the original design is used for scanning the back surface of the glass substrate, so that a patterned first gate insulating layer 410 can be formed, and the result after developing the photoresist Mask is shown in fig. 5.
The Gate is made of materials such as Cu or Al, the two materials are light-tight materials, the properties of the two materials cannot be changed under the condition of light irradiation, and the two materials serve as a Mask of the first Gate insulating layer during backlight irradiation. After the negative PR paste is coated on the first Gate insulating layer 410, due to the characteristic that an exposed portion of the negative PR paste is left, after exposure, no PR paste is left in a portion shielded by Gate, and no PR paste is left in an area not shielded;
as shown in fig. 6 and 7, on the basis of fig. 5, a first gate insulating layer 410 etching and developing process is performed to form a first gate insulating layer trench on the gate electrode 30;
as shown in fig. 8, a deposition (Dep) process of the barrier layer 50 is performed on the basis of fig. 7;
as shown in fig. 9 and 10, on the basis of fig. 8, a PR Ashing process is performed to ensure that the photoresist 80 above the trench of the first gate insulating layer 410 is still partially remained and the photoresist above the trench is ashed;
as shown in fig. 11, on the basis of fig. 10, an etching process of the shielding layer 50 is performed, such that the shielding layer material outside the trench is etched away, and the shielding layer material inside the trench remains;
as shown in fig. 12, a second gate insulating layer 420 is formed in addition to fig. 11. The material of the second gate insulating layer 420 may be silicon oxide, silicon oxynitride, silicon nitride, or other suitable insulating substances (e.g., organic polymer compounds), or a combination thereof;
as shown in fig. 1, in addition to fig. 12, the active layer 60 and the source/drain conductive layer 70 are processed, and the source/drain conductive layer 70 includes a source electrode 710 and a drain electrode 720. The material of the active layer 60 may be amorphous silicon, polycrystalline silicon, microcrystalline silicon, single crystal silicon, an oxide semiconductor material, an organic silicon material, an organic oxide semiconductor material, or a combination thereof, and the active layer 60 may be formed by a physical vapor deposition method, a chemical vapor deposition method, or a combination thereof. The material of the source-drain conductive layer 70 may include a metal, a conductive oxide, or a combination thereof, the metal may be titanium, platinum, ruthenium, gold, silver, molybdenum, aluminum, tungsten, copper, neodymium, chromium, tantalum, or an alloy thereof, or a combination thereof, the conductive oxide may be IZO, AZO, ITO, GZO, ZTO, or a combination thereof, and the gate electrode 30 may be formed by, for example, a physical vapor deposition method, a chemical vapor deposition method, a spin coating method, or a combination thereof.
The embodiment of the present disclosure also provides an array substrate, which includes the thin film transistor.
The embodiment of the present disclosure also provides a display panel, which includes the array substrate. The display panel may be a TFT-LCD display panel, and its type is not particularly limited. The display panel can be used in a mobile phone, a tablet computer or other terminal devices, and the beneficial effects of the display panel can be referred to the beneficial effects of the thin film transistor, which are not described in detail herein.
Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.
It will be understood that the present disclosure is not limited to the precise arrangements described above and shown in the drawings and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.
Claims (10)
1. A thin film transistor, comprising:
a substrate;
the buffer layer is arranged on one side of the substrate;
the grid electrode is arranged on one side of the buffer layer, which is far away from the substrate, and the orthographic projection of the buffer layer on the substrate comprises an overlapping part which is overlapped with the orthographic projection of the grid electrode on the substrate and a non-overlapping part which is positioned outside the overlapping part;
the shielding layer is arranged on one side of the buffer layer, which is far away from the substrate, and the orthographic projection of the shielding layer on the substrate at least covers part of the non-overlapping part of the orthographic projection of the buffer layer on the substrate;
the grid insulating layer is arranged on one side of the grid electrode, which is far away from the substrate, and the orthographic projection of the grid electrode on the substrate covers the orthographic projection of the buffer layer, the grid electrode and the shielding layer on the substrate;
the active layer is arranged on one side, away from the substrate, of the gate insulating layer;
and the source drain conducting layer is arranged on one side of the active layer, which deviates from the substrate.
2. The thin film transistor according to claim 1, wherein an orthographic projection of the barrier layer on the substrate covers the non-overlapping portion in an orthographic projection of the buffer layer on the substrate.
3. The thin film transistor of claim 1, wherein the shielding layer is disposed on a side of the gate electrode facing away from the substrate, and an orthographic projection of the gate electrode on the substrate covers an orthographic projection of the buffer layer and the gate electrode on the substrate.
4. The thin film transistor of claim 1, wherein an orthographic projection of the buffer layer on the substrate covers an orthographic projection of the gate electrode on the substrate.
5. The thin film transistor according to claim 1, wherein the gate insulating layer comprises:
the first sub-grid insulating layer is arranged on one side of the substrate and comprises an open area, and the buffer layer, the grid electrode and the shielding layer are positioned in the open area;
the second sub-gate insulating layer is arranged on one side, away from the substrate, of the first sub-gate insulating layer, and the orthographic projection of the gate electrode on the substrate covers the orthographic projection of the buffer layer, the gate electrode and the shielding layer on the substrate; the active layer is arranged on one side, away from the substrate, of the second sub-gate insulating layer.
6. The thin film transistor according to claim 5, wherein at least a partial region of a sidewall of the opening region is covered with the shielding layer.
7. The thin film transistor according to claim 1, wherein the shielding layer is a metal shielding layer.
8. The thin film transistor according to claim 1, wherein the thickness of the shielding layer in a direction away from the substrate is
9. An array substrate comprising the thin film transistor according to any one of claims 1 to 8.
10. A display panel comprising the array substrate according to claim 9.
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| CN202022623894.3U CN213124447U (en) | 2020-11-13 | 2020-11-13 | Thin film transistor, array substrate and display panel |
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| CN202022623894.3U CN213124447U (en) | 2020-11-13 | 2020-11-13 | Thin film transistor, array substrate and display panel |
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