CN213123730U - Light-emitting scanning signal line drive circuit, display panel and electronic device - Google Patents
Light-emitting scanning signal line drive circuit, display panel and electronic device Download PDFInfo
- Publication number
- CN213123730U CN213123730U CN202021248238.3U CN202021248238U CN213123730U CN 213123730 U CN213123730 U CN 213123730U CN 202021248238 U CN202021248238 U CN 202021248238U CN 213123730 U CN213123730 U CN 213123730U
- Authority
- CN
- China
- Prior art keywords
- transistor
- electrode
- electrically connected
- gate
- pull
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Landscapes
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
The application provides a light-emitting scanning signal line drive circuit, and the light-emitting scanning signal line drive circuit includes: the circuit comprises an enabling signal generating circuit and an adjusting circuit, wherein the enabling signal generating circuit is used for receiving a first voltage signal and comprises a pull-up point position, a pull-down point position and an output terminal, the pull-up point position is electrically connected with the adjusting circuit, the pull-down point position is electrically connected with the adjusting circuit, the adjusting circuit is used for receiving a second voltage signal and inputting the second voltage signal to the enabling signal generating circuit, the enabling signal generating circuit generates a high-potential enabling signal according to the first voltage signal and the second voltage signal and outputs the high-potential enabling signal through the output terminal, and the voltage value of the second voltage signal is larger than that of the first voltage signal. The adjusting circuit adjusts the leakage current of the enabling signal generating circuit according to the second voltage signal, so that the leakage current is reduced, and the enabling signal generated by the enabling signal generating circuit is kept stable. The application also provides a display panel and an electronic device.
Description
Technical Field
The present disclosure relates to display technologies, and particularly to a light-emitting scanning signal driving circuit, a display panel and an electronic device.
Background
Display technology of electronic devices has been one of the major research directions. In general, a display panel includes a light emitting scan signal driving circuit that outputs an enable signal to drive light emitting cells in the display panel to emit light.
At present, in a high temperature environment, due to the device characteristics of the thin film transistor, the threshold voltage is negatively biased, and the leakage current is increased, so that when the light emitting scanning signal driving circuit outputs an enable signal, the voltage value of the output enable signal is reduced, which causes the brightness change of the light emitting unit, and causes the abnormal display phenomenon of the display panel.
SUMMERY OF THE UTILITY MODEL
The application discloses luminous scanning signal line drive circuit can solve the technical problem that when luminous scanning signal drive circuit outputs an enable signal, the voltage value of the output enable signal is reduced.
In a first aspect, the present application provides a light-emitting scanning signal line driving circuit applied to a display panel, the light-emitting scanning signal line driving circuit including: the circuit comprises an enabling signal generating circuit and a regulating circuit, wherein the enabling signal generating circuit is used for receiving a first voltage signal and comprises a pull-up point position, a pull-down point position and an output terminal, the pull-up point position is electrically connected with the regulating circuit, the pull-down point position is electrically connected with the regulating circuit, the regulating circuit is used for receiving a second voltage signal and inputting the second voltage signal to the enabling signal generating circuit, the enabling signal generating circuit generates a high-potential enabling signal according to the first voltage signal and the second voltage signal and outputs the high-potential enabling signal through the output terminal, and the voltage value of the second voltage signal is larger than that of the first voltage signal.
The adjusting circuit adjusts the leakage current of the enabling signal generating circuit according to the second voltage signal, so that the leakage current of the enabling signal generating circuit is reduced, and the enabling signal generated by the enabling signal generating circuit is kept stable.
In a second aspect, the present application also provides a display panel including the light-emitting scanning signal line driving circuit according to the first aspect.
In a third aspect, the present application further provides an electronic device, where the electronic device includes a body and the display panel of the second aspect, and the body is used for bearing the display panel.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for a person skilled in the art to obtain other drawings based on the drawings without any inventive exercise.
Fig. 1 is a schematic diagram of a light-emitting scanning signal line driving circuit framework according to a first embodiment of the present application.
Fig. 2 is a schematic diagram of a light-emitting scanning signal line driving circuit according to an embodiment of the present disclosure.
Fig. 3 is a schematic diagram of a light-emitting scanning signal line driving circuit according to an embodiment of the present disclosure.
Fig. 4 is a schematic diagram of a light-emitting scanning signal line driving circuit according to an embodiment of the present disclosure.
Fig. 5 is a schematic diagram of a light-emitting scanning signal line driving circuit according to an embodiment of the present application.
Fig. 6 is a schematic view of a display panel frame according to an embodiment of the present application.
Fig. 7 is a schematic top view of an electronic device according to an embodiment of the present disclosure.
Detailed Description
The technical solutions in the embodiments of the present application will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present application, and it is obvious that the described embodiments are only some embodiments of the present application, not all embodiments. All other embodiments obtained by a person of ordinary skill in the art without any inventive work based on the embodiments in the present application are within the scope of protection of the present application.
Referring to fig. 1, fig. 1 is a schematic diagram of a frame of a light-emitting scanning signal line driving circuit according to a first embodiment of the present disclosure. The light emission scanning signal line drive circuit 1 includes: an enable signal generating circuit 11 and an adjusting circuit 12. The enable signal generating circuit 11 receives a first voltage signal EVGL, and the enable signal generating circuit 11 includes a pull-up point PU, a pull-down point PD, and an output terminal EN. The pull-up point position PU is electrically connected with the adjusting circuit 12, and the pull-down point position PD is electrically connected with the adjusting circuit 12. The adjusting circuit 12 is configured to receive a second voltage signal HVGL and input the second voltage signal HVGL to the enable signal generating circuit 11, and the enable signal generating circuit 11 generates an enable signal with a high potential according to the first voltage signal EVGL and the second voltage signal HVGL and outputs the enable signal via the output terminal EN. Wherein a voltage value of the second voltage signal HVGL is greater than a voltage value of the first voltage signal EVGL.
Specifically, the light-emission scanning signal line driving circuit 1 is generally applied to the display panel 2. The enable signal generated by the enable signal generating circuit 11 can drive the light emitting units in the display panel 2 to emit light to display a picture.
Specifically, the enable signal generating circuit 11 further includes a plurality of thin film transistors, the adjusting circuit 12 inputs the second voltage signal HVGL to the thin film transistors in the enable signal generating circuit 11, and controls the thin film transistors through the pull-up point PU and the pull-down point PD, and since the voltage value of the second voltage signal HVGL is greater than the voltage value of the first voltage signal EVGL, the source-gate voltage value of the thin film transistors is less than zero. According to the current-voltage characteristic curve of the thin film transistor, when the source-gate voltage value of the thin film transistor is smaller than zero, the leakage current of the thin film transistor is greatly reduced, that is, the leakage current of the pull-up point position PU is greatly reduced.
It is understood that, in the present embodiment, the adjusting circuit 12 adjusts the leakage current of the enable signal generating circuit 11 according to the second voltage signal HVGL, so that the leakage current of the enable signal generating circuit 11 is reduced, thereby stabilizing the enable signal generated by the enable signal generating circuit 11.
In this embodiment, the second voltage signal HVGL is generated by a device other than the light-emitting scanning signal line driving circuit 1, for example, a driving chip, and the voltage signal may be generated as required. It is understood that since the second voltage signal HVGL is generated by a device other than the light-emission scanning signal line driving circuit 1 and the first voltage signal EVGL is generated by a device inside the light-emission scanning signal line driving circuit 1, the risk of short circuit inside the light-emission scanning signal line driving circuit 1 is reduced and the operation stability of the light-emission scanning signal line driving circuit 1 is improved.
In one possible embodiment, referring to fig. 2, fig. 2 is a schematic diagram of a light-emitting scanning signal line driving circuit according to an embodiment of the present disclosure. The enable signal generating circuit 11 includes a first transistor M1, the first transistor M1 including a first gate g1, a second gate g2, a first electrode s, and a second electrode d. The first gate g1 of the first transistor M1 is electrically connected to the second gate g2 and is configured to receive a first timing signal ECLKn, and the first timing signal ECLKn is configured to control on/off of the first transistor M1. The first electrode s of the first transistor M1 is electrically connected to the pull-up point PU, the second electrode d of the first transistor M1 is configured to receive a third voltage signal EVGH, and the first transistor M1 charges the pull-up point PU by the third voltage signal EVGH.
Specifically, when the first timing signal ECLKn is at a high level, the first transistor M1 is turned on, and the third voltage signal EVGH charges the pull-up point PU. In this embodiment, the third voltage signal EVGH is a dc voltage signal, and compared with a conventional ac voltage signal, the process of charging the pull-up point PU by the third voltage signal EVGH is faster, which is beneficial to maintaining the voltage value of the pull-up point PU.
In one possible embodiment, please refer to fig. 3, in which fig. 3 is a schematic diagram of a light-emitting scanning signal line driving circuit according to an embodiment of the present disclosure. The adjusting circuit 12 includes: a second transistor M2 and a third transistor M3, and the enable signal generating circuit 11 includes a fourth transistor M4. The second transistor M2, the third transistor M3, and the fourth transistor M4 each include a first gate g1, a second gate g2, a first electrode s, and a second electrode d. The first gate g1 of the second transistor M2 is electrically connected to the pull-up point PU, the second gate g2 of the second transistor M2 is electrically connected to the second gate g2 of the third transistor M3, the first electrode s of the second transistor M2 is configured to receive the second voltage signal HVGL, and the second electrode d of the second transistor M2 is electrically connected to the second electrode d of the third transistor M3. The first gate g1 of the third transistor M3 is electrically connected to the pull-down point PD, and the first electrode s of the third transistor M3 is electrically connected to the second gate g2 of the fourth transistor M4 and is configured to receive the first voltage signal EVGL. The first gate g1 of the fourth transistor M4 is electrically connected to the pull-down point PD, the first electrode s of the fourth transistor M4 is electrically connected to the second electrode d of the second transistor M2, and the second electrode d of the fourth transistor M4 is electrically connected to the pull-up point PU.
Specifically, when the third voltage signal EVGH finishes charging the pull-up point PU, the pull-up point PU maintains a high voltage. The first voltage signal EVGL is input to the pull-down point PD, and since the pull-up point PU maintains a high potential, the second transistor M2 is turned on, so that the second voltage signal HVGL is transmitted to the first electrode s of the fourth transistor M4 through the second transistor M2. In the present embodiment, since the voltage value of the second voltage signal HVGL is greater than the voltage value of the first voltage signal EVGL, the voltage value between the first gate g1 of the fourth transistor M4 and the first electrode s of the fourth transistor M4 is less than 0V. According to the current-voltage characteristic curve of the thin film transistor, it can be found that the leakage current of the fourth transistor M4 is greatly reduced, so that the leakage current of the pull-up point PU is greatly reduced.
In one possible embodiment, please refer to fig. 4, in which fig. 4 is a schematic diagram of a light emitting scanning signal line driving circuit according to an embodiment of the present disclosure. The adjusting circuit 12 includes: a second transistor M2 and a third transistor M3, and the enable signal generating circuit 11 includes a fifth transistor M5. The second transistor M2, the third transistor M3, and the fifth transistor M5 each include a first gate g1, a second gate g2, a first electrode s, and a second electrode d. The first gate g1 of the second transistor M2 is electrically connected to the pull-up point PU, the second gate g2 of the second transistor M2 is electrically connected to the first electrode s of the second transistor M2 and is configured to receive the second voltage signal HVGL, and the second electrode d of the second transistor M2 is electrically connected to the second electrode d of the third transistor M3. The first gate g1 of the third transistor M3 is electrically connected to a pull-down point PD, the second gate g2 of the third transistor M3 is electrically connected to the first gate g1 of the fifth transistor M5 and is configured to receive the first voltage signal EVGL, and the second electrode d of the third transistor M3 is electrically connected to the first electrode s of the fifth transistor M5. The second gate g2 of the fifth transistor M5 is electrically connected to the pull-down point PD, and the second electrode d of the fifth transistor M5 is electrically connected to the output terminal EN.
Specifically, when the third voltage signal EVGH finishes charging the pull-up point PU, the pull-up point PU maintains a high voltage. The first voltage signal EVGL is input to the pull-down point PD, and since the pull-up point PU maintains a high potential, the second transistor M2 is turned on, so that the second voltage signal HVGL is transmitted to the first electrode s of the fifth transistor M5 through the second transistor M2. In the present embodiment, since the voltage value of the second voltage signal HVGL is greater than the voltage value of the first voltage signal EVGL, the voltage value between the first gate g1 of the fifth transistor M5 and the first electrode s of the fifth transistor M5 is less than 0V. According to the current-voltage characteristic curve of the thin film transistor, it can be found that the leakage current of the fifth transistor M5 is greatly reduced, so that the leakage current of the pull-up point PU is greatly reduced.
In other possible embodiments, the regulating circuit 12 may also transmit the second voltage signal HVGL to the first electrode s of the fourth transistor M4 and the first electrode s of the fifth transistor M5 simultaneously, so that the leakage current of the fourth transistor M4 and the fifth transistor M5 is reduced. It is to be understood that the electrical connection manner of the regulating circuit 12 is not limited in the present application as long as the regulating circuit 12 is not affected to transmit the second voltage signal HVGL to the enable signal generating circuit 11.
In a possible embodiment, please refer to fig. 5, in which fig. 5 is a schematic diagram of a light emitting scanning signal line driving circuit according to an embodiment of the present disclosure. The enable signal generating circuit 11 further includes: a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, and a storage capacitor C1. The sixth transistor M6, the seventh transistor M7, the eighth transistor M8 and the ninth transistor M9 each include a first gate g1, a second gate g2, a first electrode s and a second electrode d. The first gate G1 of the sixth transistor M6 is configured to receive a second timing signal ECLKBn, the first electrode s of the sixth transistor M6 is electrically connected to the second gate G2 of the sixth transistor M6 and the pull-down point PD, the second electrode d of the sixth transistor M6 is electrically connected to a first scan signal GN, the first gate G1 of the seventh transistor M7 is electrically connected to a second scan signal G (N +1), the first electrode s of the seventh transistor M7 is electrically connected to the second gate G2 of the seventh transistor M7 and receives the first voltage signal EVGL, the second electrode d of the seventh transistor M7 is electrically connected to the pull-down point PD, the first gate G1 of the eighth transistor M8 is electrically connected to one end of the storage capacitor C1, the output terminal, and the second gate G2 of the eighth transistor M8, and the first electrode s of the eighth transistor M8 is electrically connected to the third voltage signal EVGL, the second electrode d of the eighth transistor M8 is electrically connected to the pull-up point PU and the other end of the storage capacitor C1, the first gate g1 of the ninth transistor M9 is electrically connected to the pull-up point PU, the first electrode s of the ninth transistor M9 is electrically connected to the output terminal EN and the second gate g2 of the ninth transistor M9, and the second electrode d of the ninth transistor M9 is configured to receive the third voltage signal EVGH.
Specifically, the second timing signal ECLKBn is used to control on/off of the sixth transistor M6, and the first scan signal GN is transmitted to the pull-down point PD through the sixth transistor M6. The second scan signal G (N +1) is used to control the on/off of the seventh transistor M7. When the pull-up point PU maintains the high level, the second scan signal G (N +1) outputs the high level, and the seventh transistor M7 is turned on, so that the first voltage signal EVGL is input to the pull-down point PD through the seventh transistor M7. The third transistor M3 forms a feedback circuit when the third transistor M3 is turned on, so that the third voltage signal EVGH charges the pull-up point PU through the third transistor M3. The storage capacitor C1 is used for storing the voltage between the pull-up point PU and the output terminal EN. The ninth transistor M9 is configured to transmit the third voltage signal EVGH to the output terminal EN when the pull-up point PU is at a high level.
Fig. 6 is a schematic view of a display panel 2 according to an embodiment of the present disclosure, and fig. 6 is a schematic view of a display panel frame according to an embodiment of the present disclosure. The display panel 2 includes the light-emission scanning signal line drive circuit 1 as described above. The light-emitting scanning signal line driving circuit 1 refers to the above description, and is not described herein again.
Further, referring to fig. 6 again, the display panel 2 further includes a pixel circuit 21, the pixel circuit 21 includes a light emitting unit 211 and a driving unit 212, the pixel circuit 21 receives the enable signal output by the enable signal generating circuit 11 of the light emitting scanning signal line driving circuit 1, and the driving unit 212 drives the light emitting unit 211 to emit light according to the enable signal.
It can be understood that, in this embodiment, the voltage value of the enable signal generated by the light-emitting scanning signal line driving circuit 1 is stable, so that when the driving unit 212 drives the light-emitting unit 211 to emit light, the luminance of the light-emitting unit 211 is not easy to change, and the display screen is good.
Fig. 7 is a schematic top view of an electronic device 3 according to an embodiment of the present application, and fig. 7 is a schematic top view of the electronic device. The electronic device 3 includes a body 31 and the display panel 2, where the body 31 is used for carrying the display panel 2.
The principle and the implementation of the present application are explained herein by applying specific examples, and the above description of the embodiments is only used to help understand the core idea of the present application; meanwhile, for a person skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.
Claims (10)
1. A light-emitting scanning signal line driving circuit applied to a display panel, comprising: the circuit comprises an enabling signal generating circuit and an adjusting circuit, wherein the enabling signal generating circuit receives a first voltage signal, the enabling signal generating circuit comprises a pull-up point position, a pull-down point position and an output terminal, the pull-up point position is electrically connected with the adjusting circuit, the pull-down point position is electrically connected with the adjusting circuit, the adjusting circuit is used for receiving a second voltage signal and inputting the second voltage signal to the enabling signal generating circuit, the enabling signal generating circuit generates a high-potential enabling signal according to the first voltage signal and the second voltage signal and outputs the high-potential enabling signal through the output terminal, and the voltage value of the second voltage signal is larger than that of the first voltage signal.
2. The light-emitting scanning signal line driving circuit according to claim 1, wherein the enable signal generating circuit includes a first transistor, the first transistor includes a first gate, a second gate, a first electrode and a second electrode, the first gate of the first transistor is electrically connected to the second gate and is configured to receive a first timing signal, the first timing signal is configured to control on/off of the first transistor, the first electrode of the first transistor is electrically connected to the pull-up point, the second electrode of the first transistor is configured to receive a third voltage signal, and the first transistor charges the pull-up point through the third voltage signal.
3. The light-emitting scanning signal line drive circuit according to claim 1, wherein the adjustment circuit includes: the enable signal generating circuit comprises a second transistor and a third transistor, the second transistor, the third transistor and the fourth transistor each comprise a first gate, a second gate, a first electrode and a second electrode, the first gate of the second transistor is electrically connected to the pull-up point, the second gate of the second transistor is electrically connected to the second gate of the third transistor, the first electrode of the second transistor is used for receiving the second voltage signal, the second electrode of the second transistor is electrically connected to the second electrode of the third transistor, the first gate of the third transistor is electrically connected to the pull-down point, the first electrode of the third transistor is electrically connected to the second gate of the fourth transistor and is used for receiving the first voltage signal, and the first gate of the fourth transistor is electrically connected to the pull-down point, and a first electrode of the fourth transistor is electrically connected with a second electrode of the second transistor, and a second electrode of the fourth transistor is electrically connected with the pull-up point.
4. The light-emitting scanning signal line driver circuit according to claim 3, wherein a voltage between the first gate and the first electrode of the fourth transistor is less than 0V.
5. The light-emitting scanning signal line drive circuit according to claim 2, wherein the adjustment circuit includes: the enable signal generation circuit comprises a fifth transistor, and the second transistor, the third transistor and the fifth transistor respectively comprise a first grid electrode, a second grid electrode, a first electrode and a second electrode; a first gate of the second transistor is electrically connected to the pull-up point, a second gate of the second transistor is electrically connected to the first electrode of the second transistor and is configured to receive the second voltage signal, a second electrode of the second transistor is electrically connected to the second electrode of the third transistor, a first gate of the third transistor is electrically connected to the pull-down point, a second gate of the third transistor is electrically connected to the first gate of the fifth transistor and is configured to receive the first voltage signal, and a second electrode of the third transistor is electrically connected to the first electrode of the fifth transistor; and a second gate of the fifth transistor is electrically connected with the pull-down point, and a second electrode of the fifth transistor is electrically connected with the output terminal.
6. The light-emitting scanning signal line driver circuit according to claim 5, wherein a voltage between the first gate and the first electrode of the fifth transistor is less than 0V.
7. The light-emitting scanning signal line drive circuit according to any one of claims 1 to 6, wherein the enable signal generation circuit further includes: the storage capacitor comprises a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor and a storage capacitor, wherein the sixth transistor, the seventh transistor, the eighth transistor and the ninth transistor respectively comprise a first grid electrode, a second grid electrode, a first electrode and a second electrode; a first gate of the sixth transistor is configured to receive a second timing signal, a first electrode of the sixth transistor is electrically connected to a second gate of the sixth transistor and the pull-down point, a second electrode of the sixth transistor is electrically connected to a first scan signal, and a first gate of the seventh transistor is electrically connected to a second scan signal; a first electrode of the seventh transistor is electrically connected with a second gate of the seventh transistor and receives the first voltage signal, and a second electrode of the seventh transistor is electrically connected with the pull-down point; a first gate of the eighth transistor is electrically connected to one end of the storage capacitor, the output terminal and a second gate of the eighth transistor, a first electrode of the eighth transistor is electrically connected to a third voltage signal, and a second electrode of the eighth transistor is electrically connected to the pull-up point and the other end of the storage capacitor; a first gate of the ninth transistor is electrically connected to the pull-up point, a first electrode of the ninth transistor is electrically connected to the output terminal and a second gate of the ninth transistor, and a second electrode of the ninth transistor is configured to receive the third voltage signal.
8. A display panel comprising the light-emitting scanning signal line driver circuit according to any one of claims 1 to 7.
9. The display panel according to claim 8, wherein the display panel further comprises a pixel circuit including a light emitting unit and a driving unit, the pixel circuit receiving the enable signal output from the enable signal generation circuit of the light emission scanning signal line driving circuit, the driving unit driving the light emitting unit to emit light in accordance with the enable signal.
10. An electronic device, comprising a body and a display panel according to any one of claims 8 to 9, wherein the body is used for carrying the display panel.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202021248238.3U CN213123730U (en) | 2020-06-30 | 2020-06-30 | Light-emitting scanning signal line drive circuit, display panel and electronic device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202021248238.3U CN213123730U (en) | 2020-06-30 | 2020-06-30 | Light-emitting scanning signal line drive circuit, display panel and electronic device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN213123730U true CN213123730U (en) | 2021-05-04 |
Family
ID=75674514
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202021248238.3U Active CN213123730U (en) | 2020-06-30 | 2020-06-30 | Light-emitting scanning signal line drive circuit, display panel and electronic device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN213123730U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113870765A (en) * | 2020-06-30 | 2021-12-31 | 深圳市柔宇科技有限公司 | Light-emitting scanning signal line drive circuit, display panel and electronic device |
| CN116504184A (en) * | 2023-06-30 | 2023-07-28 | 惠科股份有限公司 | Light-emitting driving circuit, time sequence control method and display panel |
-
2020
- 2020-06-30 CN CN202021248238.3U patent/CN213123730U/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113870765A (en) * | 2020-06-30 | 2021-12-31 | 深圳市柔宇科技有限公司 | Light-emitting scanning signal line drive circuit, display panel and electronic device |
| CN116504184A (en) * | 2023-06-30 | 2023-07-28 | 惠科股份有限公司 | Light-emitting driving circuit, time sequence control method and display panel |
| CN116504184B (en) * | 2023-06-30 | 2023-09-15 | 惠科股份有限公司 | Light-emitting driving circuit, time sequence control method and display panel |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN109272940B (en) | Pixel driving circuit, driving method thereof and display substrate | |
| CN109545145B (en) | Pixel circuit, driving method thereof and display device | |
| US11875717B2 (en) | Display panel, integrated chip, and display apparatus with different brightness modes | |
| CN109801592B (en) | Pixel circuit, driving method thereof and display substrate | |
| US11551606B2 (en) | LED driving circuit, display panel, and pixel driving device | |
| CN108597444B (en) | Silicon-based OLED pixel circuit and method for compensating OLED electrical characteristic change thereof | |
| CN213123730U (en) | Light-emitting scanning signal line drive circuit, display panel and electronic device | |
| TW201413681A (en) | Organic light emitting diode display apparatus | |
| WO2020107830A1 (en) | Pixel circuit and display device | |
| US10971063B2 (en) | Pixel circuit and display device | |
| WO2023011333A1 (en) | Pixel driving circuit and driving method therefor, and display panel | |
| CN110021262B (en) | Pixel circuit, driving method thereof, pixel unit and display panel | |
| CN111243515A (en) | Pixel circuit, display panel and driving method of pixel circuit | |
| CN111696485A (en) | Pixel circuit, display module, dimming method and display device | |
| CN110675815A (en) | Pixel driving circuit, driving method thereof and display device | |
| CN113593475A (en) | Pixel circuit, driving method and display device | |
| CN108877679A (en) | Pixel circuit, display device and image element driving method | |
| US11238792B2 (en) | Pixel circuit and display device | |
| CN110706657B (en) | Pixel circuit and display device | |
| CN115588402B (en) | Driving circuit and display panel | |
| CN106782339A (en) | A kind of pixel-driving circuit and its driving method, display device | |
| CN115064126A (en) | Pixel circuit, display panel and display device | |
| CN113870765A (en) | Light-emitting scanning signal line drive circuit, display panel and electronic device | |
| WO2023092517A1 (en) | Driving apparatus and driving method for led display screen, and led display screen | |
| CN114783374B (en) | Pixel driving circuit, display panel and display device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| PP01 | Preservation of patent right |
Effective date of registration: 20220511 Granted publication date: 20210504 |
|
| PP01 | Preservation of patent right |