CN115064126A

CN115064126A - Pixel circuit, display panel and display device

Info

Publication number: CN115064126A
Application number: CN202210753818.5A
Authority: CN
Inventors: 王尚龙
Original assignee: Wuhan Tianma Microelectronics Co Ltd
Current assignee: Wuhan Tianma Microelectronics Co Ltd
Priority date: 2022-06-28
Filing date: 2022-06-28
Publication date: 2022-09-16

Abstract

The embodiment of the application provides a pixel circuit, a display panel and a display device, wherein in the pixel circuit, a driving transistor is used for providing light-emitting driving current for a light-emitting module; the first pole of the first transistor is electrically connected with the first reset signal line, the first pole of the second transistor is electrically connected with the grid electrode of the driving transistor, and a first node is arranged between the second pole of the first transistor and the second pole of the second transistor; the first pole of the third transistor is electrically connected with the second pole of the driving transistor, the first pole of the fourth transistor is electrically connected with the grid electrode of the driving transistor, and a second node is arranged between the second pole of the third transistor and the second pole of the fourth transistor; the input end of the adjusting module is electrically connected with the first node, the output end of the adjusting module is electrically connected with the second node, and the adjusting module is used for adjusting the electric potentials of the first node and the second node. The method and the device can reduce the potential difference between the first node and the second node and the grid electrode of the driving transistor, and are favorable for improving the grid electrode leakage problem of the driving transistor.

Description

Pixel circuit, display panel and display device

[ technical field ] A method for producing a semiconductor device

The present disclosure relates to display technologies, and particularly to a pixel circuit, a display panel, and a display device.

[ background of the invention ]

An organic light-emitting diode (OLED) display panel has the advantages of low power consumption, self-luminescence, wide viewing angle, wide temperature characteristic, fast response speed and the like, and is widely applied in the market. The pixel circuit for controlling the light emitting device to emit light is the core technical content of the OLED display panel, and has important research significance.

A driving transistor is generally included in the pixel circuit, and the driving transistor is capable of generating a driving current for driving the light emitting device according to a voltage of a gate thereof. However, in the prior art, the gate voltage of the driving transistor has a leakage problem, which causes the gate voltage of the driving transistor to be unstable, and affects the luminance of the light emitting device, and further affects the display effect.

[ application contents ]

In view of the above, embodiments of the present disclosure provide a pixel circuit, a display panel and a display device to solve the above problems.

In a first aspect, an embodiment of the present application provides a pixel circuit, which includes a light emitting module, a driving transistor, a first transistor, a second transistor, a third transistor, a fourth transistor, and a regulating module; the driving transistor is used for providing light-emitting driving current for the light-emitting module; the first pole of the first transistor is electrically connected with the first reset signal line, the first pole of the second transistor is electrically connected with the grid electrode of the driving transistor, and a first node is arranged between the second pole of the first transistor and the second pole of the second transistor; the first pole of the third transistor is electrically connected with the second pole of the driving transistor, the first pole of the fourth transistor is electrically connected with the grid electrode of the driving transistor, and a second node is arranged between the second pole of the third transistor and the second pole of the fourth transistor; the input end of the adjusting module is electrically connected with the first node, the output end of the adjusting module is electrically connected with the second node, and the adjusting module is used for adjusting the electric potentials of the first node and the second node.

In one implementation manner of the first aspect, the adjusting module includes a fifth transistor, a first pole of the fifth transistor is electrically connected to the first node, a second pole of the fifth transistor is electrically connected to the second node, and a gate of the fifth transistor is electrically connected to the first signal line.

In one implementation form of the first aspect, the signal transmitted by the first signal line controls the fifth transistor to be turned off.

In one implementation form of the first aspect, the first signal line is electrically connected to a fixed-potential signal line.

In one implementation manner of the first aspect, the fifth transistor is a P-type transistor, and the first signal line is electrically connected to the direct-current high-potential signal line.

In one implementation manner of the first aspect, the pixel circuit further includes a data voltage writing module, an input end of the data voltage writing module is electrically connected to the data signal line, and an output end of the data voltage writing module is electrically connected to the first pole of the driving transistor; the working process of the pixel circuit comprises a data writing stage, wherein in the data writing stage, the data voltage writing module, the third transistor and the fourth transistor are started; the signal transmitted by the first signal line controls the fifth transistor to be started after the data writing phase.

In one implementation form of the first aspect, the operation process of the pixel circuit further includes a light emission phase performed after the data writing phase; the fifth transistor is turned on in the light emitting period.

In one implementation manner of the first aspect, the pixel circuit further includes a power supply voltage writing module and a light emission control module; the input end of the power supply voltage writing module is electrically connected with the power supply voltage signal wire, the output end of the power supply voltage writing module is electrically connected with the first pole of the driving transistor, and the control end of the power supply voltage writing module is electrically connected with the light-emitting control signal wire; the input end of the light-emitting control module is electrically connected with the second pole of the driving transistor, the output end of the light-emitting control module is electrically connected with the first pole of the light-emitting module, and the control end of the light-emitting control module is electrically connected with the light-emitting control signal line; the first signal line is electrically connected with the light-emitting control signal line, and the signal transmitted by the light-emitting control signal line controls the power voltage writing module, the light-emitting control module and the fifth transistor to be in the same on-off state.

In one implementation manner of the first aspect, the operation process of the pixel circuit further includes a regulation phase and a light-emitting phase which are sequentially performed after the data writing phase; the fifth transistor is turned on during the regulation phase.

In one implementation of the first aspect, the second pole of the first transistor is electrically connected to the second pole of the second transistor at a first node; a second pole of the third transistor is electrically coupled to a second pole of the fourth transistor at a second node.

In one implementation manner of the first aspect, the gate of the first transistor and the gate of the second transistor are both electrically connected to a first scan line, and a signal transmitted by the first scan line controls the switching states of the first transistor and the second transistor to be the same; the grid electrode of the third transistor and the grid electrode of the fourth transistor are electrically connected with the second scanning line, and the signals transmitted by the second scanning line control the on-off states of the third transistor and the fourth transistor to be the same.

In a second aspect, an embodiment of the present application provides a display panel including the pixel circuit provided in the first aspect.

In a third aspect, embodiments of the present application provide a display device, including the display panel as provided in the second aspect.

In the application, the adjusting module is arranged between the first node and the second node and used for neutralizing the potentials of the first node and the second node, so that the potential difference between the first node and the grid electrode of the second node and the potential difference between the second node and the grid electrode of the driving transistor can be reduced, the grid electrode potential of the driving transistor is favorably improved, the grid electrode potential of the driving transistor is stabilized, the phenomenon that the brightness of a display frame picture is greatly changed is favorably avoided, and the display effect of the display panel is improved.

[ description of the drawings ]

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

Fig. 1 is a schematic diagram of a pixel circuit according to an embodiment of the present disclosure;

FIG. 2 is a schematic diagram of the pixel circuit shown in FIG. 1;

FIG. 3 is a timing diagram of the pixel circuit shown in FIG. 2;

FIG. 4 is yet another schematic diagram of the pixel circuit of FIG. 1;

FIG. 5 is a timing diagram of the pixel circuit shown in FIG. 4;

FIG. 6 is a timing diagram of the pixel circuit of FIG. 2;

fig. 7 is a schematic diagram of another pixel circuit provided in the present application;

FIG. 8 is a timing diagram of the pixel circuit of FIG. 2;

FIG. 9 is yet another timing diagram for the pixel circuit of FIG. 2;

fig. 10 is a schematic view of a display panel according to an embodiment of the present disclosure;

fig. 11 is a schematic view of a display device according to an embodiment of the present disclosure.

[ detailed description ] A

For better understanding of the technical solutions of the present application, the following detailed descriptions of the embodiments of the present application are provided with reference to the accompanying drawings.

It should be understood that the embodiments described are only a few embodiments of the present application, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

The terminology used in the embodiments of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in the examples of this application and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

It should be understood that the term "and/or" as used herein is merely one type of association that describes an associated object, meaning that three relationships may exist, e.g., a and/or B may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" herein generally indicates that the former and latter related objects are in an "or" relationship.

In the description herein, it is to be understood that the terms "substantially", "approximately", "about", "substantially", and the like, as used in the claims and the examples herein, are intended to be generally accepted as not being precise, within the scope of reasonable process operation or tolerance.

It should be understood that although the terms first, second, etc. may be used to describe transistors, nodes, etc. in the embodiments of the present application, these transistors, nodes, etc. should not be limited by these terms. These terms are only used to distinguish one transistor, node, etc. from another. For example, a first node may also be referred to as a second node, and similarly, a second node may also be referred to as a first node without departing from the scope of embodiments herein.

The applicant provides a solution to the problems of the prior art through intensive research.

Fig. 1 is a schematic diagram of a pixel circuit according to an embodiment of the present disclosure, fig. 2 is a schematic diagram of the pixel circuit shown in fig. 1, and fig. 3 is a timing diagram of the pixel circuit shown in fig. 2.

The present embodiment provides a pixel circuit 100, and as shown in fig. 1 to fig. 3, the pixel circuit 100 includes a light emitting module 10, a driving transistor Td, a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, and a regulating module 20. The driving transistor Td is used for providing a light emitting driving current to the light emitting module 10, and driving the light emitting module 10 to emit light.

A first pole of the first transistor T1 is electrically connected to the first reset signal line SL1, a first pole of the second transistor T2 is electrically connected to the gate of the driving transistor Td, and a first node N1 is included between a second pole of the first transistor T1 and a second pole of the second transistor T2. The first transistor T1 and the second transistor T2 are used to transmit the first reset voltage Vref1 transmitted by the first reset signal line SL1 to the gate of the driving transistor Td.

A first pole of the third transistor T3 is electrically connected to a second pole of the driving transistor Td, a first pole of the fourth transistor T4 is electrically connected to a gate electrode of the driving transistor Td, and a second node N2 is included between the second pole of the third transistor T3 and the second pole of the fourth transistor T4. The third transistor T3 and the fourth transistor T4 are used to compensate the threshold voltage of the driving transistor Td to the gate of the driving transistor Td.

As shown in fig. 1 and 2, in particular, the second pole of the first transistor T1 is electrically connected with the second pole of the second transistor T2 at the first node N1. A second pole of the third transistor T3 is electrically connected to a second pole of the fourth transistor T4 at a second node N2. A first pole of the second transistor T2, a first pole of the fourth transistor T4, and a gate of the driving transistor Td are electrically connected at a third node N3.

Further, the gate of the first transistor T1 and the gate of the second transistor T2 are both electrically connected to the first scan line S1, and a signal transmitted by the first scan line S1 controls the switching states of the first transistor T1 and the second transistor T2 to be the same. The gate of the third transistor T3 and the gate of the fourth transistor T4 are both electrically connected to the second scan line S2, and the signal transmitted by the second scan line S2 controls the switching states of the third transistor T3 and the fourth transistor T4 to be the same.

When the first scan line S1 transmits an active signal to control the first and second transistors T1 and T2 to be turned on, the first reset voltage Vref1 transmitted by the first reset signal line SL1 may be transmitted to the gate of the driving transistor Td through the turned-on first and second transistors T1 and T2.

When the second scan line S2 transmits an active signal to control the third transistor T3 and the fourth transistor T4 to be turned on, the threshold voltage of the driving transistor Td may be compensated to the gate of the driving transistor Td by the turned-on third transistor T3 and fourth transistor T4.

The input terminal 201 of the regulating module 20 is electrically connected to the first node N1, the output terminal 202 is electrically connected to the second node N2, and the regulating module 20 is configured to regulate the potentials of the first node N1 and the second node N2.

In particular, the adjustment module 20 may be used to neutralize the potential of the first node N1 and the second node N2. To reduce the potential difference between the first node N1, the second node N2 and the gate of the driving transistor Td.

It is understood that, due to the operating characteristics of the transistor, a leakage phenomenon occurs when a potential difference occurs between the first and second electrodes of the transistor, although the transistor is in an off state. The first and second poles of the transistor may be a source and a drain of the transistor.

In the related art, since the first pole of the first transistor T1 receives the first reset voltage Vref1 having a lower potential, and the second pole of the first transistor T1 is electrically connected to the second pole of the second transistor T2 at the first node N1, the first pole of the second transistor T2 is electrically connected to the gate of the driving transistor Td at the third node N3. When the gate potential of the driving transistor Td increases, that is, the potential of the third node N3 increases, the third node N3 leaks electricity to the first node N1 although the first transistor T1 and the second transistor T2 are in an off state. Also, since the first pole of the third transistor T3 receives a voltage generally greater than the gate voltage of the driving transistor Td, and the second pole of the third transistor T3 is electrically connected to the second pole of the fourth transistor T4 at the second node N2, the first pole of the fourth transistor T4 is electrically connected to the gate of the driving transistor Td at the third node N3. When the potential of the first pole of the third transistor T3 is greater than the potential of the third node N3, the second node N2 leaks electricity to the third node N3 although the third transistor T3 and the fourth transistor T4 are in an off state. This causes the gate potential of the driving transistor Td when generating the light emitting driving current to be unstable, thereby causing the light emitting driving current generated according to the gate potential thereof to be unstable, which affects the luminance of the light emitting module 10.

Moreover, since the potential of the third node N3 is lower when the luminance of the light emitting module 10 is higher than that when the luminance of the light emitting module 10 is lower, the second node N2 leaks more electricity to the third node N3 when the luminance of the light emitting module 10 is higher, and the third node N3 leaks more electricity to the first node N1 when the luminance of the light emitting module 10 is lower, which results in a larger luminance change of the display frame and affects the display effect. Especially, when the display panel is in a low gray scale state, the influence is very obvious.

In the embodiment of the present application, by providing the adjusting module 20 between the first node N1 and the second node N2 for neutralizing the potentials of the first node N1 and the second node N2, the potential difference between the first node N1 and the third node N3 and the potential difference between the second node N2 and the third node N3 can be reduced. That is, the potential difference between the first node N1, the second node N2 and the gate of the driving transistor Td is reduced, so as to improve the problem of gate leakage of the driving transistor Td, stabilize the gate potential of the driving transistor Td, further avoid the occurrence of large variation in brightness of the displayed frame, and improve the display effect of the display panel.

In one embodiment of the present application, with continued reference to fig. 2, the regulating module 20 includes a fifth transistor T5, a first pole of the fifth transistor T5 is electrically connected to the first node N1, a second pole of the fifth transistor T5 is electrically connected to the second node N2, and a gate of the fifth transistor T5 is electrically connected to the first signal line SR 1. The first pole of the fifth transistor T5 may be a source of the fifth transistor T5, and the second pole of the fifth transistor T5 may be a drain of the fifth transistor T5.

In one solution of the embodiment of the present application, please refer to fig. 2 and fig. 3, a signal transmitted by the first signal line SR1 controls the fifth transistor T5 to turn off.

Alternatively, the first signal line SR1 is electrically connected to a fixed potential signal line, and the first signal line SR1 receives a fixed potential signal.

Further, the fifth transistor T5 may be a P-type transistor, the first signal line SR1 is electrically connected to the dc high voltage signal line, and the first signal line SR1 receives the dc high voltage VGH transmitted by the dc high voltage signal line.

In this embodiment, the fifth transistor T5 is set to be in an off state during the operation of the pixel circuit 100. As can be seen from the above analysis, when the potential difference between the first node N1 and the second node N2 is greater than the potential difference between the third node N3 and the second node N2, the second node N2 leaks electricity to the first node N1 through the fifth transistor T5. During the operation of the pixel circuit 100, the second node N2 continuously leaks current to the first node N1 through the fifth transistor T5, so that the potential of the first node N1 is increased, and the potential of the second node N2 is decreased, thereby decreasing the potential difference between the first node N1, the second node N2, and the third node N3, that is, decreasing the potential difference between the first node N1, the second node N2, and the gate of the driving transistor Td, so as to improve the gate leakage problem of the driving transistor Td, stabilize the gate potential of the driving transistor Td, and improve the display effect of the display panel.

Fig. 4 is another schematic diagram of the pixel circuit shown in fig. 1, and fig. 5 is a timing diagram of the pixel circuit shown in fig. 4.

The pixel circuit 100 shown in fig. 4 differs from the pixel circuit 100 shown in fig. 2 in that: the fifth transistor T5 is an N-type transistor, and the first signal line SR1 is electrically connected to the dc low-level signal line. The timing sequence shown in fig. 5 differs from the timing sequence shown in fig. 3 only in that: the first signal line SR1 receives the low-level signal VGL transmitted by the low-dc low-level signal line and controls the fifth transistor T5 to turn off.

Fig. 6 is another timing diagram of the pixel circuit shown in fig. 2.

In another technical solution of the embodiment of the present application, as shown in fig. 1, fig. 2, and fig. 4 in combination with fig. 6, the pixel circuit 100 further includes a data voltage writing module 30, an input end 301 of the data voltage writing module 30 is electrically connected to the data signal line DL1, an output end 302 of the data voltage writing module 30 is electrically connected to a first pole of the driving transistor Td, and the data voltage writing module 30 is configured to transmit the data voltage Vdata transmitted by the data signal line DL1 to the first pole of the driving transistor Td.

The operation of the pixel circuit 100 includes a data writing phase E1, in which the data writing phase E1, the data voltage writing module 30, the third transistor T3 and the fourth transistor T4 are turned on.

Specifically, the control terminal 303 of the data voltage writing module 30 is electrically connected to the second scan line S2, and the signal transmitted by the second scan line S2 controls the data voltage writing module 30 and the switching states of the third and fourth transistors to be the same.

Further, the data voltage writing module 30 includes a sixth transistor T6, a first pole of the sixth transistor T6 is electrically connected to the data signal line DL1, a second pole of the sixth transistor T6 is electrically connected to the first pole of the driving transistor Td, and a gate of the sixth transistor T6 is electrically connected to the second scan line S2.

In the data writing phase E1, the sixth transistor T6, the third transistor T3 and the fourth transistor T4 are turned on, the data voltage Vdata is transmitted to the gate of the driving transistor Td, and the threshold voltage of the driving transistor Td is compensated to the gate of the driving transistor Td.

The fifth transistor T5 is controlled to be turned on after the data writing phase E1 by a signal transmitted through the first signal line SR 1.

It will be appreciated that the operation of the pixel circuit 100 also includes a reset phase E0 which precedes the data write phase E1. In the reset phase E0, the first scan line S1 transmits an active signal to control the first transistor T1 and the second transistor T2 to be turned on, and at this time, the first reset voltage Vref1 transmitted by the first reset signal line SL1 is transmitted to the gate of the driving transistor Td through the turned-on first transistor T1 and the turned-on second transistor T2, so as to reset the gate of the driving transistor Td.

The signal transmitted by the first signal line SR1 controls the fifth transistor T5 to be turned off in the reset phase E0 and the data write phase E1.

In the present disclosure, the fifth transistor T5 is turned on, so that the first node N1 and the second node N2 can be turned on by the fifth transistor T5. The potentials of the first node N1 and the second node N2 can be neutralized quickly, so that the potential of the first node N1 is increased, and the potential of the second node N2 is decreased, thereby decreasing the potential difference between the first node N1, the second node N2 and the gate of the driving transistor Td, and further facilitating to improve the problem of gate leakage of the driving transistor Td, stabilize the gate potential of the driving transistor Td, and improve the display effect of the display panel. In addition, in the present embodiment, the fifth transistor T5 is turned on after the data writing phase E1, so that the fifth transistor T5 can be prevented from affecting the reset phase E0 and the data writing phase E1 of the pixel circuit 100.

Fig. 7 is a schematic diagram of another pixel circuit according to an embodiment of the present disclosure.

In one embodiment of the present application, with continued reference to fig. 6, the operation of the pixel circuit 100 further includes a light-emitting phase E2 performed after the data writing phase E1.

The fifth transistor T5 is turned on during the lighting period E2.

It is understood that, during the light emitting period E2, the first transistor T1, the second transistor T2, the third transistor T3 and the fourth transistor T4 are all turned off. At this time, the driving transistor Td generates a light emission driving current for driving the light emitting module 10 according to the gate potential thereof.

As can be seen from the above analysis, a potential difference exists between the gate of the driving transistor Td and the first node N1 and the second node N2, which causes the gate of the driving transistor Td to leak current, and thus causes the luminance of the display frame to change. The fifth transistor T5 is set to be turned on in the lighting phase E2, and the potentials of the first node N1 and the second node N2 in the lighting phase E2 can be neutralized quickly, so that the potential difference between the first node N1, the second node N2 and the gate of the driving transistor Td is reduced, the leakage problem of the gate of the driving transistor Td in the lighting phase E2 is improved, and the display effect of the display panel is improved.

Specifically, as shown in fig. 1, 2, 4 and 7, the pixel circuit 100 further includes a power voltage writing module 40 and a light emitting control module 50. The input terminal 401 of the power voltage writing module 40 is electrically connected to the power voltage signal line DL2, the output terminal 402 is electrically connected to the first pole of the driving transistor Td, and the control terminal 403 is electrically connected to the emission control signal line EM. The light emission control module 50 has an input terminal 501 electrically connected to the second electrode of the driving transistor Td, an output terminal 502 electrically connected to the first electrode 101 of the light emission module 10, and a control terminal 503 electrically connected to the light emission control signal line EM.

Further, the power voltage writing module 40 includes a seventh transistor T7, and the light emitting control module 50 includes an eighth transistor T8. A first pole of the seventh transistor T7 is electrically connected to the power supply voltage signal line DL2, a second pole thereof is electrically connected to the first pole of the driving transistor Td, and a gate thereof is electrically connected to the emission control signal line EM; a first pole of the eighth transistor T8 is electrically connected to the second pole of the driving transistor Td, the second pole is electrically connected to the first pole 101 of the light emitting module 10, and the gate is electrically connected to the light emission control signal line EM.

In the light emitting period E2, the light emitting control signal line EM transmits an active signal to control the seventh transistor T7 and the eighth transistor T8 to be turned on, and the driving transistor Td generates a light emitting driving current according to the gate potential thereof and transmits the light emitting driving current to the first electrode 101 of the light emitting module 10, so as to drive the light emitting module 10 to emit light. The light emitting module 10 may include an organic light emitting diode, and the first pole 101 of the light emitting module 10 may be an anode of the organic light emitting diode.

As shown in fig. 7, the first signal line SR1 is electrically connected to the emission control signal line EM, and the signal transmitted by the emission control signal line EM controls the power supply voltage writing module 40, the emission control module 50, and the fifth transistor T5 to have the same switching state. That is, the channel types of the seventh transistor T7, the eighth transistor T8, and the fifth transistor T5 are the same.

In the implementation of the present application, the first signal line SR1 is electrically connected to the emission control signal line EM, that is, the signal transmitted by the emission control signal line EM is multiplexed to control the on-off state of the fifth transistor T5, so that it is not necessary to additionally set the control signal of the fifth transistor T5, which is beneficial to simplifying the design of the peripheral driving circuit in the display panel and reducing the difficulty in manufacturing the display panel.

In an embodiment of the present application, please refer to fig. 1, the pixel circuit 100 further includes a reset module 60, an input terminal 601 of the reset module 60 is electrically connected to the first reset signal line SL1, an output terminal 602 is electrically connected to the first pole 101 of the light emitting module 10, and the reset module 60 is configured to transmit the first reset voltage Vref1 transmitted by the first reset signal line SL1 to the first pole 101 of the light emitting module 10.

Specifically, as shown in fig. 2, 4 and 7, the reset module 60 includes a ninth transistor T9, a first electrode of the ninth transistor T9 is electrically connected to the first reset signal line SL1, a second electrode thereof is electrically connected to the first electrode 101 of the light emitting module 10, and a gate thereof is electrically connected to the first scan line S1. The channel type of the ninth transistor T9 is the same as the channel type of the first and second transistors T1 and T2.

In the reset phase E0, the ninth transistor T9 is turned on, and the first reset voltage Vref1 transmitted by the first reset signal line SL1 is transmitted to the first electrode 101 of the light emitting module 10 through the turned-on ninth transistor T9, thereby completing the reset of the light emitting module 10.

The operation of the pixel circuit shown in fig. 2 is described below with reference to fig. 2 and 6:

note that, in the following description, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 are P-type transistors, for example.

The operation of the pixel circuit 100 includes a reset phase E0, a data writing phase E1 and a light emitting phase E2, which are sequentially performed.

In the reset phase E0, the first scan line S1 transmits a turn-on signal, i.e., a low level signal, and the first transistor T1, the second transistor T2, and the ninth transistor T9 are turned on; the second scan line S2, the emission control signal line EM, and the first signal line SR1 transmit off signals, i.e., high level signals, and the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are turned off. Meanwhile, the first reset line SL1 transmits a first reset voltage Vref1, and the first reset voltage Vref1 is transmitted to the gate of the driving transistor Td through the turned-on first transistor T1 and second transistor T2, thereby completing the reset of the gate of the driving transistor Td. The first reset voltage Vref1 resets the first pole 101 of the light emitting module 10 through the turned-on ninth transistor T9. Alternatively, the light emitting module 10 includes an organic light emitting diode, and the first reset voltage Vref1 resets an anode of the organic light emitting diode through the turned-on ninth transistor T9.

In the data writing phase E1, the second scan line S2 transmits an on signal, i.e., a low level signal, and the third transistor T3, the fourth transistor T4 and the sixth transistor T6 are turned on; the first scan line S1, the light emission control signal line EM, and the first signal line SR1 transmit off signals, i.e., high level signals, and the first transistor T1, the second transistor T2, the fifth transistor T5, the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 are turned off. Meanwhile, the data signal line DL1 transmits the data voltage Vdata, at the start point of the data writing phase E1, the gate potential of the driving transistor Td is the first reset voltage Vref1, the source potential of the driving transistor Td is the data voltage signal Vdata, the potential difference between the source and the gate of the driving transistor Td is (Vdata-Vref1), and the potential difference between the two is greater than 0, so that the driving transistor Td is turned on, and the data voltage Vdata is transmitted to the gate of the driving transistor Td through the turned-on driving transistor Td and the turned-on third and fourth transistors T3 and T4, so that the gate potential of the driving transistor Td gradually increases. When the gate potential of the driving transistor Td is equal to (Vdata- | Vth |), the driving transistor Td turns off. Where Vth is the threshold voltage of the driving transistor Td.

In the light emitting period E2, the first and second scan lines S1 and S2 transmit off signals, i.e., high level signals, and the first, second, third, fourth, sixth, and ninth transistors T1, T2, T3, T4, T6, and T9 are turned off; the light emission control signal line EM and the first signal line SR1 transmit an on signal, i.e., a low level signal, and the seventh transistor T7, the eighth transistor T8, and the fifth transistor T5 are turned on. Meanwhile, the power supply voltage signal line DL2 transmits the power supply voltage VDD, i.e., the source potential of the driving transistor Td is the power supply voltage VDD. Since the power voltage VDD has a potential greater than the data voltage Vdata, the driving transistor Td generates a light emitting driving current and transmits the light emitting driving current to the light emitting module 10 through the eighth transistor T8, thereby controlling the light emitting module 10 to emit light.

Meanwhile, the fifth transistor T5 is turned on to turn on the second node N2 and the first node N1, quickly neutralize the potentials of the first node N1 and the second node N2, and reduce the potential difference between the first node N1, the second node N2 and the gate of the driving transistor Td, thereby improving the problem of gate leakage of the driving transistor Td, stabilizing the gate potential of the driving transistor Td, and enabling the driving transistor Td to generate a stable light emitting driving current.

Fig. 8 is another timing diagram of the pixel circuit shown in fig. 2, and fig. 9 is another timing diagram of the pixel circuit shown in fig. 2.

As shown in fig. 8 and 9, in one embodiment of the present application, the operation process of the pixel circuit 100 further includes a conditioning phase E3 and a light emitting phase E2, which are sequentially performed after the data writing phase E1.

The fifth transistor T5 is turned on during the regulation phase E3.

The timing shown in fig. 8 and 9 differs from the timing shown in fig. 6 mainly in that: an adjusting phase E3 is set between the data writing phase E1 and the lighting phase E2, and the first signal line SR1 transmits an active signal to control the fifth transistor T5 to turn on during the adjusting phase E3.

Alternatively, as shown in fig. 8, the fifth transistor T5 is turned on during the adjusting period E3 and turned off during the lighting period E2. In addition, as shown in fig. 9, the fifth transistor T5 can be turned on during both the adjusting phase E3 and the lighting phase E2.

The embodiment of the application can neutralize the potentials of the first node N1 and the second node N2 before the lighting phase E2, thereby being beneficial to keeping the gate potential of the driving transistor Td stable at the starting time of the lighting phase E2 and further ensuring the brightness stability of the display frame.

Fig. 10 is a schematic view of a display panel according to an embodiment of the present disclosure.

The embodiment of the present application provides a display panel 200, which includes the pixel circuit 100 provided in the above embodiment. As shown in fig. 10, in the display panel 200, the pixel circuits 100 may be arranged in an array along a first direction X and a second direction Y.

In the display panel 200, by providing the adjustment module 20 between the first node N1 and the second node N2 for neutralizing the potentials of the first node N1 and the second node N2, the potential difference between the first node N1 and the third node N3 and the potential difference between the second node N2 and the third node N3 can be reduced. That is, the potential difference between the first node N1, the second node N2 and the gate of the driving transistor Td is reduced, which is favorable for improving the problem of gate leakage of the driving transistor Td, stabilizing the gate potential of the driving transistor Td, further being favorable for avoiding the brightness of the display frame from generating large variation, and improving the display effect of the display panel.

The present embodiment provides a display device 300, as shown in fig. 11, the display device 300 includes the display panel 200 provided in the above embodiment. The display device 300 provided in the embodiment of the present application may be a mobile phone, and in addition, the display device 300 may also be an electronic device such as a computer and a television.

In the display apparatus 300, by providing the adjustment module 20 between the first node N1 and the second node N2 for neutralizing the potentials of the first node N1 and the second node N2, the potential difference between the first node N1 and the third node N3 and the potential difference between the second node N2 and the third node N3 can be reduced. That is, the potential difference between the first node N1, the second node N2 and the gate of the driving transistor Td is reduced, which is favorable for improving the problem of gate leakage of the driving transistor Td, stabilizing the gate potential of the driving transistor Td, further being favorable for avoiding the brightness of the display frame from generating large variation, and improving the display effect of the display panel.

The above description is only exemplary of the present application and should not be taken as limiting the present application, as any modification, equivalent replacement, or improvement made within the spirit and principle of the present application should be included in the scope of protection of the present application.

Claims

1. A pixel circuit, comprising:

a light emitting module;

the driving transistor is used for providing light-emitting driving current for the light-emitting module;

a first transistor and a second transistor, a first electrode of the first transistor being electrically connected to a first reset signal line, and a first electrode of the second transistor being electrically connected to a gate electrode of the driving transistor; a first node is included between the second pole of the first transistor and the second pole of the second transistor;

a third transistor and a fourth transistor, a first electrode of the third transistor being electrically connected to the second electrode of the driving transistor, and a first electrode of the fourth transistor being electrically connected to the gate electrode of the driving transistor; a second node is included between the second pole of the third transistor and the second pole of the fourth transistor;

the input end of the adjusting module is electrically connected with the first node, the output end of the adjusting module is electrically connected with the second node, and the adjusting module is used for adjusting the electric potentials of the first node and the second node.

2. The pixel circuit according to claim 1, wherein the adjusting module comprises a fifth transistor having a first pole electrically connected to the first node, a second pole electrically connected to the second node, and a gate electrically connected to the first signal line.

3. The pixel circuit according to claim 2, wherein the signal transmitted by the first signal line controls the fifth transistor to be turned off.

4. The pixel circuit according to claim 3, wherein the first signal line is electrically connected to a fixed-potential signal line.

5. The pixel circuit according to claim 4, wherein the fifth transistor is a P-type transistor, and wherein the first signal line is electrically connected to a direct-current high-potential signal line.

6. The pixel circuit according to claim 2, further comprising a data voltage writing module having an input terminal electrically connected to a data signal line and an output terminal electrically connected to the first pole of the driving transistor;

the working process of the pixel circuit comprises a data writing stage, and in the data writing stage, the data voltage writing module, the third transistor and the fourth transistor are started;

the signal transmitted by the first signal line controls the fifth transistor to be switched on after the data writing phase.

7. The pixel circuit according to claim 6, wherein the operation of the pixel circuit further comprises a light emission phase performed after the data writing phase;

the fifth transistor is turned on in the light emitting period.

8. The pixel circuit according to claim 7, further comprising a power supply voltage writing module and a light emission control module; the input end of the power supply voltage writing module is electrically connected with a power supply voltage signal wire, the output end of the power supply voltage writing module is electrically connected with the first pole of the driving transistor, and the control end of the power supply voltage writing module is electrically connected with a light-emitting control signal wire; the input end of the light-emitting control module is electrically connected with the second pole of the driving transistor, the output end of the light-emitting control module is electrically connected with the first pole of the light-emitting module, and the control end of the light-emitting control module is electrically connected with the light-emitting control signal line;

the first signal line is electrically connected with the light-emitting control signal line, and the signals transmitted by the light-emitting control signal line control the power voltage writing module, the light-emitting control module and the fifth transistor to have the same on-off state.

9. The pixel circuit according to claim 6, wherein the operation of the pixel circuit further comprises a conditioning phase and a light emitting phase sequentially performed after the data writing phase;

the fifth transistor is turned on during the regulation phase.

10. The pixel circuit according to claim 1, wherein a second pole of the first transistor is electrically connected to a second pole of the second transistor at the first node;

a second pole of the third transistor is electrically coupled to a second pole of the fourth transistor at the second node.

11. The pixel circuit according to claim 10, wherein a gate of the first transistor and a gate of the second transistor are electrically connected to a first scan line, and a signal transmitted from the first scan line controls switching states of the first transistor and the second transistor to be the same;

the grid electrode of the third transistor and the grid electrode of the fourth transistor are both electrically connected with a second scanning line, and the signal transmitted by the second scanning line controls the on-off states of the third transistor and the fourth transistor to be the same.

12. A display panel comprising a plurality of pixel circuits according to any one of claims 1 to 11.

13. A display device characterized by comprising the display panel according to claim 12.