CN114241998B

CN114241998B - Pixel circuit, display device and driving method of display device

Info

Publication number: CN114241998B
Application number: CN202111617896.4A
Authority: CN
Inventors: 李博资; 陈心全
Original assignee: Kunshan Govisionox Optoelectronics Co Ltd
Current assignee: Kunshan Govisionox Optoelectronics Co Ltd
Priority date: 2021-12-27
Filing date: 2021-12-27
Publication date: 2023-06-30
Anticipated expiration: 2041-12-27
Also published as: CN114241998A

Abstract

The embodiment of the invention discloses a pixel circuit, a display device and a driving method of the display device. The pixel circuit includes: the device comprises a driving module, a compensation module and a leakage suppression module; the compensation module comprises a first compensation unit and a second compensation unit, and the connection point of the first compensation unit and the second compensation unit is an intermediate node; the electric leakage suppression module comprises a control end, a voltage input end and a voltage output end; the control end of the leakage suppression module is connected with a first leakage control signal, the voltage input end of the leakage suppression module is connected with leakage suppression voltage, and the voltage output end of the leakage suppression module is electrically connected with the intermediate node; the first leakage control signal is provided by the driving chip, and the leakage suppression module is used for writing the leakage suppression voltage into the intermediate node in a blank stage after full-screen scanning. Compared with the prior art, the embodiment of the invention reduces the voltage difference between the control end of the driving module and the intermediate node, reduces the electric leakage of the transistor and improves the display effect of the display device.

Description

Pixel circuit, display device and driving method of display device

Technical Field

The embodiment of the invention relates to the technical field of display, in particular to a pixel circuit, a display device and a driving method of the display device.

Background

With the continuous development of display technology, the application range of display devices is becoming wider, and the requirements of people on the display devices are also becoming higher. For example, the display device can be compatible with high-frequency display, low-frequency display, and the like. However, since the transistor in the pixel circuit has a natural leakage characteristic, the leakage characteristic of the transistor has a large influence on display at the time of low-frequency display, and a phenomenon of picture or flicker is likely to occur.

Disclosure of Invention

The embodiment of the invention provides a pixel circuit, a display device and a driving method of the display device, so as to reduce the electric leakage of a transistor and improve the display effect of the display device.

In order to achieve the technical purpose, the embodiment of the invention provides the following technical scheme:

a pixel circuit includes:

the driving module comprises a control end, a data input end and a data output end; the data input end is used for accessing a data signal in a data writing stage, and the driving module is used for conducting in the data writing stage, so that the data signal is written into the data output end by the data input end;

the compensation module comprises a first compensation unit and a second compensation unit, the first compensation unit and the second compensation unit are connected between the data output end and the control end of the driving module, and the connection point of the first compensation unit and the second compensation unit is an intermediate node; the compensation module is used for being conducted in the data writing stage, and writing the data signals into the control end of the data signal from the data output end of the driving module;

The leakage suppression module comprises a control end, a voltage input end and a voltage output end; the control end of the leakage suppression module is connected with a first leakage control signal, the voltage input end of the leakage suppression module is connected with a leakage suppression voltage, and the voltage output end of the leakage suppression module is electrically connected with the intermediate node; the first leakage control signal is provided by a driving chip, and the leakage suppression module is used for writing the leakage suppression voltage into the intermediate node in a blank stage after full-screen scanning, so that the voltage difference between the control end of the driving module and the intermediate node is reduced.

Further, the first compensation unit comprises a control end, a first end and a second end, the control end of the first compensation unit is connected with a first scanning signal, the first end of the first compensation unit is electrically connected with the control end of the driving module, and the second end of the first compensation unit is used as the intermediate node;

the second compensation unit comprises a control end, a first end and a second end, the control end of the second compensation unit is connected with a second electric leakage control signal, the first end of the second compensation unit is electrically connected with the second end of the first compensation unit, and the second end of the second compensation unit is electrically connected with the data output end of the driving module;

The first scanning signal is provided by a scanning circuit, and the second leakage control signal is provided by the driving chip;

preferably, the on average of the first leakage control signal and the second leakage control signal is high level or is low level, and the levels of the first leakage control signal and the second leakage control signal are kept opposite;

or the conducting level of the first leakage control signal is the same as that of the second leakage control signal, the level of the first leakage control signal is the same as that of the second leakage control signal, and the first leakage control signal is multiplexed into the second leakage control signal.

the second compensation unit comprises a control end, a first end and a second end, the control end of the second compensation unit is connected with the first scanning signal, the first end of the second compensation unit is electrically connected with the second end of the first compensation unit, and the second end of the second compensation unit is electrically connected with the data output end of the driving module;

The first scanning signal is provided by a scanning circuit, and the on-off states of the first compensation unit and the second compensation unit are the same.

Further, the first compensation unit comprises a first transistor, wherein a gate of the first transistor is used as a control end of the first compensation unit, a first pole of the first transistor is used as a first end of the first compensation unit, and a second pole of the first transistor is used as a second end of the first compensation unit;

the second compensation unit comprises a second transistor, wherein the grid electrode of the second transistor is used as the control end of the second compensation unit, the first electrode of the second transistor is used as the first end of the second compensation unit, and the second electrode of the second transistor is used as the second end of the second compensation unit;

preferably, the first transistor and the second transistor are P-type transistors, or the first transistor and the second transistor are N-type transistors.

Further, the leakage suppression module includes a third transistor, a gate of the third transistor is used as a control end of the leakage suppression module, a first pole of the third transistor is used as a voltage input end of the leakage suppression module, and a second pole of the third transistor is used as a voltage output end of the leakage suppression module;

Preferably, the third transistor is a P-type transistor or an N-type transistor.

Further, the pixel circuit further includes: the grid initialization module comprises a control end, a first end and a second end, wherein the control end of the grid initialization module is connected with a second scanning signal, the first end of the grid initialization module is connected with an initialization voltage, and the second end of the grid initialization module is electrically connected with the control end of the driving module;

preferably, the initialization voltage is opposite in level in a full-screen scanning phase and a blank phase.

Further, the driving module includes a driving transistor;

the driving transistor is a P-type transistor, and the value of the data signal is between the first data voltage and the second data voltage; the value of the initialization voltage is lower than the first data voltage, and the leakage suppression voltage is greater than or equal to the first data voltage;

or the driving transistor is an N-type transistor, and the value of the data signal is between the third data voltage and the fourth data voltage; the value of the initialization voltage is higher than the fourth data voltage, and the leakage suppression voltage is smaller than or equal to the fourth data voltage.

Further, the leakage suppression voltage is provided by a driving chip; or the data signal is multiplexed as the leakage suppression voltage.

In a second aspect, an embodiment of the present invention further provides a display apparatus, including: a driving chip and a plurality of pixel circuits according to any of the embodiments of the present invention; the driving chip is electrically connected with a plurality of pixel circuits.

In a third aspect, an embodiment of the present invention further provides a driving method of a display device, which is applicable to the display device provided in any embodiment of the present invention; the driving method of the display device includes:

a full-screen scanning stage, wherein the scanning circuit controls the pixel circuits to scan line by line; in the data writing stage of line scanning, a data signal is written into a data input end of the driving module, the compensation module is conducted with the driving module, and the data signal is written into a control end of the driving module through the data input end of the driving module;

and in a blank stage after full-screen scanning, the driving chip controls the electric leakage suppression modules in the pixel circuits to be conducted, electric leakage suppression voltage is written into the middle nodes of the pixel circuits, and the voltage difference between the control ends of the driving modules in the pixel circuits and the middle nodes is reduced.

The compensation module comprises a first compensation unit and a second compensation unit which are connected between a data output end and a control end of the driving module, and an intermediate node is added between a first node and a third node. And the voltage of the intermediate node can be subjected to voltage adjustment under the control of the leakage suppression module. The smaller the voltage difference between the first node and the intermediate node, the smaller the leakage current of the first compensation unit, and accordingly, the more stable the potential of the first node. The embodiment of the invention sets the first leakage control signal to be provided by the driving chip, so that the leakage suppression module can be used for writing the leakage suppression voltage into the intermediate node in the blank stage after full-screen scanning, and is also beneficial to electrically connecting the first leakage control signals of all pixel circuits in the display device, and the driving chip provides the first leakage control signal. In this case, the first leakage control signal does not need to be supplied from the scanning circuit, and thus the structure of the scanning circuit does not need to be changed. In summary, the embodiment of the invention realizes the effect of reducing the leakage of the transistor on the basis of simplifying the circuit design, and realizes the leakage inhibition of the first node.

Drawings

FIG. 1 is a schematic diagram of a conventional pixel circuit;

FIG. 2 is a schematic diagram of a driving timing sequence of the pixel circuit shown in FIG. 1;

fig. 3 is a schematic circuit diagram of a portion of a pixel circuit according to an embodiment of the present invention;

fig. 4 is a timing diagram of a display device according to an embodiment of the invention;

FIG. 5 is a schematic diagram of a portion of another pixel circuit according to an embodiment of the present invention;

FIG. 6 is a schematic diagram of a portion of a pixel circuit according to an embodiment of the present invention;

FIG. 7 is a timing diagram of another display device according to an embodiment of the invention;

fig. 8 is a schematic circuit diagram of a pixel circuit according to an embodiment of the present invention;

fig. 9 is a schematic structural diagram of a display device according to an embodiment of the present invention;

fig. 10 is a flowchart illustrating a driving method of a display device according to an embodiment of the invention.

Detailed Description

The invention is described in further detail below with reference to the drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting thereof. It should be further noted that, for convenience of description, only some, but not all of the structures related to the present invention are shown in the drawings.

As described in the background art, the existing display device has a problem of transistor leakage, thereby causing a phenomenon of picture or flicker. The inventors have found that the cause of this problem is as follows.

Fig. 1 is a circuit schematic diagram of a conventional pixel circuit. Referring to fig. 1, the pixel circuit is of a 7T1C structure, and specifically, includes a transistor T1', a transistor T2', a transistor T3', a transistor T4', a transistor T5', a transistor T6', a transistor T7', and a capacitor Cst'. The transistor T1 'is a driving transistor, the other transistors are switching transistors, and the capacitor Cst' is a storage capacitor for maintaining the potential of the gate (node N1 ') of the transistor T1' stable. However, since the transistor has a natural leakage characteristic, the transistor has a leakage current in an off state, and the problem caused by the leakage of the transistor T3' and the transistor T5' is particularly serious for the pixel circuit, so that the potential of the node N1' is unstable. The arrow in fig. 1 indicates the leakage path of the node N1', and the stability of the driving current generated by the transistor T1' is affected due to the instability of the node N1 '.

Fig. 2 is a schematic diagram of a driving timing sequence of the pixel circuit shown in fig. 1. Referring to fig. 1 and 2, the driving timing of the pixel circuit in one frame includes an initialization phase t11, a data write access ticket t12, and a light-emitting phase t13.

In the initialization stage T11, the scan signal Sn-1 is low, the scan signal Sn is high, the light emission control signal En is high, the scan signal Sn-1 controls the transistors T5 'and T6' to be turned on, the initialization voltage Vref is written into the node N1 'through the transistor T5', and the initialization voltage Vref is written into the anode of the light emitting device OLED 'through the transistor T6'. The initialization of the node N1' ensures that the transistor T1' is in a turned-on state at the beginning of the next stage, and the initialization of the light emitting device OLED ' can avoid the influence of the display brightness of the previous frame on the display brightness of the current frame. Thus, the transistor T5 'is also called a gate initialization transistor, and the transistor T6' is also called an anode initialization transistor.

In the data writing stage T12, the scan signal Sn-1 is at a high level, the scan signal Sn is at a low level, the light emission control signal En is at a high level, the scan signal Sn controls the transistors T2' and T3' to be turned on, and the data signal Dm is written into the node N1' through the turned-on transistors T2', T1' and T3', thereby completing the threshold voltage compensation and the data writing to the transistor T1 '. The transistor T2 'is also called a data writing transistor, and the transistor T3' is also called a compensation transistor.

In the light emitting period T13, the scan signal Sn-1 is high, the scan signal Sn is high, and the light emitting control signal En is low, and the light emitting control signal En controls the transistors T4 'and T7' to be turned on, thereby turning on the driving current path between the first power source ELVDD and the second power source ELVSS. The transistor T4 'and the transistor T7' are also called light emission control transistors. Since the node N1' stores the data signal Dm, the transistor T1' generates a driving current of a corresponding magnitude to drive the light emitting device OLED ' to emit light.

However, during the light emitting period of the light emitting device OLED ', the node N1' continuously leaks electricity through the transistor T3 'and the transistor T5', so that the voltage of the node N1 'deviates, the driving current deviates, and the light emitting brightness of the light emitting device OLED' deviates. And this deviation becomes more serious as the light emission period t13 is prolonged. For example, for a display device with a lower refresh frequency, the time of the light-emitting phase t13 is longer; in another example, when down-conversion is performed in a frame-skip manner, it is necessary to multiply the time of the light-emitting period t13 in the case where the initialization period t11 and the data writing period t12 are performed once. Therefore, at the time of low-frequency display, the display screen generates a phenomenon of picture or flicker.

In view of this, the embodiment of the invention provides a pixel circuit. Fig. 3 is a schematic circuit diagram of a portion of a pixel circuit according to an embodiment of the present invention. Referring to fig. 3, the pixel circuit includes a driving module 100, a compensation module 200, and a leakage suppression module 300. The driving module 100 includes a control terminal 103, a data input terminal 101, and a data output terminal 102; the data input terminal 101 is used for accessing a data signal during a data writing phase, and the driving module 100 is used for conducting during the data writing phase, and writing the data signal from the data input terminal 101 to the data output terminal 102. The compensation module 200 includes a first compensation unit 210 and a second compensation unit 220, where the first compensation unit 210 and the second compensation unit 220 are connected between the data output terminal 102 and the control terminal 103 of the driving module 100, and a connection point of the first compensation unit 210 and the second compensation unit 220 is an intermediate node N2; the compensation module 200 is used for conducting in the data writing stage, and writing the data signal into the control terminal 103 of the driving module 100 from the data output terminal 102. The control terminal 103 is defined as a first node N1, and the data output terminal 102 is defined as a third node N3.

The leakage suppression module 300 includes a control terminal 303, a voltage input terminal 301, and a voltage output terminal 302; the control end 303 of the leakage suppression module 300 is connected to the first leakage control signal Cont1, the voltage input end 301 of the leakage suppression module 300 is connected to the leakage suppression voltage Vrefp, and the voltage output end 302 of the leakage suppression module 300 is electrically connected to the intermediate node N2; the first leakage control signal Cont1 is provided by the driving chip, and the leakage suppression module 300 is configured to write the leakage suppression voltage Vrefp into the intermediate node N2 during a blank period after full-screen scanning, so as to reduce a voltage difference between the control terminal 103 and the intermediate node N2.

Unlike the prior art, the compensation module 200 according to the embodiment of the present invention includes a first compensation unit 210 and a second compensation unit 220 connected to each other, and an intermediate node N2 is added between the first node N1 and the third node N3. And the voltage of the intermediate node N2 may be voltage-adjusted under the control of the leakage suppression module 300. The first compensation unit 210 is directly connected to the first node N1, and the leakage magnitude directly affects the state of the first node N1. The first compensation unit 210 is formed by a transistor, and the first node N1 and the intermediate node N2 are respectively disposed at two ends of the first compensation unit 210, and as is known from the characteristics of the transistor, the smaller the voltage difference between the first node N1 and the intermediate node N2 is, the smaller the leakage current of the first compensation unit 210 is, and accordingly, the more stable the potential of the first node N1 is.

Fig. 4 is a timing diagram of a display device according to an embodiment of the invention. Referring to fig. 4, the tearing effect signal TE is generated by the driving chip, and the processor transmits the next frame of image data to the driving chip, illustratively, after hearing the rising edge or high state of the tearing effect signal TE. Therefore, the embodiment of the invention uses the tearing effect signal TE to represent the duration of one frame. Signals S0 to Sn represent scanning signals of the pixel circuits of each row, and signals E1 to En represent light emission control signals of the pixel circuits of each row. As can be seen from fig. 4, one frame of display can be divided into a full-screen scan phase T1 and a blank phase T2. In a full-screen scanning stage T1, scanning signals and light-emitting control signals scan pixel circuits row by row, each row of pixel circuits sequentially perform an initialization stage and a data writing stage until the scanning is finished, and the last row of pixel circuits are in a light-emitting stage. After entering the blank phase T2, all the pixel circuits are in the light emitting phase. Since the time of the full-screen scanning phase T1 of the high-frequency display and the low-frequency display is unchanged, the difference is only the time of the blank phase T2, so it is particularly important to reduce the leakage current of the first node N1 in the blank phase T2.

The embodiment of the invention sets the first leakage control signal Cont1 to be provided by the driving chip, so that the leakage suppression module 300 not only can be used for writing the leakage suppression voltage Vrefp into the intermediate node N2 in the blank stage T2 after full-screen scanning, but also is beneficial to electrically connecting the first leakage control signals Cont1 of all pixel circuits in the display device, and the driving chip provides the first leakage control signal Cont1. In this way, the first leakage control signal Cont1 does not need to be supplied from the scanning circuit, and the structure of the scanning circuit does not need to be changed. In summary, the embodiment of the present invention achieves the effect of reducing the leakage current of the transistor on the basis of simplifying the circuit design, and achieves the leakage current suppression of the first node N1.

With continued reference to fig. 3, the first compensation unit 210 may optionally include a control terminal, a first terminal and a second terminal, where the control terminal of the first compensation unit 210 is connected to the first scan signal Sn, and the first terminal of the first compensation unit 210 is electrically connected to the control terminal 103 of the driving module 100, and the second terminal of the first compensation unit 210 is used as the intermediate node N2. The second compensation unit 220 includes a control end, a first end and a second end, the control end of the second compensation unit 220 is connected to the second leakage control signal Cont2, the first end of the second compensation unit 220 is electrically connected to the second end of the first compensation unit 210, and the second end of the second compensation unit 220 is electrically connected to the data output end 102 of the driving module 100. The first scan signal Sn is provided by the scan circuit, and the second leakage control signal Cont2 is provided by the driving chip. In this way, the connection mode of the first compensation unit 210 and the second compensation unit 220 is realized, but the control signals of the two are connected with different signals. Specifically, the second leakage control signal Cont2 controls the second compensation unit 220 to be turned on during the full-screen scanning stage T1 to ensure that the data signal can be written into the first node N1. The second leakage control signal Cont2 controls the second compensation unit 220 to be turned off during the blank period T2 to disconnect the electrical connection between the intermediate node N2 and the third node N3, so as to avoid the leakage suppression voltage Vrefp from interfering with the voltage of the third node N3.

On the basis of the above embodiments, optionally, the working states of the second compensation unit 220 and the leakage suppression module 300 are opposite, that is, the second compensation unit 220 is turned on in the full-screen scanning stage T1, and the leakage suppression module 300 is turned off in the full-screen scanning stage T1, so as to ensure that the pixel circuit normally completes the initialization stage and the data writing stage; the second compensation unit 220 is turned off in the blank period T2, and the leakage suppression module 300 is turned on in the blank period T2 to maintain the potential of the intermediate node N2 close to the potential of the first node N1 without affecting the potential of the third node N3.

The level states of the first leakage control signal Cont1 and the second leakage control signal Cont2 are set according to the specific arrangement of the leakage suppression module 300 and the second compensation unit 220. Alternatively, the on-levels of the first leakage control signal Cont1 and the second leakage control signal Cont2 are averaged to be high level or both low levels, and the levels of the first leakage control signal Cont1 and the second leakage control signal Cont2 are kept opposite to control the working states of the leakage suppression module 300 and the second compensation unit 220 to be opposite.

Alternatively, the first leakage control signal Cont1 and the second leakage control signal Cont2 have the same on level, the first leakage control signal Cont1 and the second leakage control signal Cont2 have the same level, and the first leakage control signal Cont1 is multiplexed into the second leakage control signal Cont2 to control the operation states of the leakage suppression module 300 and the second compensation unit 220 to be opposite.

Fig. 5 is a schematic circuit diagram of a portion of another pixel circuit according to an embodiment of the invention. Referring to fig. 5, the first compensation unit 210 may optionally include a first transistor T1, where a gate of the first transistor T1 is used as a control terminal of the first compensation unit 210, and is connected to the first scan signal Sn. A first pole of the first transistor T1 is electrically connected to the first node N1 as a first terminal of the first compensation unit 210. The second terminal of the first transistor T1 is electrically connected to the intermediate node N2 as the second terminal of the first compensation unit 210. The second compensation unit 220 includes a second transistor T2, and a gate of the second transistor T2 is used as a control terminal of the second compensation unit 220 and is connected to the second leakage control signal Cont2. A first pole of the second transistor T2 is electrically connected to the intermediate node N2 as a first terminal of the second compensation unit 220. The second terminal of the second transistor T2 is electrically connected to the third node N3 as the second terminal of the second compensation unit 220.

With continued reference to fig. 5, the leakage suppression module 300 may optionally include a third transistor T3, where a gate of the third transistor T3 is used as a control terminal of the leakage suppression module 300 and is connected to the first leakage control signal Cont1. The first electrode of the third transistor T3 is used as a voltage input terminal of the leakage suppression module 300, and is connected to the leakage suppression voltage Vrefp. The second pole of the third transistor T3 is electrically connected to the intermediate node N2 as the voltage output terminal of the leakage suppression module 300.

With continued reference to fig. 5, the first transistor T1, the second transistor T2, and the third transistor T3 are optionally P-type transistors or N-type transistors. By the arrangement, the channel types of the transistors are the same, and the transistors can be manufactured in the same process, so that the manufacturing process is simplified.

In other embodiments, the channel types of the second transistor T2 and the third transistor T3 may also be set to be different, for example, the second transistor T2 is an N-type transistor, and the third transistor T3 is a P-type transistor; alternatively, the second transistor T2 is a P-type transistor, and the third transistor T3 is an N-type transistor. Thus, the first leakage control signal Cont1 may be multiplexed into the second leakage control signal Cont2 to control the second transistor T2 and the third transistor T3 to be in opposite operation states.

In the above embodiments, the control terminals of the leakage suppression module 300 and the second compensation unit 220 are connected to the driving chip, which is not a limitation of the present invention. Fig. 6 is a schematic circuit diagram of a portion of a pixel circuit according to another embodiment of the present invention. Referring to fig. 6, in another embodiment of the present invention, optionally, the control terminal of the first compensation unit 210 and the control terminal of the second compensation unit 220 are both connected to the first scan signal Sn. The first scan signal Sn is provided by the scan circuit, and the on-off states of the first compensation unit 210 and the second compensation unit 220 are the same. Specifically, in the full-screen scanning stage T1, taking a row of pixel circuits as an example, in the data writing stage, the first scanning signal Sn controls the first compensation unit 210 and the second compensation unit 220 to be turned on simultaneously, and the data signal is written from the third node N3 to the first node N1; in the light emitting stage, the first scan signal Sn controls the first compensation unit 210 and the second compensation unit 220 to be turned off simultaneously, and the voltage of the intermediate node N2 does not affect the voltage of the third node N3.

With continued reference to fig. 6, the drive module 100 optionally includes a drive transistor DT on the basis of the embodiments described above. The gate of the driving transistor DT serves as a control terminal of the driving module and is electrically connected to the first node N1. The first pole of the driving transistor DT is used as a data input of the driving module for accessing the data signal. The second pole of the driving transistor DT is electrically connected to the third node N3 as a data output terminal of the driving module. The channel type of the driving transistor DT determines a supply manner of the data signal, and if the driving transistor DT is a P-type transistor, the driving transistor DT is turned on under the control of a low level, that is, when the gate voltage of the driving transistor DT is lower than the voltage of the first pole, the driving transistor DT is turned on; if the driving transistor DT is an N-type transistor, the driving transistor DT is turned on under the control of a high level, i.e., when the gate voltage of the driving transistor is higher than the voltage of the first pole, the driving transistor DT is turned on.

With reference to fig. 3, 5 and 6, the pixel circuit may further include: the gate initialization module 400, the gate initialization module 400 includes a control end, a first end and a second end, the control end of the gate initialization module 400 is connected to the second scan signal Sn-1, the first end of the gate initialization module 400 is connected to the initialization voltage Vref, and the second end of the gate initialization module 400 is electrically connected to the control end (the first node N1) of the driving module 100. The gate initialization module 400 is configured to initialize the first node N1, and writing of the initialization voltage Vref can ensure that the driving module 100 is in a conductive state during the data writing stage.

On the basis of the above embodiments, the embodiments of the present invention further define the numerical ranges of the initialization voltage Vref and the leakage suppression voltage Vrefp. In one embodiment, optionally, the driving transistor DT is a P-type transistor, and the value of the data signal is between the first data voltage and the second data voltage; the value of the initialization voltage Vref is lower than the first data voltage, and the leakage suppression voltage Vrefp is greater than or equal to the first data voltage. The first data voltage is, for example, 3V and the second data voltage is 7V, i.e., the voltage of the gate of the driving transistor DT is approximately between 3V and 7V. Then, the value of the initialization voltage Vref is lower than 3V, preferably a negative value, to initialize the driving transistor DT. The leakage suppression voltage Vrefp is greater than or equal to 3V, for example, when the voltage of the first node N1 is 3V and the voltage of the intermediate node N2 is also 3V, the voltage difference between the first node N1 and the intermediate node N2 is 0, and the first transistor T1 does not generate leakage current; as another example, when the voltage of the first node N1 is 7V and the voltage of the intermediate node N2 is 3V, the voltage difference between the first node N1 and the intermediate node N2 is 4V, and the voltage difference is smaller, and the leakage current generated by the first transistor T1 is smaller. Therefore, in the embodiment of the invention, when the driving transistor DT is a P-type transistor, the leakage suppression voltage Vrefp is set to be greater than or equal to the first data voltage, which is favorable for making the voltage difference between the first node N1 and the intermediate node N2 smaller.

In another embodiment, optionally, the driving transistor DT is an N-type transistor, and the value of the data signal is between the third data voltage and the fourth data voltage; the value of the initialization voltage Vref is higher than the fourth data voltage, and the leakage suppression voltage Vrefp is less than or equal to the fourth data voltage. This arrangement is advantageous in that the voltage difference between the first node N1 and the intermediate node N2 is small in the case where the driving transistor DT is an N-type transistor.

On the basis of the above embodiments, optionally, the leakage suppression voltage is provided by the driving chip; or the data signal is multiplexed as the leakage suppression voltage. If the data signal is multiplexed to the leakage suppression voltage, the voltage of the data signal in the blanking period T2 may be set to be constant, and the constant value may be set as in the foregoing embodiment, or the value at the time of scanning the last row of pixels may be maintained.

In the above embodiments, the leakage path suppression scheme of the compensation module 200 is described, and the leakage path suppression scheme of the gate initialization module 400 is described below. Fig. 7 is a timing diagram of another display device according to an embodiment of the invention. With reference to fig. 6 and 7, the levels of the initialization voltage Vref in the full-screen scan period T1 and the blank period T2 are optionally opposite based on the above embodiments. Illustratively, the driving transistor DT is a P-type transistor, and in the full-screen scanning stage T1, the initialization voltage Vref is low level to realize initialization of the driving transistor DT; in the blank period T2, the voltage of the initialization voltage Vref increases to suppress the leakage current of the gate initialization module 400. The value of the initialization voltage Vref in the blank period T2 may refer to the setting mode of the leakage suppression voltage Vrefp, which is not described herein.

With continued reference to fig. 7, alternatively, the scan signal S0 is a second scan signal of the first row of pixel circuits, and the scan signal S1 is a first scan signal of the first row of pixel circuits; the scan signal S1 is also used as the second scan signal of the second row of pixel circuits, … …, and so on, and the scan signal Sn is used as the first scan signal of the nth row of pixel circuits. It can be seen that the embodiment of the invention adopts a set of scanning circuits, and can meet the requirements of the pixel circuits on two scanning signals through the progressive multiplexing of the scanning signals.

Fig. 8 is a schematic circuit diagram of a pixel circuit according to an embodiment of the present invention. Referring to fig. 8, optionally, the pixel circuit further includes a data writing module 500, where the data writing module 500 includes a control terminal, a first terminal and a second terminal, a gate of the data writing module 500 is connected to the first scan signal Sn, a first terminal of the data writing module 500 is connected to the data signal Dm, and the second terminal of the data writing module is electrically connected to the data input terminal of the driving module 100. The data writing module 500 is used for conducting in a data writing phase and writing a data signal into a data input terminal of the driving module 100.

Optionally, the data writing module 500 includes a fifth transistor T5, and a gate of the fifth transistor T5 is used as a control terminal of the data writing module 500, and is connected to the first scan signal Sn. The first pole of the fifth transistor T5 is connected to the data signal Dm as the first terminal of the data writing module 500. The second terminal of the fifth transistor T5 is electrically connected to the data input terminal of the driving module 100 as the second terminal of the data writing module 500.

With continued reference to fig. 8, the pixel circuit optionally further includes an anode initialization module 600, the anode initialization module 600 including a control terminal, a first terminal, and a second terminal. The control end of the anode initialization module 600 is connected to the second scan signal Sn-1, the first end of the anode initialization module 600 is connected to the initialization voltage Vref, and the second end of the anode initialization module 600 is electrically connected to the light emitting device OLED. The anode initialization module 600 is used for conducting in an initialization stage, and writing an initialization voltage Vref to the anode of the light emitting device OLED.

Optionally, the anode initialization module includes a sixth transistor T6, and a gate of the sixth transistor T6 is used as a control terminal of the anode initialization module 600, and is connected to the second scan signal Sn-1. The first pole of the sixth transistor T6 is used as the first terminal of the anode initialization module 600, and is connected to the initialization voltage Vref. The second terminal of the sixth transistor T6 is electrically connected to the light emitting device OLED as the second terminal of the anode initialization module 600.

With continued reference to fig. 8, the pixel circuit optionally further includes a light emission control module 700, the light emission control module 700 including a first control terminal, a second control terminal, a first terminal, a second terminal, a third terminal, and a fourth terminal. The first control end and the second control end of the light emitting control module 700 are both connected with a light emitting control signal En, the first end of the light emitting control module 700 is connected with a first power supply ELVDD, the second end of the light emitting control module 700 is electrically connected with the data input end of the driving module 100, the third end of the light emitting control module 700 is electrically connected with the data output end of the driving module 100, and the fourth end of the light emitting control module 700 is electrically connected with the light emitting device OLED. The light emitting control module 700 is used for conducting in the light emitting stage to conduct the driving current path.

Optionally, the light-emitting control module 700 includes a seventh transistor T7 and an eighth transistor T8, where a gate of the seventh transistor T7 is used as a first control terminal of the light-emitting control module 700, and is connected to the light-emitting control signal En. A first electrode of the seventh transistor T7 is connected to the first power ELVDD as a first terminal of the light emission control module 700. A second terminal of the seventh transistor T7 is electrically connected to the data input terminal of the driving module 100 as a second terminal of the light emission control module 700. The gate of the eighth transistor T8 is used as a second control terminal of the light emission control module 700, and is connected to the light emission control signal En. The first electrode of the eighth transistor T8 is electrically connected to the data output terminal of the driving module 100 as the third terminal of the light emission control module 700. The second electrode of the eighth transistor T8 is electrically connected to the light emitting device OLED as the eighth fourth terminal of the light emission control module 700.

With continued reference to fig. 8, the pixel circuit may further include a memory module 800, a first end of the memory module 800 is connected to the first power ELVDD, a second end of the memory module 800 is electrically connected to the control end of the driving module 100, and the memory module 800 is configured to store potential stabilization of the control end of the driving module 100.

Optionally, the memory module 800 includes a storage capacitor Cst, a first electrode of which is used as a first terminal of the memory module 800, and is connected to the first power source ELVDD. The second pole of the storage capacitor Cst serves as a second terminal of the storage module 800 and is electrically connected to the control terminal of the driving module 100.

The embodiment of the invention also provides a display device. Fig. 9 is a schematic structural diagram of a display device according to an embodiment of the present invention. Referring to fig. 9, the display device includes: the driving chip 1 and the pixel circuits 2 provided by any embodiment of the invention have corresponding beneficial effects. The driving chip 1 is electrically connected to the plurality of pixel circuits 2, and is configured to provide a first leakage control signal to all of the pixel circuits 2.

With continued reference to fig. 9, the display device optionally further includes a scanning circuit 3, and output terminals of each stage of the scanning circuit 3 are electrically connected to each row of pixel circuits 2, respectively, for providing the pixel circuits 2 with a first scanning signal and a second scanning signal.

Therefore, the embodiment of the invention sets the first leakage control signal provided by the driving chip 1, so that the leakage suppression module can be used for writing the leakage suppression voltage into the intermediate node in the blank stage after full-screen scanning, and is also beneficial to electrically connecting the first leakage control signals of all the pixel circuits 2 in the display device, and the driving chip 1 provides the first leakage control signal. In this way, the first leakage control signal does not need to be supplied from the scanning circuit 3, and thus the structure of the scanning circuit 3 does not need to be changed. In summary, the embodiment of the invention realizes the effect of reducing the leakage of the transistor on the basis of simplifying the circuit design, and realizes the leakage inhibition of the first node.

The embodiment of the invention also provides a driving method of the display device, which is suitable for the display device provided by any embodiment of the invention and has corresponding beneficial effects. Fig. 10 is a flowchart illustrating a driving method of a display device according to an embodiment of the invention. Referring to fig. 10, the driving method includes the steps of:

s110, in a full-screen scanning stage, the scanning circuit controls a plurality of pixel circuits to scan line by line.

In the data writing stage of line scanning, data signals are written into the data input end of the driving module, the compensation module is conducted with the driving module, and the data signals are written into the control end of the driving module through the data input end of the driving module.

And S120, in a blank stage after full-screen scanning, the driving chip controls the electric leakage suppression modules in the pixel circuits to be conducted, electric leakage suppression voltages are written into intermediate nodes of the pixel circuits, and voltage difference between control ends of the driving modules in the pixel circuits and the intermediate nodes is reduced.

On the basis of the above embodiments, the driving method is optionally applicable to a case where the time of the blank phase is longer than the one-frame display time, for example, a case where the low-frequency display is realized in a frame skip manner.

Note that the above is only a preferred embodiment of the present invention and the technical principle applied. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, while the invention has been described in connection with the above embodiments, the invention is not limited to the embodiments, but may be embodied in many other equivalent forms without departing from the spirit or scope of the invention, which is set forth in the following claims.

Claims

1. A pixel circuit, comprising:

The leakage suppression module comprises a control end, a voltage input end and a voltage output end; the control end of the leakage suppression module is connected with a first leakage control signal, the voltage input end of the leakage suppression module is connected with a leakage suppression voltage, and the voltage output end of the leakage suppression module is electrically connected with the intermediate node; the first leakage control signal is provided by a driving chip, and the leakage suppression module is used for writing the leakage suppression voltage into the intermediate node in a blank stage after full-screen scanning, so that the voltage difference between the control end of the driving module and the intermediate node is reduced; wherein, a frame of display is divided into a full-screen scanning stage and a blank stage, in the full-screen scanning stage, a scanning circuit controls a plurality of pixel circuits to scan line by line until the scanning is finished, the pixel circuit in the last line is in a light-emitting stage, and after entering the blank stage, all the pixel circuits are in the light-emitting stage.

2. The pixel circuit according to claim 1, wherein the first compensation unit includes a control terminal, a first terminal and a second terminal, the control terminal of the first compensation unit is connected to a first scanning signal, the first terminal of the first compensation unit is electrically connected to the control terminal of the driving module, and the second terminal of the first compensation unit is used as the intermediate node;

the first scanning signal is provided by a scanning circuit, and the second leakage control signal is provided by the driving chip.

3. The pixel circuit according to claim 2, wherein the on-levels of the first and second leakage control signals are either both high or low, the levels of the first and second leakage control signals remaining opposite;

4. The pixel circuit according to claim 1, wherein the first compensation unit includes a control terminal, a first terminal and a second terminal, the control terminal of the first compensation unit is connected to a first scanning signal, the first terminal of the first compensation unit is electrically connected to the control terminal of the driving module, and the second terminal of the first compensation unit is used as the intermediate node;

5. The pixel circuit according to claim 2 or 4, wherein the first compensation unit comprises a first transistor, a gate of the first transistor being a control terminal of the first compensation unit, a first pole of the first transistor being a first terminal of the first compensation unit, a second pole of the first transistor being a second terminal of the first compensation unit;

the second compensation unit comprises a second transistor, wherein a grid electrode of the second transistor is used as a control end of the second compensation unit, a first electrode of the second transistor is used as a first end of the second compensation unit, and a second electrode of the second transistor is used as a second end of the second compensation unit.

6. The pixel circuit according to claim 5, wherein the first transistor and the second transistor are each P-type transistors or the first transistor and the second transistor are each N-type transistors.

7. The pixel circuit of claim 1, wherein the leakage suppression module comprises a third transistor having a gate as a control terminal of the leakage suppression module, a first electrode of the third transistor as a voltage input terminal of the leakage suppression module, and a second electrode of the third transistor as a voltage output terminal of the leakage suppression module.

8. The pixel circuit according to claim 7, wherein the third transistor is a P-type transistor or an N-type transistor.

9. The pixel circuit of claim 1, further comprising: the grid initialization module comprises a control end, a first end and a second end, wherein the control end of the grid initialization module is connected with a second scanning signal, the first end of the grid initialization module is connected with initialization voltage, and the second end of the grid initialization module is electrically connected with the control end of the driving module.

10. The pixel circuit of claim 9, wherein the initialization voltage is at opposite levels during a full-screen scan phase and a blank phase.

11. The pixel circuit of claim 9, wherein the drive module comprises a drive transistor;

12. The pixel circuit according to claim 1, wherein the leakage suppression voltage is provided by a drive chip; or the data signal is multiplexed as the leakage suppression voltage.

13. A display device, comprising: a driver chip and a plurality of pixel circuits according to any one of claims 1 to 12; the driving chip is electrically connected with a plurality of pixel circuits.

14. A driving method of a display device, wherein the display device includes a scanning circuit, a driving chip, and a plurality of pixel circuits, the pixel circuits including: the device comprises a driving module, a compensation module and a leakage suppression module; the compensation module comprises a first compensation unit and a second compensation unit, and the connection point of the first compensation unit and the second compensation unit is an intermediate node; one frame of display is divided into a full-screen scanning stage and a blank stage; the driving method of the display device includes: