CN213042122U

CN213042122U - Dead time control device of high-speed sine-gate single photon detector

Info

Publication number: CN213042122U
Application number: CN202022039259.0U
Authority: CN
Inventors: 慈兆会; 祁留锋; 陆飞
Original assignee: Beijing Zhongchuangwei Nanjing Quantum Communication Technology Co ltd
Current assignee: Beijing Zhongchuangwei Nanjing Quantum Communication Technology Co ltd
Priority date: 2020-09-16
Filing date: 2020-09-16
Publication date: 2021-04-23
Anticipated expiration: 2030-09-16

Abstract

The application provides a high-speed sine gate single photon detector dead time control device which comprises an FPGA, a sine signal generation module, a gate control module, a single photon avalanche diode, an avalanche discrimination module and a signal extraction module, wherein the FPGA, the sine signal generation module, the gate control module, the single photon avalanche diode, the avalanche discrimination module and the signal extraction module are sequentially and electrically connected; the FPGA is electrically connected with the input end of the sine signal generation module by adopting a high-speed communication interface, and the output end of the signal extraction module is electrically connected with the FPGA. When the single-photon avalanche diode needs to enter a dead time state, the FPGA does not output square wave signals in the dead time period, when the single-photon avalanche diode needs to enter the working state, the FPGA outputs the square wave signals with high and low levels in the working time period, the square wave signals are output as sine signals through the sine signal generation module, and the gate control module sends sine gate control signals to the single-photon detector according to the sine signals, so that the dead time control device for controlling the single-photon detector to enter the dead time state through the sine signals is realized.

Description

Dead time control device of high-speed sine-gate single photon detector

Technical Field

The application relates to the technical field of quantum communication equipment, in particular to a dead time control device of a high-speed sine gate single-photon detector.

Background

Key performance parameters of single photon detectors (i.e., single photon avalanche diodes, APDs) include detection efficiency, back-pulsing, etc. The back pulse refers to that after a single photon avalanche diode passes through one avalanche, under the condition that no photons are incident, the avalanche has a certain probability to trigger another avalanche to generate one avalanche count. The back pulse is an important factor limiting the operating rate of single photon detectors. An effective method of reducing the back pulse is to turn off the gate signal after the single photon avalanche diode detects a photon and produces an effective count to cause the voltage across the single photon avalanche diode to drop below the avalanche voltage, thereby inhibiting subsequent avalanches that may be triggered by the avalanche process. The gate signal off time is referred to as the dead time during which a photon incident on a single photon avalanche diode will not produce a count.

The existing sine gate single photon detector dead time control device is shown in figure 1 and comprises a phase-locked loop, a gate signal generation module, a single photon avalanche diode, an avalanche signal screening module, a signal extraction module and an FPGA which are sequentially and electrically connected, wherein the phase-locked loop is used for frequency doubling a 100kHz clock signal to form a square wave signal, the gate control signal generation module is used for filtering and amplifying the square wave signal to form a sine gate control signal, the single photon avalanche diode detects a received optical signal according to the sine gate control signal, and a detection result is input to the FPGA through the avalanche signal screening module and the signal extraction module.

However, in the existing sine gate single photon detector dead time control device, because a clock signal is continuous, an obtained sine gate control signal is also a continuous sine signal, a single photon avalanche diode is always in a working state and does not enter a dead time state, the single photon avalanche diode can still generate dark count and rear pulse, the existing device processes a signal sent by a signal extraction module by controlling an FPGA according to the frequency of an optical signal, namely the FPGA receives the signal sent by the signal extraction module and processes the signal to obtain a count value, then the FPGA does not count the count value when receiving the signal sent by the signal extraction module within a certain time, then processes the signal sent by the signal extraction module again to obtain the count value, and so on. Therefore, in the prior art, the effect of the single photon avalanche diode entering dead time is achieved by controlling the FPGA to process the signal to filter out dark counts and rear pulses, and therefore a sinusoidal gate single photon detector dead time control device capable of enabling the single photon detector to enter the dead time is urgently needed.

SUMMERY OF THE UTILITY MODEL

In order to overcome the above defects of the prior art, the utility model aims to solve the technical problem that a high-speed sine gate single photon detector dead time controlling means is provided to do not make the single photon detector get into the problem of the sine gate single photon detector dead time controlling means of dead time among the solution prior art.

The embodiment of the utility model provides a concrete technical scheme is:

a high-speed sine gate single photon detector dead time control device comprises an FPGA, a sine signal generation module, a gate control module, a single photon avalanche diode, an avalanche discrimination module and a signal extraction module which are sequentially and electrically connected;

the FPGA is electrically connected with the input end of the sine signal generating module by adopting a high-speed communication interface, and the output end of the signal extracting module is electrically connected with the FPGA.

Preferably, the high-speed communication interface of the FPGA is a GTx interface.

Preferably, the sinusoidal signal generating module is a filter.

Preferably, the gate comprises a first amplifier, an attenuator and a second amplifier which are connected in sequence, wherein an input end of the first amplifier is connected with an output end of the filter, and an output end of the second amplifier is connected with an input end of the single photon avalanche diode.

Preferably, the high-speed single photon detection dead time control device further comprises a phase-locked loop, and the phase-locked loop is used for outputting a clock signal.

According to the scheme, the dead time control device of the high-speed sine gate single-photon detector has the following advantages compared with the prior art:

when the high-speed sine gate single-photon detector dead time control device works, the FPGA outputs a square wave signal for controlling dead time according to a clock signal and a counting narrow pulse signal, namely when a single-photon avalanche diode needs to enter a dead time state, the FPGA does not output the square wave signal in the dead time period, if the single-photon avalanche diode enters a working state, the FPGA outputs the square wave signal with high and low levels in the working time period, the square wave signal is output as a sine signal through a sine signal generation module, and the gating module sends a sine gating signal to the single-photon detector according to the sine signal, so that the dead time control device for controlling the single-photon detector to enter the dead time state through the sine signal is realized. In addition, the square wave signal is output through the high-speed communication interface of the FPGA, and the speed of the high-speed communication interface of the FPGA can reach several GHz, so that the high-speed dead time control of the APD can be realized.

Drawings

The drawings described herein are for illustration purposes only and are not intended to limit the scope of the present disclosure in any way. In addition, the shapes, the proportional sizes, and the like of the respective members in the drawings are merely schematic for helping the understanding of the present invention, and do not specifically limit the shapes, the proportional sizes, and the like of the respective members of the present invention. The skilled person in the art can, under the teaching of the present invention, choose various possible shapes and proportional dimensions to implement the invention according to the specific situation.

FIG. 1 is a schematic structural diagram of a high-speed single photon detection dead time control device in the prior art;

FIG. 2 is a schematic structural diagram of a high-speed single photon detection dead time control apparatus according to the present application;

fig. 3 is a schematic structural diagram of another high-speed single photon detection dead time control device according to the present application.

Detailed Description

The details of the present invention can be more clearly understood with reference to the accompanying drawings and the description of the embodiments of the present invention. However, the specific embodiments of the present invention described herein are for the purpose of explanation only, and should not be construed as limiting the invention in any way. Given the teachings of the present invention, the skilled person can conceive of any possible variants based on the invention, which should all be considered as belonging to the scope of the invention. It will be understood that when an element is referred to as being "disposed on" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present. The terms "mounted," "connected," and "connected" are to be construed broadly and may include, for example, mechanical or electrical connections, communications between two elements, direct connections, indirect connections through intermediaries, and the like. The terms "vertical," "horizontal," "upper," "lower," "left," "right," and the like as used herein are for illustrative purposes only and do not denote a unique embodiment.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

The application provides a high-speed sine gate single photon detector dead time control device, which has a specific structure shown in a schematic diagram shown in FIG. 2 and comprises an FPGA, a sine signal generation module, a gate control module, a single photon avalanche diode, an avalanche discrimination module and a signal extraction module which are electrically connected in sequence; the output end of the signal extraction module is electrically connected with the FPGA and used for generating a counting narrow pulse signal according to the narrow pulse digital signal output by the avalanche discrimination module and transmitting the counting narrow pulse signal to the FPGA; the FPGA is used for outputting square wave signals according to clock signals and counting narrow pulse signals, the FPGA is electrically connected with the input end of the sine signal generating module through a high-speed communication interface, and the sine signal generating module is used for generating sine signals according to the square wave signals. When the single-photon detector works, the FPGA outputs a square wave signal according to a clock signal and a counting narrow pulse signal, a sine signal generation module filters a high-frequency part in a digital signal in a low-pass filtering mode to obtain a sine signal, and a gating module sends a sine gating signal to the single-photon detector through the sine signal. The square wave signal is preferably a signal with a 2.56bps code rate with a duty ratio of 40% -60%, and the sine signal generation module directly filters the high frequency part of the square wave signal in a low-pass filtering manner to generate a 1.25GHz sine signal. Specifically, after receiving the effective counting narrow pulse signal, the FPGA stops sending the high-speed communication interface driving signal, that is, when the APD needs to enter the dead time state, the FPGA does not output the square wave signal in the dead time period, so that the gate control module does not output the sinusoidal gate control signal in the dead time period, thereby enabling the APD to enter the dead time state. If the FPGA does not receive the effective counting narrow pulse signal, a high-speed communication interface driving signal is sent, namely the FPGA sends a square wave signal, so that the gate control module outputs a sine gate control signal in the time period, the APD enters a working state, and the dead time control device for controlling the single-photon detector to enter a dead time state through the sine signal is realized. In addition, the square wave signal is output through the high-speed communication interface of the FPGA, and the speed of the high-speed communication interface of the FPGA can reach several GHz, so that the high-speed dead time control of the APD can be realized.

And the high-speed communication interface of the FPGA is a GTx interface. The FPGA basically integrates some high-speed serial interfaces, which are collectively referred to as Gigabit drivers (GTx), and the transmission rate thereof is at least several GHz level, the commonly used high-speed serial interfaces include GTP, GTR, GTx, GTH, GTZ, GTY, GTM (transmission rate is increasing), and the like, and the GTx Transceiver transmits data by using differential signals, wherein lvds (low Voltage differential signal) and cml (current Mode logic) are two commonly used differential signal standards.

Preferably, the sinusoidal signal generating module is a filter; the filter is used for filtering a square wave Signal output by the FPGA high-speed communication interface, the filter is a frequency selection device, and can enable a wave with a specific frequency in the Signal to pass through, and greatly attenuate waves with other frequencies, so that the filter converts the Signal into a time function of voltage or current under the action of various sensors, namely a time waveform of various physical quantities or a Signal, and since the independent variable time is continuously taken, the time function is called a continuous time Signal, and is also conventionally called an Analog Signal (Analog Signal).

The gate control comprises a first amplifier, an attenuator and a second amplifier which are connected in sequence, wherein the input end of the first amplifier is connected with the output end of the filter, and the output end of the second amplifier is connected with the input end of the single photon avalanche diode. The first amplifier and the second amplifier both adopt operational amplifiers, and the operational amplifier (for short, operational amplifier) is a circuit unit with high amplification factor, and is an amplifier with a special coupling circuit and feedback. The operational amplifier is an electronic integrated circuit containing a multi-stage amplifying circuit, the input stage of the operational amplifier is a differential amplifying circuit, and the operational amplifier has high input resistance and zero drift suppression capability; the intermediate stage mainly performs voltage amplification, has high voltage amplification factor and is generally composed of a common emitter amplification circuit; the output pole is connected with the load, and has the characteristics of strong loading capacity and low output resistance.

The high-speed single photon detection dead time control device further comprises a phase-locked loop, and the phase-locked loop is used for outputting a clock signal. The phase-locked loop adopts an AD9520 phase-locked loop, and the frequency multiplication output frequency of a 100KHz clock signal is 1.25 GHz. Therefore, the FPGA can output square wave signals quickly and accurately according to the counting narrow pulse signals, namely dead time control is carried out on the APD accurately and quickly.

The present application has been described in detail with reference to specific embodiments and illustrative examples, but the description is not intended to limit the application. Those skilled in the art will appreciate that various equivalent substitutions, modifications or improvements may be made to the presently disclosed embodiments and implementations thereof without departing from the spirit and scope of the present disclosure, and these fall within the scope of the present disclosure. The protection scope of this application is subject to the appended claims.

Claims

1. A high-speed sine gate single photon detector dead time control device is characterized by comprising an FPGA, a sine signal generation module, a gate control module, a single photon avalanche diode, an avalanche discrimination module and a signal extraction module which are sequentially and electrically connected;

2. The high-speed sine-gate single photon detector dead time control device according to claim 1, wherein the high-speed communication interface of the FPGA is a GTx interface.

3. The high-speed sinusoidal gate single photon detector dead time control device according to claim 1 or 2, wherein the sinusoidal signal generating module is a filter.

4. The high-speed sinusoidal gate single photon detector dead time control device according to claim 3, wherein said gate control comprises a first amplifier, an attenuator and a second amplifier connected in sequence, an input of said first amplifier being connected to an output of said filter, an output of said second amplifier being connected to an input of said single photon avalanche diode.