CN213041950U - Configurable I-V characteristic testing device for semiconductor device - Google Patents
Configurable I-V characteristic testing device for semiconductor device Download PDFInfo
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- CN213041950U CN213041950U CN202021568979.XU CN202021568979U CN213041950U CN 213041950 U CN213041950 U CN 213041950U CN 202021568979 U CN202021568979 U CN 202021568979U CN 213041950 U CN213041950 U CN 213041950U
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Abstract
The utility model provides a configurable I-V characteristic testing device for semiconductor devices, which consists of a PCB substrate, a power supply port, a suspension port, a grounding port, a first clamp, a second clamp, a single-pole three-throw switch group and a single-pole double-throw switch group; the power port, the suspension port and the grounding port are led out through the PCB substrate, the power port is connected with a power end of the graphic instrument, and the grounding port is connected with a grounding end of the graphic instrument; the first clamp and the second clamp are used for installing a failed device and a normal device respectively. The utility model adopts a universal dual in-line clamp, which can simply realize the I-V characteristic test of the dual in-line packaged semiconductor device and also can test the I-V characteristic of the packaged semiconductor device in other forms which can be converted into dual in-line; a pin required to be subjected to I-V characteristic test is selected through the single-pole three-throw switch, and quick comparison of I-V characteristic curves of a failed device and a normal device is realized through the double-throw switch group.
Description
Technical Field
The utility model relates to a semiconductor test analysis technical field, in particular to configurable semiconductor device I-V characteristic test device.
Background
The failure positioning refers to a series of positioning tests and mechanism analysis aiming at the semiconductor device so as to determine the failure defects of the device. The common failure positioning method is to determine the pins with abnormal electrical characteristics through an I-V characteristic test among the pins, and then to energize the pins with abnormal electrical characteristics to excite the failure characteristics: firstly, testing I-V characteristics between pins of a failure device and normal devices by using a graphic instrument or a semiconductor parameter tester, and comparing the I-V characteristic difference between the pins of the failure device and the normal devices to determine abnormal pins; then, by methods such as an micro-optical microscope (EMMI) and a light beam induced resistance change (OBIRCH), power is applied between abnormal pins of the failed device and the normal device, and a chip image with a bright point is obtained; comparing the chip images of the failed device and the normal device, wherein the chip images of the failed device have bright spots, but the chip images of the normal device do not have the positions of the bright spots, which are often the positions with failure defects. Therefore, in the semiconductor device failure positioning method, the inter-pin IV characteristic test is a precondition.
However, there are two problems in using conventional inter-pin IV characterization tests: 1) because the graphic instrument and other semiconductor parameter testers only have two test ports, when the IV characteristic test is carried out on a multi-pin device, the two test ports are required to be connected to each pin of the device one by one, and the test efficiency is very low; 2) if I-V characteristics among all pins are to be tested, each pin needs to be connected more than once, so that the pins are easy to wear or deform; 3) when I-V characteristic test between pins of a failure device is completed and I-V characteristic test between pins of a normal device is performed, I-V curves between pins corresponding to the two devices cannot form visual comparison due to long interval time, and are recorded one by one only in a mode of photographing or drawing, so that the test efficiency is further reduced, and the most visual comparison cannot be performed. Therefore, an apparatus for performing an I-V characteristic test of a semiconductor device conveniently, rapidly and intuitively is required, but there is no related patent for achieving the above effects at present.
SUMMERY OF THE UTILITY MODEL
An object of the utility model is to provide a configurable semiconductor device I-V characteristic test device can realize semiconductor device I-V characteristic test simply, high-efficiently, accomplishes inefficacy pin location more effectively.
In order to realize the technical effect, the utility model discloses a technical scheme is: the configurable I-V characteristic testing device for the semiconductor device is provided, and comprises a PCB substrate, a power supply port, a suspension port, a grounding port, a first clamp, a second clamp, a single-pole three-throw switch group and a single-pole double-throw switch group;
the power port, the suspension port and the grounding port are led out through the PCB substrate, the power port is connected with a power end of the graphic instrument, and the grounding port is connected with a grounding end of the graphic instrument; the first clamp and the second clamp are fixed on the PCB substrate and are respectively used for mounting a failure device and a normal device;
each 2 single-pole three-throw switches are single-pole three-throw switch units, and the single-pole three-throw switch group comprises n single-pole three-throw switch units; each 2 single-pole double-throw switches are single-pole double-throw switch units, and the single-pole double-throw switch group comprises n single-pole double-throw switch units; 1 three-terminal wire is led out from each of the power supply port, the suspension port and the grounding port to form a three-terminal wire unit, and 2n groups of three-terminal wire units are formed in total;
the single-pole-three-throw switch unit, the single-pole-two-throw switch unit and the corresponding 2 groups of three-terminal line units form a pin measurement unit which is used for measuring the I-V characteristics between a group of pins corresponding to the failed device and the normal device; a group of pin leading-out wires of the failure device or the normal device are respectively connected with a first single-pole double-throw switch and a second single-pole double-throw switch in the single-pole double-throw switch unit; the first single-pole double-throw switch and the second single-pole double-throw switch are connected with a first single-pole three-throw switch and a second single-pole three-throw switch in the single-pole three-throw switch unit through microstrip lines on a PCB substrate; the first single-pole three-throw switch and the second single-pole three-throw switch respectively correspond to 2 groups of three-end lines;
the switching between a failure device and a normal device can be realized by switching the position of a single-pole double-throw switch in the pin measurement unit; the switching of the power port and the grounding port can be realized by switching the position of the single-pole three-throw switch.
Furthermore, the first clamp and the second clamp are identical in structure and size, and a failure device and a normal device are installed through the switching rod.
Further, 24 pin measurement units are arranged.
Furthermore, the PCB substrate adopts a double-layer structure, and microstrip lines with the same attribute adopt the same wiring mode for wiring so as to ensure the consistency of signal delay.
Furthermore, the power supply port and the grounding port are connected with the graphic instrument in a jack mode.
Furthermore, the microstrip line adopts a trace line with the width of 20-24 mil.
The utility model provides a configurable semiconductor device I-V characteristic test device gains's beneficial effect is:
(1) by using the universal dual in-line clamp, I-V characteristic test of the semiconductor device packaged by dual in-line and other packaged semiconductor devices capable of being converted into dual in-line can be realized relatively simply.
(2) The pins needing I-V characteristic test are quickly switched through the single-pole three-throw switch, and the quick comparison of I-V characteristic curves of a failure device and a normal device is realized through the double-throw switch group.
Drawings
The utility model is further explained with the following drawings:
FIG. 1 is a schematic diagram of a configurable I-V characteristic testing apparatus for semiconductor devices;
FIG. 2 is a schematic diagram of a fixture configuration in a configurable semiconductor device I-V characteristic testing apparatus;
FIG. 3 is a schematic cross-sectional view of a fixture in an I-V characteristic testing apparatus for configurable semiconductor devices;
in the figure: the circuit comprises a 1-PCB substrate, a 2-power port, a 3-floating port, a 4-grounding port, a 5-single-pole triple-throw switch I, a 6-single-pole triple-throw switch II, a 7-single-pole triple-throw switch III, an 8-single-pole triple-throw switch IV, a 9-single-pole triple-throw switch V, a 10-single-pole triple-throw switch VI, an 11-double-throw switch group, a 12-clamp I, a 13-clamp II and a 14-switching rod.
Detailed Description
The present invention provides a configurable I-V characteristic testing apparatus for semiconductor devices, which is described in detail below with reference to the accompanying drawings and embodiments. The advantages and features of the present invention will become more fully apparent from the following description and appended claims. It is to be noted that the drawings are in a very simplified form and are not to be construed as precise ratios as are merely intended to facilitate and distinctly illustrate the embodiments of the present invention.
Referring to fig. 1 to 3, in the configurable I-V characteristic testing apparatus for a semiconductor device provided in the present invention, a power port 2, a suspension port 3, and a ground port 4 can be led out from a PCB substrate 1 through jacks, wherein the power port 2 and the ground port 4 are respectively connected to a power end and a ground end of a graphic instrument, 1 set of three-terminal wires are led out from the power port 2, the suspension port 3, and the ground port 4 on the PCB substrate 1, 48 sets of three-terminal wires are led out and switched with 48 single-pole three-throw switches through microstrip lines, taking 6 sets of three-terminal wires as an example, the two sets of three-terminal wires are respectively led out through a single-pole three-throw switch one 5, a single-pole three-throw switch two 6, a single-pole three-throw switch three 7, a single-pole three-throw switch four 8, a single-pole three-throw switch five 9, and a single-pole three-throw switch six 10 and connected to a double-throw switch group 11, the double-throw switch, and corresponding pins of the second clamp 13 are switched, and the double-throw switch group 11 and the other 7 double-throw switch groups comprise 48 double-throw switches in total so as to realize the connection of all 48 single-pole three-throw switches with all 48 pins of the first clamp 12 and the second clamp 13.
In the configurable I-V characteristic testing device for the semiconductor device, the first clamp 12 and the second clamp 13 are used for installing the semiconductor device through the switching rod 14, the structure and the size are the same, the device with the standard dual in-line package of at most 48 pins is supported and installed, most of the dual in-line semiconductor devices can be covered, and the dual in-line structure formed by converting other types of packages is supported.
In the configurable semiconductor device I-V characteristic testing device, the double-throw switch group 11 and the other 7 double-throw switch groups can realize that 6 lines are switched simultaneously through 1 switch.
In the configurable I-V characteristic testing device for the semiconductor device, the PCB substrate 1 adopts a double-layer structure, and microstrip lines with the same attribute adopt the same wiring mode for wiring so as to ensure the consistency of signal delay.
In the configurable I-V characteristic testing device for the semiconductor device, a power supply port 2 and a ground port 4 are connected with a power supply end and a ground end of a graphic instrument in a jack mode.
In the configurable I-V characteristic testing device for the semiconductor device, the microstrip line adopts a routing line with the width of 20-24 mil.
The utility model relates to a test method of configurable semiconductor device I-V characteristic testing arrangement as follows:
1) 48 single-pole three-throw switches including a single-pole three-throw switch I5, a single-pole three-throw switch II 6, a single-pole three-throw switch III 7, a single-pole three-throw switch IV 8, a single-pole three-throw switch V9 and a single-pole three-throw switch VI 10 on the PCB substrate 1 are switched to the suspension port 3.
2) The double-throw switch group 11 and the other 7 double-throw switch groups on the PCB substrate 1 are switched to the first clamp 12.
3) The switching lever 14 is opened, the failure device is mounted on the first clamp 12, the normal device is mounted on the second clamp 13, and the switching lever 14 is closed.
4) The power supply end and the grounding end of the graphic instrument are respectively connected with the power supply port 2 and the grounding port 4 on the PCB substrate 1 through jacks, and the suspended port 3 is not connected.
5) The graphic instrument is turned on and the output voltage and current limit are set based on the electrical characteristics between the pins of the device being tested.
6) And switching the single-pole three-throw switch I5 to the power port 2 and switching the single-pole three-throw switch II 6 to the ground port 4 to realize the I-V characteristic test between corresponding pins.
7) The I-V characteristic of the failed device was recorded.
8) The double-throw switch group 11 and other 7 double-throw switch groups on the PCB substrate 1 are switched to the second clamp 13.
9) The I-V characteristic of a normal device was recorded and compared to a failed device.
10) The single-pole three-throw switch I5 and the single-pole three-throw switch II 6 are switched to the suspension port 3, and the double-throw switch group 11 and the other 7 double-throw switch groups on the PCB substrate 1 are switched to the clamp I12.
11) And repeating the step 6 to the step 10 until I-V characteristic comparison between all pins of the failed device and all pins of the normal device is completed, and finishing the I-V characteristic test.
It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (6)
1. The configurable I-V characteristic testing device of the semiconductor device is characterized by comprising a PCB substrate, a power supply port, a suspension port, a grounding port, a first clamp, a second clamp, a single-pole three-throw switch group and a single-pole double-throw switch group;
the power port, the suspension port and the grounding port are led out through the PCB substrate, the power port is connected with a power end of the graphic instrument, and the grounding port is connected with a grounding end of the graphic instrument; the first clamp and the second clamp are fixed on the PCB substrate and are respectively used for mounting a failure device and a normal device;
each 2 single-pole three-throw switches are single-pole three-throw switch units, and the single-pole three-throw switch group comprises n single-pole three-throw switch units; each 2 single-pole double-throw switches are single-pole double-throw switch units, and the single-pole double-throw switch group comprises n single-pole double-throw switch units; 1 three-terminal wire is led out from each of the power supply port, the suspension port and the grounding port to form a three-terminal wire unit, and 2n groups of three-terminal wire units are formed in total;
the single-pole-three-throw switch unit, the single-pole-two-throw switch unit and the corresponding 2 groups of three-terminal line units form a pin measurement unit which is used for measuring the I-V characteristics between a group of pins corresponding to the failed device and the normal device; a group of pin leading-out wires of the failure device or the normal device are respectively connected with a first single-pole double-throw switch and a second single-pole double-throw switch in the single-pole double-throw switch unit; the first single-pole double-throw switch and the second single-pole double-throw switch are connected with a first single-pole three-throw switch and a second single-pole three-throw switch in the single-pole three-throw switch unit through microstrip lines on a PCB substrate; the first single-pole three-throw switch and the second single-pole three-throw switch respectively correspond to 2 groups of three-end lines;
the switching between a failure device and a normal device can be realized by switching the position of a single-pole double-throw switch in the pin measurement unit; the switching of the power port and the grounding port can be realized by switching the position of the single-pole three-throw switch.
2. The configurable I-V characteristic test apparatus of a semiconductor device as claimed in claim 1, wherein the first and second clamps are identical in structure and size, and a failed device and a normal device are mounted through a switch bar.
3. The configurable I-V characteristic test apparatus of a semiconductor device as claimed in claim 2, wherein the pin measurement units are provided in 24 number.
4. The I-V characteristic testing device of claim 1, wherein the PCB substrate adopts a double-layer structure, and microstrip lines with the same attribute adopt the same routing mode for wiring so as to ensure the consistency of signal delay.
5. The configurable semiconductor device I-V characteristic testing apparatus of claim 4, wherein the power port and the ground port are connected to the graphic instrument by means of jacks.
6. The I-V characteristic testing apparatus of claim 3, wherein the microstrip line is a 20-24mil wide trace.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202021568979.XU CN213041950U (en) | 2020-08-02 | 2020-08-02 | Configurable I-V characteristic testing device for semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202021568979.XU CN213041950U (en) | 2020-08-02 | 2020-08-02 | Configurable I-V characteristic testing device for semiconductor device |
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| Publication Number | Publication Date |
|---|---|
| CN213041950U true CN213041950U (en) | 2021-04-23 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202021568979.XU Active CN213041950U (en) | 2020-08-02 | 2020-08-02 | Configurable I-V characteristic testing device for semiconductor device |
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| CN (1) | CN213041950U (en) |
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- 2020-08-02 CN CN202021568979.XU patent/CN213041950U/en active Active
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