CN212991088U - Packaging structure of passive component and chip comprising same - Google Patents

Packaging structure of passive component and chip comprising same Download PDF

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Publication number
CN212991088U
CN212991088U CN202022151358.8U CN202022151358U CN212991088U CN 212991088 U CN212991088 U CN 212991088U CN 202022151358 U CN202022151358 U CN 202022151358U CN 212991088 U CN212991088 U CN 212991088U
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China
Prior art keywords
chip
frame
passive component
package structure
packaging structure
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CN202022151358.8U
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Chinese (zh)
Inventor
王斌
罗阳
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Allwinner Technology Co Ltd
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Allwinner Technology Co Ltd
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Priority to CN202022151358.8U priority Critical patent/CN212991088U/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

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  • Lead Frames For Integrated Circuits (AREA)

Abstract

The utility model belongs to the semiconductor field discloses a packaging structure of passive components and parts and chip including this packaging structure, include, have the frame of frame pin and frame carrier, be the stacked structure and set up in the first chip and the second chip on frame carrier surface, passive components and parts one end sets up on the frame pin, and the other end sets up on the frame carrier, and wherein, a plurality of frame pins of the power stitch that corresponds first chip merge or form even muscle. The utility model discloses following beneficial effect has at least: the electrical property of the chip under the higher frequency work can be improved, the frame package is enabled to be equivalent to the substrate package under the advantage of low cost, and the competitiveness of the product is improved.

Description

Packaging structure of passive component and chip comprising same
Technical Field
The utility model relates to a semiconductor field, in particular to packaging structure of passive components and parts.
Background
With the development of consumer electronic products, the chip cost performance of the consumer electronic products is gradually improved and valued by chip design companies; for consumption chips such as intelligent hardware, network cameras and the like, the number of functional pins is generally between 80 and 130, and two types of packages such as substrates and frames can meet requirements. Because the electrical performance of the substrate type package is generally superior to that of the frame type package, the substrate type package is generally adopted in the current market. If the electrical performance of the frame-type package can be improved to be equivalent to that of the substrate-type package, the frame-type package with lower packaging cost will take more advantages.
The electrical property of the chip is mainly started from improving the frequency of a CPU or a DRAM, and the inventor finds that two methods can solve the problem of unstable electrical property caused by improving the frequency of the CPU or the DRAM, one method is to increase the number of routing wires to reduce inductive coupling, but the advantages of the method are not obvious; the other is to increase the CPU frequency by adding the capacitor filter, and how to place the capacitor or other components and better utilize the frame structure becomes a determining factor which can directly determine whether the electrical property is stable after the chip is packaged.
SUMMERY OF THE UTILITY MODEL
The utility model discloses aim at solving one of the technical problem that exists among the prior art at least. Therefore, the utility model provides a passive components and parts's packaging structure can improve the chip electrical property under higher frequency work, makes frame encapsulation electrical property match with base plate class encapsulation, has improved the competitiveness of product.
The utility model discloses still provide a chip of packaging structure who has above-mentioned passive components and parts.
According to the utility model discloses a packaging structure of passive components and parts of first aspect embodiment, include: a frame 100 comprising frame leads 101 and a frame carrier 102; a first chip 400 and a second chip 500 disposed on the surface of the frame carrier 102 in a stacked structure, wherein signal contacts of the first chip 400 and signal contacts of the second chip 500 are connected to frame leads 101 through metal wires 300; one end of the passive component 200 is arranged on the frame pin 101, and the other end of the passive component 200 is arranged on the frame carrier 102; the plurality of frame pins 101 corresponding to the power pins of the first chip 400 are combined or formed into a connecting rib.
According to some embodiments of the present invention, the package structure further comprises a plastic package body 600 for encapsulating and protecting the frame 100, the metal wire 300, the first chip 400, the second chip 500 and the passive component 200.
According to some embodiments of the present invention, the plastic package body 600 is a resin-based polymer.
According to some embodiments of the present invention, 4 or 5 frame pins 101 are combined into one pin or form the connecting rib.
According to some embodiments of the present invention, the first chip 400 is an SoC chip, and the second chip 500 is a memory chip.
According to some embodiments of the present invention, the metal wire 300 is a silver alloy wire or a palladium copper wire.
According to some embodiments of the present invention, the passive component 200 is a surface mount component.
According to some embodiments of the present invention, the passive component 200 includes a resistor, a capacitor, an inductor, or a crystal oscillator.
According to some embodiments of the invention, the resistance is 0201 resistance, and the electric capacity is 0201 electric capacity.
According to a second aspect of the present invention, a chip includes any one of the above-mentioned passive components and parts.
According to the utility model discloses a packaging structure of passive components and parts has following beneficial effect at least: the electrical property of the chip under the higher frequency work can be improved, the frame package is enabled to be equivalent to the substrate package under the advantage of low cost, and the competitiveness of the product is improved.
Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.
Drawings
The above and/or additional aspects and advantages of the present invention will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:
fig. 1 is a schematic top view of a partial structure according to an embodiment of the present invention;
fig. 2 is a schematic structural cross-sectional view of an embodiment of the present invention.
Detailed Description
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the drawings are exemplary only for the purpose of explaining the present invention, and should not be construed as limiting the present invention.
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the embodiments described herein are merely illustrative and not restrictive, and therefore do not represent any changes in the technical spirit, structure, proportion, or size which may occur or which may not affect the performance or objectives achieved thereby, and are intended to be covered by the teachings herein.
Reference will now be made in detail to the present embodiments of the present application, preferred embodiments of which are illustrated in the accompanying drawings, which are for the purpose of visually supplementing the description with figures and detailed description, so as to enable a person skilled in the art to visually and visually understand each and every feature and technical solution of the present application, but not to limit the scope of the present application.
In the description of the application, the meaning of a plurality is one or more, the meaning of a plurality is two or more, and larger, smaller, larger, etc. are understood as excluding the present number, and larger, smaller, inner, etc. are understood as including the present number. If the first and second are described for the purpose of distinguishing technical features, they are not to be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated or implicitly indicating the precedence of the technical features indicated.
In order to facilitate understanding of an embedded structure provided in an embodiment of the present application, a specific structure thereof will be described below with reference to the accompanying drawings.
Referring to fig. 1 and fig. 2, wherein fig. 1 shows a schematic structural plan view of an embodiment of the present invention, and fig. 2 shows a schematic structural cross-sectional view of an embodiment of the present invention. As can be seen from fig. 1 and 2, a package structure of a passive component includes a frame 100, which includes frame leads 101 and a frame carrier 102; a first chip 400 and a second chip 500 disposed on the surface of the frame carrier 102 in a stacked structure, wherein signal contacts of the first chip 400 and signal contacts of the second chip 500 are connected to the frame leads 101 through metal wires 300; one end of the passive component 200 is arranged on the frame pin 101, and the other end of the passive component 200 is arranged on the frame carrier 102; in which a plurality of frame pins 101 corresponding to the power pins of the first chip 400 are combined into one pin or formed into a connecting rib. It should be noted that, the package structure of this embodiment adopts a conventional customized frame, and subsequent products can still be used, and through a normal package technology, when the electrical performance of the product is improved, compared with the substrate package, the heat dissipation performance of the chip is increased, and the package cost can be reduced, thereby increasing the competitiveness of the product. By arranging the passive component 200 between the frame pins and the frame carrier, the electrical performance of the chip under higher frequency operation is improved, the frame package is made to be equivalent to the substrate package under the advantage of low cost, and the competitiveness of the product is improved.
The utility model discloses an among some embodiments, still including plastic-sealed body 600, plastic-sealed body 600 is used for encapsulating frame 100, metal wire 300, first chip 400, second chip 500 and passive components and parts 200 and protects, has guaranteed that chip, components and parts and metal connecting wire can not receive environmental impact to have more stable electrical property.
In some embodiments of the present invention, the plastic package body 600 is a resin polymer.
The utility model discloses an in the middle of some embodiments, can merge into a pin or form even muscle by 4 or 5 frame pins 101, it is to explain that, in the middle of some concrete embodiments, can adopt the frame pin that a plurality of CPU power correspond to merge together, will be passive components and parts and place between CPU power pin and EPAD, neither influence the normal pin number of frame like this, also influence the normal volume production routing of chip yet.
The utility model discloses an among some embodiments, first chip 400 is the SoC chip, and second chip 500 is the storage chip, and is further, when adopting the SoC chip as one of them encapsulation chip, passive components and parts adopt electric capacity, then can carry out electric capacity filtering, the electrical property of the SoC chip during operation of improvement to the SoC chip.
In some embodiments of the present invention, the metal wire 300 is an Ag alloy wire or a palladium copper wire.
The utility model discloses an among some embodiments, passive components and parts 200 are surface mounting type components and parts, and is further, passive components and parts 200 be resistance, electric capacity, inductance or crystal oscillator, and is further, and resistance is 0201 resistance, and electric capacity is 0201 electric capacity, and what need explain is that, need explain, no matter use that kind of passive components and parts, adopt the utility model discloses a packaging structure back, will be passive components and parts set up between frame pin and frame carrier, can both more or less improve the electrical property of chip under the higher frequency work, this is because, passive components and parts can increase to prop big chip area in die and cause the cost to rise, generally do this seldom, and directly increase passive device on PCB, its effect will be poor than increasing passive device in the packaging body.
In some embodiments, the passive component 200 may also be placed between the bonding contact and the bonding Pin of the SoC chip 400, and the bonding wire crosses the passive component 200.
The embodiment of this application still includes a chip, and this chip includes the utility model discloses a passive components and parts's packaging structure should realize, as long as used the utility model provides a passive components and parts's packaging structure, the chip that then uses this structure all is in the utility model discloses a protection scope.
Referring to fig. 2, in a specific embodiment, an SIP packaging process is adopted, a memory chip 500 and an SoC chip 400 are stacked and placed on a frame 100 together, the memory chip 500 is in direct contact with the surface of the frame 100, a solder contact of the SoC chip 400 is connected with a frame pin 101 through a silver alloy wire 300, one end of a capacitor device 200 is placed on a carrier 102 of the frame, the other end of the capacitor device is placed on the frame pin 101, and the whole SIP packaging is used for integrally encapsulating and protecting the SoC chip 400, the memory chip 500, the Ag alloy wire 300 and the capacitor device 200 by using a resin polymer 600.
Specifically, the frame 100 is customized according to the power pins of the actual SoC chip 400, and 4 or 5 pins at the corners of the frame are combined or form connecting ribs.
It should be noted that the utility model discloses a passive components and parts's packaging structure has passed through inventor's product experiment to through the test, this encapsulation reliability experimental result passes through, has further verified this utility model's technical scheme has the feasibility of implementation.
In some embodiments, when the passive component 200 is a resistor or a crystal oscillator, embodiments of the present invention using the same can be applied to RF-level audio products.
Although specific embodiments have been described herein, those of ordinary skill in the art will recognize that many other modifications or alternative embodiments are equally within the scope of this disclosure. For example, any of the functions and/or processing capabilities described in connection with a particular device or component may be performed by any other device or component. In addition, while various illustrative implementations and architectures have been described in accordance with embodiments of the present disclosure, those of ordinary skill in the art will recognize that many other modifications of the illustrative implementations and architectures described herein are also within the scope of the present disclosure.
The embodiments of the present invention have been described in detail with reference to the accompanying drawings, but the present invention is not limited to the above embodiments, and various changes can be made without departing from the spirit of the present invention within the knowledge of those skilled in the art.

Claims (10)

1. A packaging structure of a passive component is characterized by comprising:
a frame (100) comprising a frame lead (101) and a frame carrier (102);
a first chip (400) and a second chip (500) arranged on the surface of the frame carrier (102) in a stacked structure, wherein the signal contact of the first chip (400) and the signal contact of the second chip (500) are connected to the frame pin (101) through a metal wire (300);
one end of the passive component (200) is arranged on the frame pin (101), and the other end of the passive component (200) is arranged on the frame carrier (102);
the frame pins (101) corresponding to the power pins of the first chip (400) are combined or form connecting ribs.
2. The package structure of a passive component according to claim 1, further comprising a molding compound (600) for encapsulating and protecting the frame (100), the metal lines (300), the first chip (400), the second chip (500), and the passive component (200).
3. The package structure of a passive component according to claim 2, wherein the molding compound (600) is a resin polymer.
4. The package structure of a passive component according to claim 1, wherein 4 or 5 frame leads (101) are combined into one lead or form the tie bar.
5. The package structure of a passive component as claimed in claim 1, wherein the first chip (400) is an SoC chip and the second chip (500) is a memory chip.
6. The package structure of a passive component according to claim 1, wherein the metal wire (300) is a silver alloy wire or a palladium copper wire.
7. The package structure of a passive component according to claim 1, wherein the passive component (200) is a surface mount component.
8. The packaging structure of a passive component according to claim 7, characterized in that the passive component (200) comprises a resistor, a capacitor, an inductor or a crystal oscillator.
9. The package structure of a passive component as claimed in claim 8, wherein the resistor is a 0201 resistor, and the capacitor is a 0201 capacitor.
10. A chip comprising a package structure of a passive component according to any of claims 1 to 9.
CN202022151358.8U 2020-09-27 2020-09-27 Packaging structure of passive component and chip comprising same Active CN212991088U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202022151358.8U CN212991088U (en) 2020-09-27 2020-09-27 Packaging structure of passive component and chip comprising same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202022151358.8U CN212991088U (en) 2020-09-27 2020-09-27 Packaging structure of passive component and chip comprising same

Publications (1)

Publication Number Publication Date
CN212991088U true CN212991088U (en) 2021-04-16

Family

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Family Applications (1)

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Country Status (1)

Country Link
CN (1) CN212991088U (en)

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