CN212933504U - Liquid crystal driving system based on FPGA - Google Patents

Abstract

The utility model discloses a liquid crystal driving system based on FPGA, which comprises a chip based on FPGA, wherein the chip based on FPGA comprises a Nios II embedded system, an Avalon bus, a PLL module and an image processing module; the Nios II embedded system comprises a Nios II processor, an SDRAM controller core, a FLASH controller core, an image display VGA module and at least one communication module; the Nios II processor, the SDRAM controller core, the FLASH controller core, the image display VGA module and at least one communication module are electrically connected to the Avalon bus; the PLL module is electrically connected with the SDRAM controller core; the image processing module is electrically connected with the image display VGA module. The system applies the advantages of FPGA parallel processing, has short sending period and simple structure, realizes the optimized image display function, and realizes flexible, efficient, high-speed, flicker-free, stable and high-performance liquid crystal display drive control.

Description

Liquid crystal driving system based on FPGA

Technical Field

The utility model relates to a liquid crystal driving system field especially relates to a liquid crystal driving system based on FPGA.

Background

With the continuous advancement of information, information has become an important part of people's life, and obtaining information through vision is a main means of people. Since the liquid crystal display is widely applied to various industries, the design of a display driving control circuit in the application of the liquid crystal display is a very important link, and the research on a new solution of the liquid crystal driving display control has great significance for realizing the liquid crystal display with short development period, simple structure and easy interaction.

However, the existing liquid crystal display solutions mostly adopt a liquid crystal display module consisting of a liquid crystal display driving liquid crystal driver, a circuit board and a peripheral circuit, and the display control solution has the advantages of mature technology and low cost, but the defects are obvious: the structure is complex, the design is difficult, the development cycle is long, and the interface with some modern new technology products is difficult.

SUMMERY OF THE UTILITY MODEL

The utility model aims at providing a liquid crystal driving system based on FPGA, which can effectively solve the problems of difficult upgrading, complex structure, slow processing speed, low picture display quality and the like existing in the prior traditional liquid crystal display, and compared with a special integrated circuit, the FPGA is more flexible; FPGAs are faster compared to conventional processors.

In order to achieve the above object, the present invention provides a liquid crystal driving system based on FPGA, which comprises a chip based on FPGA, wherein the chip based on FPGA comprises a Nios II embedded system, an Avalon bus, a PLL module and an image processing module; the Nios II embedded system comprises a Nios II processor, an SDRAM controller core, a FLASH controller core, an image display VGA module and at least one communication module; the Nios II processor, the SDRAM controller core, the FLASH controller core, the image display VGA module and the at least one communication module are electrically connected to the Avalon bus; the PLL module is electrically connected with the SDRAM controller core; the image processing module is electrically connected to the image display VGA module.

Further, the at least one communication module comprises a USB core, an SPI core and an RS232 core.

Further, the USB nuclear power is connected with the USB communication circuit, the SPI nuclear power is connected with the SPI communication circuit, and the RS232 nuclear power is connected with the RS232 communication circuit.

Furthermore, the system also comprises a FLASH chip circuit, an SDRAM chip circuit, a VGA chip circuit and an external clock source; the FLASH chip circuit is electrically connected with the FLASH controller core, the SDRAM chip circuit is electrically connected with the SDRAM controller core and the PLL module, the VGA chip circuit is electrically connected with the image processing module and the PLL module, and the external clock source is electrically connected with the PLL module.

Furthermore, the Nios II embedded system also comprises a JTAG debugging module, wherein one end of the JTAG debugging module is electrically connected to the Avalon bus, and the other end of the JTAG debugging module is electrically connected to the JTAG debugging interface circuit.

Furthermore, the Nios II embedded system further comprises a PIO module, wherein one end of the PIO module is electrically connected to the Avalon bus, and the other end of the PIO module is electrically connected to the 4 x 4 key.

Further, the Nios II embedded system is also provided with a system ID.

The embodiment of the utility model provides a beneficial effect that technical scheme brought is: the system has short development period and simple structure; the system needs to be upgraded or added with functions, does not need to change a peripheral hardware circuit, and only needs to use a hardware description language to write a hardware function module to realize the online upgrade of the hardware system; the system applies the advantage of FPGA parallel processing, realizes the optimized image display function and flexible, high-efficiency, high-speed, flicker-free, stable and high-performance liquid crystal display driving control; in addition, the system is provided with a USB (universal serial bus), SPI (serial peripheral interface) and RS232 communication modules, and can also realize a multi-mode communication function.

Drawings

Fig. 1 is a schematic diagram of a liquid crystal driving system based on FPGA of the present invention.

Fig. 2 is a schematic diagram of the present invention regarding an FPGA real-time edge detection system.

Fig. 3 is a schematic diagram of the VGA interface chip driver hardware circuit of the present invention.

Fig. 4 is a flowchart of the present invention relating to VGA module control.

Detailed Description

In order to make the above objects, features and advantages of the present invention more comprehensible, embodiments of the present invention are described in detail below with reference to the accompanying drawings.

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, but the present invention may be implemented in other ways than those specifically described herein, and one skilled in the art may similarly generalize the present invention without departing from the spirit of the present invention, and therefore the present invention is not limited to the specific embodiments disclosed below.

Next, the present invention will be described in detail with reference to the schematic drawings, and in the detailed description of the embodiments of the present invention, for convenience of illustration, the schematic drawings are only examples, and the present invention should not be limited thereto. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.

In order to make the objects, technical solutions and advantages of the present invention clearer, embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.

As shown in fig. 1, the utility model provides a liquid crystal driving system based on FPGA, the system includes chip based on FPGA, the chip based on FPGA includes Nios II embedded system, Avalon bus, PLL module and image processing module; the Nios II embedded system comprises a Nios II processor, an SDRAM controller core, a FLASH controller core, an image display VGA module and at least one communication module; the Nios II processor, the SDRAM controller core, the FLASH controller core, the image display VGA module and at least one communication module are electrically connected to the Avalon bus; the PLL module is electrically connected with the SDRAM controller core; the image processing module is electrically connected with the image display VGA module. The system applies the advantages of FPGA parallel processing, has short sending period and simple structure, realizes the optimized image display function, and realizes flexible, efficient, high-speed, flicker-free, stable and high-performance liquid crystal display drive control.

In a preferred embodiment, at least one communication module comprises a USB core, an SPI core and an RS232 core.

As a preferred embodiment, the USB nuclear power is connected with the USB communication circuit, the SPI nuclear power is connected with the SPI communication circuit, and the RS232 nuclear power is connected with the RS232 communication circuit.

As a preferred embodiment, the system also includes a FLASH chip circuit, an SDRAM chip circuit, a VGA chip circuit, and an external clock source; the FLASH chip circuit is electrically connected with the FLASH controller core, the SDRAM chip circuit is electrically connected with the SDRAM controller core and the PLL module, the VGA chip circuit is electrically connected with the image processing module and the PLL module, and the external clock source is electrically connected with the PLL module.

As a preferred embodiment, the Nios II embedded system further includes a JTAG debug module, one end of which is electrically connected to the Avalon bus, and the other end of which is electrically connected to a JTAG debug interface circuit.

As a preferred embodiment, the Nios II embedded system further includes a PIO module, one end of which is electrically connected to the Avalon bus and the other end of which is electrically connected to the 4 × 4 key.

As a preferred embodiment, the Nios II embedded system is also provided with a system ID.

SDRAM module: the NiosII embedded system in the system provides an Avalon bus for the SDRAM module, and the IP core is integrated into the NiosII embedded system through the Avalon bus. The SDRAM controller is mainly used for storing images, downloaded image data are configured, processed and stored in the SDRAM temporarily, and then the liquid crystal display controller is waited for extracting the image data for display. The off-chip SDRAM in the system is K4S511632B-TL75 of SAMSUNG company, when the system builds a NiosII soft core, C program design is carried out in a NiosII IDE environment, and the SDRAM is mainly a C program running space and carries out high-speed processing on data. The driving clock of the SDRAM chip in the system is set to 75MHZ, and the VGA display requirement is met. In order to independently design, implement and optimize a certain module and constrain the implementation result of the module in a planned FPGA region, the module uses LogicLock to logically lock, so that the implementation result of each module can be better inherited when design integration is carried out.

A FLASH module: the FPGA is a volatile device, and configuration information can be lost after power failure, so that the FPGA configuration realized by using the PC has no memory function, and needs to be reconfigured after the system is powered on every time. The off-chip FLASH chip adopted in the system design is am29LV160DT-120 of AMD company, and has three main functions in the system, wherein one function is to store an FPGA configuration file; secondly, saving the program C, and reading the program C into an SDRAM for rapid processing after the program C is powered on; and thirdly, storing the configuration picture information and supplying the configuration picture information to the VGA for display. The driving clock of the FLASH chip in the system is set to be 75MHZ, so that the VGA display requirement is met. In the same processing scheme, the module uses LogicLock for logical locking.

A PLL module: the PLL phase-locked loop is a frequency divider and the main function of the PLL is to synchronize the internal or external clock and the reference clock input frequency. In the system design, a 50MHz system clock is respectively used for generating 75MHz, 75MHz and 25MHz clock outputs and respectively supplied to a NiosII embedded system, an external SDRAM chip circuit and a VGA display chip circuit. In addition, considering PCB line delay, layout and wiring delay and the like, in order to realize the synchronization of FLASH and SDRAM, the clock phase shift of SDRAM is actually adjusted to-27 deg in the system design.

As shown in fig. 2, the system adopts the Sobel and Roberts operator joint edge detection technology, and the implementation process is as follows: after image information comes, joint detection is carried out by combining the advantages of Sobel and Roberts, so that whether an edge of one image is a noise point is judged, pre-judgment is carried out according to the characteristics of edge continuity and the characteristics of noise point isolation or fragmentation, the image is regarded as the noise point when the image is not continuous, then the noise point is processed by mean optimization, and optimized image display is realized through a VGA liquid crystal display platform. The mean value optimization algorithm is realized by taking the mean value of 8 points in the neighborhood, namely 9 pixel points, through a 3 x 3 template to replace the noise point. The use of Sobel and Roberts in conjunction with the edge detection technique has the following advantages: noise is removed but the edges are not weakened so that the whole image is optimized.

As shown in fig. 3, the VGA module is designed to realize the display control of the lcd, and the lcd module is actually a liquid crystal driving core, and is mainly used to read the image information in the SDRAM memory, and drive the lcd to display the image after the image information is converted into the VGA display format standard by the interface chip circuit. The interface chip of VGA is ADV7125 of ADI corporation in usa, and the LCD display specification is 640 × 480 to achieve the requirements of small size, portability, high performance and the like of the embedded system. The ADV7125 is a high-speed video digital-to-analog conversion chip, three 8-bit digital video signals of three colors, namely red (R7-R0), green (G7-G0) and blue (B7-B0), and three RGB analog output signals. There are five signals for the VGA pinouts, RGB (red green blue three primary color signals), VGA _ HS (line sync signal), VGA _ VS (field sync signal). The hardware circuit of the VGA interface chip, namely the liquid crystal controller module, is realized by the following processes: after the system is powered on, the system starts to operate, and firstly, the FPGA performs hardware configuration, namely a flow shown in the figure. Then SDRAM carries on the software program loading, namely the process, image information and C language program are stored in SDRAM temporarily, then through VGA soft core buffer memory to VGA submodule in high speed FIFO, the image processing module carries on the image optimization processing to the image information, finally through driving ADV7125 chip circuit to convert the digital signal to the analog signal to carry on the image display, in this way, the phenomenon of the flashing, brushing the screen has been avoided effectively.

In the design, the refresh clock frequency of the ADV7125 chip circuit is set to be 25MHz, namely the refresh speed of the LCD screen is about 50MHz, which is also the reason that the PLL module sets a 25MHz distribution output. The refresh rate is sufficient for this design to meet the flicker pattern that is not visible to the naked eye, so there is a divided-by-25 MHZ output of the PLL module.

As shown in fig. 4, the flow of the VGA control core is designed as follows: in the effective time sequence stage, reading the image data in the SDRAM, then buffering in a cache module FIFO in the VGA module, then generating a time sequence control signal required by the module by a time sequence unit, then reading the data in the FIFO, and finally outputting and displaying.

While the invention has been described above with reference to an embodiment, various modifications may be made and equivalents may be substituted for elements thereof without departing from the scope of the invention. In particular, as long as there is no structural conflict, the various features of the disclosed embodiments of the present invention can be used in any combination with each other, and the non-exhaustive description of these combinations in this specification is merely for the sake of brevity and resource conservation. Therefore, it is intended that the invention not be limited to the particular embodiments disclosed, but that the invention will include all embodiments falling within the scope of the appended claims.

Claims (7)

1. The liquid crystal driving system based on the FPGA is characterized by comprising an FPGA-based chip, wherein the FPGA-based chip comprises a Nios II embedded system, an Avalon bus, a PLL module and an image processing module;

the Nios II embedded system comprises a Nios II processor, an SDRAM controller core, a FLASH controller core, an image display VGA module and at least one communication module;

the Nios II processor, the SDRAM controller core, the FLASH controller core, the image display VGA module and the at least one communication module are electrically connected to the Avalon bus;

the PLL module is electrically connected with the SDRAM controller core;

the image processing module is electrically connected to the image display VGA module.

2. The FPGA-based liquid crystal driving system of claim 1, wherein the at least one communication module comprises a USB core, an SPI core and an RS232 core.

3. The FPGA-based liquid crystal driving system of claim 2, wherein the USB core is electrically connected to the USB communication circuit, the SPI core is electrically connected to the SPI communication circuit, and the RS232 core is electrically connected to the RS232 communication circuit.

4. The FPGA-based liquid crystal driving system of claim 1, further comprising a FLASH chip circuit, an SDRAM chip circuit, a VGA chip circuit, and an external clock source;

the FLASH chip circuit is electrically connected with the FLASH controller core, the SDRAM chip circuit is electrically connected with the SDRAM controller core and the PLL module, the VGA chip circuit is electrically connected with the image processing module and the PLL module, and the external clock source is electrically connected with the PLL module.

5. The FPGA-based LCD driving system as recited in claim 1, wherein the Nios II embedded system further comprises a JTAG debug module, one end of the JTAG debug module is electrically connected to the Avalon bus, and the other end of the JTAG debug module is electrically connected to the JTAG debug interface circuit.

6. The FPGA-based LCD driving system as recited in claim 1, wherein the NiosII embedded system further comprises a PIO module electrically connected to the Avalon bus at one end and to a 4 x 4 button at the other end.

7. The FPGA-based LCD driving system as recited in claim 1, wherein the Nios II embedded system is further configured with a system ID.

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