CN212809187U - Automatic test development board of communication module - Google Patents
Automatic test development board of communication module Download PDFInfo
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- CN212809187U CN212809187U CN202021612686.7U CN202021612686U CN212809187U CN 212809187 U CN212809187 U CN 212809187U CN 202021612686 U CN202021612686 U CN 202021612686U CN 212809187 U CN212809187 U CN 212809187U
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Abstract
The utility model provides an automatic test development board of a communication module, which comprises a development board body, a module test seat fixedly arranged on the development board body, an upper computer and a plurality of first data conversion modules; the test socket comprises a communication interface, a plurality of first interfaces to be tested and a plurality of second interfaces to be tested; the upper computer is used for generating a target test instruction and sending the target test instruction to the communication interface; the module test seat is used for sending the data to be tested corresponding to the first interface to be tested to the first data conversion module or sending the data to be tested corresponding to the second interface to be tested to the upper computer; each first data conversion module is used for converting data to be tested into target data and sending the target data to an upper computer; the upper computer is used for detecting the target data and generating a test result. The utility model discloses a host computer sends test instruction for the communication module that awaits measuring on the test development board, realizes carrying out the automated test to communication module, has improved test speed and test productivity, has reduced the test cost.
Description
Technical Field
The utility model relates to a communication module tests the field, in particular to communication module's automatic test development board.
Background
The communication module is a wireless module based on the narrowband Internet of things technology, and has the characteristics of low power consumption, low cost, deep coverage, capability of supporting massive connection and the like.
Most of communication modules in the current market are tested manually, the test module is placed in a tray during testing, all functional modules are connected in a manual lead welding mode, and only when the test result meets the standard of a company, the communication module is delivered to a terminal customer for secondary development; however, the testing method has the disadvantages of slow testing speed, low testing capacity, low equipment integration level, long development period, high production cost, poor stability, difficult maintenance, and incapability of meeting the sudden order requirement and price requirement of a client.
SUMMERY OF THE UTILITY MODEL
The to-be-solved technical problem of the utility model is that there is the defect that test speed is slow, the test productivity is low, manufacturing cost is high in order to overcome the test mode of the manual test communication module among the prior art, provides a communication module's automatic test development board.
The utility model discloses an above-mentioned technical problem is solved through following technical scheme:
the utility model provides an automatic test development board of a communication module, which comprises a development board body, a module test seat, an upper computer and a plurality of first data conversion modules, wherein the module test seat is fixedly arranged on the development board body;
the module test seat comprises a communication interface, a plurality of first interfaces to be tested and a plurality of second interfaces to be tested; the communication interface is electrically connected with the second interface to be tested and the upper computer respectively;
each first data conversion module is electrically connected with the first interface to be tested and the upper computer respectively;
the communication module to be tested is fixedly arranged on the module test seat;
the upper computer is used for generating a target test instruction and sending the target test instruction to the communication interface;
the module test seat is used for sending the data to be tested corresponding to the first interface to be tested to the first data conversion module according to the target test instruction received by the communication interface;
each first data conversion module is used for converting the corresponding data to be tested into target data and sending the target data to the upper computer;
the upper computer is also used for detecting the target data and generating a test result; or the like, or, alternatively,
the module test seat is used for sending the data to be tested corresponding to the second interface to be tested to the upper computer through the communication interface according to the target test instruction received by the communication interface;
the upper computer is also used for detecting the data to be tested and generating a test result.
Preferably, the first data conversion module comprises a first data interface and a second data interface; the upper computer comprises a third data interface;
the interface type of the first data interface is the same as that of the first interface to be tested, and the interface type of the second data interface is the same as that of the third data interface;
the upper computer is used for sending the target test instruction to the communication interface through the third data interface;
the module test socket is used for sending the to-be-tested data corresponding to the first to-be-tested interface to the first data conversion module through the first data interface according to the target test instruction received by the communication interface;
the first data conversion module is used for converting the corresponding data to be tested into the target data and sending the target data to the upper computer through the second data interface;
the upper computer is also used for detecting the target data and generating a test result.
Preferably, the test development board further comprises a second data conversion module fixedly arranged on the development board body;
the second data conversion module comprises a first USB (Universal Serial bus) type interface and a second USB type interface; the upper computer comprises a fourth data interface;
the first USB type interface and the communication interface are the same in interface type, and the second USB type interface and the fourth data interface are the same in interface type;
the upper computer is used for sending the target test instruction to the communication interface through the fourth data interface;
the module test socket is used for sending the data to be tested corresponding to the second interface to be tested to the second data conversion module through the first USB type interface according to the target test instruction received by the communication interface;
the second data conversion module is used for carrying out format conversion processing on the corresponding data to be tested received through the first USB type interface and sending the corresponding data to be tested after the format conversion processing to the upper computer through the second USB type interface;
the upper computer is also used for detecting the data to be tested and generating a test result.
Preferably, the module test socket further comprises a third interface to be tested; the upper computer also comprises a USB2.0 interface;
the USB2.0 interface is electrically connected with the third interface to be tested through a UART (universal asynchronous receiver transmitter) data line;
the upper computer is used for sending the target test instruction to the communication interface through the USB2.0 interface;
the module test seat is used for sending the data to be tested corresponding to the third interface to be tested to the upper computer through the UART data wire according to the target test instruction received by the communication interface;
the upper computer is also used for detecting the data to be tested and generating a test result.
Preferably, the test development board further includes a first power management unit, a second power management unit, a third power management unit and a control module, the first power management unit, the second power management unit, the third power management unit and the control module are fixedly arranged on the development board body, the module test socket further includes a first voltage interface, a second voltage interface and a power interface, and the control module includes a first input/output interface and a third voltage interface;
the input end of the first power management unit, the input end of the second power management unit and the input end of the third power management unit are electrically connected with external power supply equipment, the output end of the first power management unit is electrically connected with the first voltage interface, and the output end of the second power management unit is electrically connected with the second voltage interface;
the output end of the third power management unit is electrically connected with the third voltage interface;
the first input/output interface is electrically connected with the power interface;
the first power management unit and the second power management unit are respectively used for supplying power to the first voltage interface and the second voltage interface of the module test socket;
the third management unit is used for supplying power to the control module;
the control module is used for supplying power to the module test seat.
Preferably, the test development board further comprises a first current limiting resistor and a second current limiting resistor which are fixedly arranged on the development board body, and the module test socket further comprises a first analog-to-digital conversion interface and a second analog-to-digital conversion interface;
one end of the first current limiting resistor is electrically connected with the first analog-to-digital conversion interface, one end of the second current limiting resistor is electrically connected with the second analog-to-digital conversion interface, and the other end of the first current limiting resistor and the other end of the second current limiting resistor are both electrically connected with the output end of the second power management unit.
Preferably, the test development board further includes a first triode, a second triode, a third current-limiting resistor and a fourth current-limiting resistor which are fixedly arranged on the development board body, the control module further includes a second input/output interface, a third input/output interface, a fourth input/output interface and a third analog-to-digital conversion interface, and the module test socket further includes a fifth input/output interface and a reset interface;
a base electrode of the first triode is electrically connected with the third input/output interface, an emitting electrode of the first triode is grounded, a collector electrode of the first triode is electrically connected with one end of the third current limiting resistor, and the other end of the third current limiting resistor is electrically connected with an enabling pin of the first power management unit;
a base electrode of the second triode is electrically connected with the fourth input/output interface, an emitting electrode of the second triode is grounded, a collector electrode of the second triode is electrically connected with one end of the fourth current limiting resistor, and the other end of the fourth current limiting resistor is electrically connected with an enabling pin of the second power management unit;
the second input/output interface is electrically connected with the reset interface;
the third analog-to-digital conversion interface is electrically connected with the fifth input/output interface.
Preferably, the first interface to be tested comprises a pci 2.0/3.0 (bus) interface or an RGMII (gigabit media independent) interface;
the second interface to be tested comprises a UISM (universal user identification card) interface, a digital audio interface, a radio frequency interface, an analog-to-digital conversion interface, an input/output interface or a reset interface;
the first USB type interface comprises a USB2.0/2.1 interface and a USB3.0/3.1 interface;
the second USB type interface and the fourth data interface each comprise a USB3.1 interface.
Preferably, the third data interface includes a solid state disk interface or a network cable interface.
Preferably, the first USB type interface includes a USB2.0/2.1 interface and a USB3.0/3.1 interface;
and/or the third interface to be tested comprises a UART interface.
The utility model discloses an actively advance the effect and lie in:
the utility model discloses a host computer in the test development board sends test instruction for the communication module that awaits measuring on the test development board, realizes carrying out the automated test to communication module, does not need extra design hardware, has improved test speed and test productivity, has reduced the test cost.
Drawings
Fig. 1 is a schematic circuit diagram of an automated testing development board of a communication module according to a preferred embodiment of the present invention.
Detailed Description
The present invention will be more clearly and completely described below by way of embodiments with reference to the accompanying drawings, and the description of the embodiments is provided to help understanding the present invention, but the present invention is not limited thereto.
As shown in fig. 1, this embodiment provides an automatic test development board for a communication module, which includes a development board body, a module test socket 1 fixed on the development board body, an upper computer 2, a plurality of first data conversion modules 3, a second data conversion module 4, a first power management unit 5, a second power management unit 6, a third power management unit 7, a control module 8, a first current limiting resistor R1, a second current limiting resistor R2, a first triode Q1, a second triode Q2, a third current limiting resistor R3, a fourth current limiting resistor R4, a third data conversion module 9, an analog module 10, a fourth data conversion module 11, at least one SIM (subscriber identity card) card socket 12, and an external power supply device 13; wherein, the communication module to be tested is fixedly arranged on the module test seat 1.
In this embodiment, the module test socket 1 includes communication interfaces USB2.0/2.1 and USB3.0/3.1, a plurality of first interfaces to be tested and a plurality of second interfaces to be tested, a third interface to be tested, a first voltage (VBAT _ RF) interface, a second voltage (VBAT _ BB) interface, a power supply (PWRKEY) interface, a first analog-to-digital conversion (ADC1) interface, a second analog-to-digital conversion (ADC2) interface, a fifth input/output (GPIO5) interface, and a RESET (RESET) interface.
The first interface to be tested comprises a PCIe2.0/3.0 interface or an RGMII interface and the like. The second interface to be tested comprises a UISM interface, a digital audio (I2S + PCM) interface, a radio frequency (RF _ ANT) interface, a first analog-to-digital conversion (ADC1) interface, a second analog-to-digital conversion (ADC2) interface, a fifth input/output (GPIO5) interface or a RESET (RESET) interface. The third interface to be tested comprises a UART interface.
The upper computer 2 comprises a third data interface, a fourth data interface and a USB2.0 interface, wherein the third data interface comprises a solid state disk interface or a network cable interface, and the fourth data interface comprises a USB3.1 interface.
The control module 8 includes a first input output (GPIO1) interface, a third Voltage (VCC) interface, a second input output (GPIO2) interface, a third input output (GPIO3) interface, a fourth input output (GPIO4) interface, and a third analog-to-digital conversion (ADC3) interface.
The USB3.1 interface of the upper computer 2 is electrically connected with one end of the second data conversion module 4 through a USB3.1 interface data line, the other end of the second data conversion module 4 is electrically connected with the USB2.0/2.1 interface and the USB3.0/3.1 interface of the module test seat 1 through a USB2.0/2.1 data line and a USB3.0/3.1 data line respectively, and the USB2.0/2.1 interface and the USB3.0/3.1 interface of the module test seat 1 are electrically connected with the second interface to be tested.
In this embodiment, the first data conversion module 3 includes a first data interface and a second data interface, an interface type of the first data interface of the first data conversion module 3 is the same as an interface type of the first interface to be tested (that is, the interface type of the first data interface of the first data conversion module 3 is the same as an interface type of the pci 2.0/3.0 interface or an interface type of the RGMII interface), and an interface type of the second data of the first data conversion module 3 is the same as an interface type of the third data interface of the upper computer 2 (that is, the interface type of the second data of the first data conversion module 3 is the same as an interface type of the solid state disk interface of the upper computer 2 or an interface type of the network cable interface).
When the first interface to be tested is the pci 2.0/3.0 interface and the first data conversion module 3 is the first data conversion submodule 31, the pci 2.0/3.0 interface of the module test socket 1 is electrically connected with one end of the first data conversion submodule 31, and the other end of the first data conversion submodule 31 is electrically connected with the solid state disk interface of the upper computer 2 through the m.2fcp flexible flat cable.
When the PCIe2.0/3.0 interface of the test module test socket 1 is tested, the upper computer 2 is used for sending a target test instruction to the communication interfaces USB2.0/2.1 and USB3.0/3.1 through the solid state disk interface; the module test socket 1 is used for sending the data to be tested corresponding to the interface PCIe2.0/3.0 to the first data conversion submodule 31 through the interface PCIe2.0/3.0 according to the target test instruction received by the communication interfaces USB2.0/2.1 and USB 3.0/3.1; the first data conversion submodule 31 is configured to convert corresponding data to be tested into target data and send the target data to the upper computer 2 through the solid state disk interface; the upper computer 2 is also used for detecting target data and generating a test result.
In this embodiment, when the first interface to be tested is the RGMII interface and the first data conversion module 3 is the first data conversion sub-module 32, the RGMII interface of the module test socket 1 is electrically connected to one end of the first data conversion sub-module 32, and the other end of the first data conversion sub-module 32 is electrically connected to the network cable interface of the upper computer 2 through the network cable with the rate of 1G.
When the testing module tests the RGMII interface of the seat 1, the upper computer 2 is used for sending a target testing instruction to the communication interfaces USB2.0/2.1 and USB3.0/3.1 through the network cable interface; the module test socket 1 is used for sending the data to be tested corresponding to the RGMII interface to the first data conversion submodule 32 through the RGMII interface according to the target test instruction received by the communication interfaces USB2.0/2.1 and USB 3.0/3.1; the first data conversion submodule 32 is configured to convert corresponding data to be tested into target data and send the target data to the upper computer 2 through the network cable interface; the upper computer 2 is also used for detecting target data and generating a test result.
In this embodiment, the second data conversion module 4 includes a first USB type interface and a second USB type interface, and the first USB type interface of the second data conversion module 4 is the same as the interface types of the communication interfaces USB2.0/2.1 and USB3.0/3.1 of the module test socket 1. The second USB type interface of the second data conversion module 4 is the same as the fourth data interface of the upper computer 2 in interface type (i.e., the second USB type interface of the second data conversion module 4 is the same as the USB3.1 interface of the upper computer 2 in interface type), and the second data conversion module is a USB-HUB (USB expansion interface) interface.
In this embodiment, when the second interface to be tested is a UISM interface, as shown in fig. 1, the first SIM card socket 121 is electrically connected to the UISM1 interface of the module test socket 1, and the second SIM card socket 122 is electrically connected to the UISM2 interface of the module test socket 1, where the number of inserted SIM cards is determined according to the function of the module test socket 1 (i.e., the function of the communication module to be tested), and when the module test socket 1 supports a single SIM card, the SIM card 121 is inserted into the first SIM card socket 121.
When the USIM1 interface of the test module test socket 1 is tested, the upper computer 2 is used for sending a target test instruction to the communication interfaces USB2.0/2.1 and USB3.0/3.1 through the USB3.1 interface; the module test socket 1 is used for sending data to be tested corresponding to the USIM1 interface to the second data conversion module 4 through the USB2.0/2.1 interface and the USB3.0/3.1 interface according to a target test instruction received by the communication interfaces USB2.0/2.1 and USB 3.0/3.1; the second data conversion module 4 is used for performing format conversion processing on the corresponding data to be tested received through the USB2.0/2.1 interface and the USB3.0/3.1 interface and sending the corresponding data to be tested after the format conversion processing to the upper computer 2 through the USB3.1 interface; the upper computer 2 is also used for detecting data to be tested and generating a test result.
When the module test socket 1 supports dual SIM cards, the SIM121 card is inserted into the first SIM card socket 121, and the SIM122 card is inserted into the second SIM card socket 122.
When the USIM1 interface and the USIM2 interface of the test module test socket 1 are connected, the upper computer 2 is used for sending a target test instruction to the communication interfaces USB2.0/2.1 and USB3.0/3.1 through the USB3.1 interface; the module test socket 1 is used for sending data to be tested corresponding to the USIM1 interface and the USIM2 interface to the second data conversion module 4 through the USB2.0/2.1 interface and the USB3.0/3.1 interface according to a target test instruction received by the communication interfaces USB2.0/2.1 and USB 3.0/3.1; the second data conversion module 4 is used for performing format conversion processing on the corresponding data to be tested received through the USB2.0/2.1 interface and the USB3.0/3.1 interface and sending the corresponding data to be tested after the format conversion processing to the upper computer 2 through the USB3.1 interface; the upper computer 2 is also used for detecting data to be tested and generating a test result.
In this embodiment, when the second interface to be tested is a digital audio (I2S + PCM) interface, the digital audio (I2S + PCM) interface of the module test socket 1 is electrically connected to one end of the third data conversion module 9, and the other end of the third data conversion module 9 is electrically connected to the analog module 10.
When the test module tests the digital audio (I2S + PCM) interface of the socket 1, the upper computer 2 is used for sending a target test instruction to the communication interfaces USB2.0/2.1 and USB3.0/3.1 through the USB3.1 interface; the module test socket 1 is used for sending data to be tested corresponding to a digital audio (I2S + PCM) interface to the second data conversion module 4 through the USB2.0/2.1 interface and the USB3.0/3.1 interface according to a target test instruction received by the communication interfaces USB2.0/2.1 and USB 3.0/3.1; the second data conversion module 4 is used for performing format conversion processing on the corresponding data to be tested received through the USB2.0/2.1 interface and the USB3.0/3.1 interface and sending the corresponding data to be tested after the format conversion processing to the upper computer 2 through the USB3.1 interface; the upper computer 2 is also used for detecting data to be tested and generating a test result.
In this embodiment, the analog module 10 is configured to send an analog signal to the third data conversion module 9; the third data conversion module 9 is used for converting the analog signal into data to be tested corresponding to the digital audio (I2S + PCM) interface and sending the data to be tested to the digital audio (I2S + PCM) interface. Wherein the analog module 10 needs to keep the analog signal connection 3S (3 seconds) free from a drop.
In this embodiment, when the second interface to be tested is a radio frequency (RF _ ANT) interface, the radio frequency (RF _ ANT) interface of the module test socket 1 is electrically connected to the fourth data conversion module 11.
When testing the radio frequency (RF _ ANT) interface of the module test socket 1, the upper computer 2 is used for sending a target test instruction to the communication interfaces USB2.0/2.1 and USB3.0/3.1 through the USB3.1 interface; the module test socket 1 is configured to send, according to a target test instruction received by the communication interfaces USB2.0/2.1 and USB3.0/3.1, to-be-tested data corresponding to a radio frequency (RF _ ANT) interface generated by the fourth data conversion module 11 to the second data conversion module 4 through the USB2.0/2.1 interface and the USB3.0/3.1 interface; the second data conversion module 4 is used for performing format conversion processing on the corresponding data to be tested received through the USB2.0/2.1 interface and the USB3.0/3.1 interface and sending the corresponding data to be tested after the format conversion processing to the upper computer 2 through the USB3.1 interface; the upper computer 2 is also used for detecting data to be tested and generating a test result.
In this embodiment, when the second interface to be tested is the first analog-to-digital conversion (ADC1) interface and the second analog-to-digital conversion (ADC2) interface.
The input end of the first power management unit 5, the input end of the second power management unit 6 and the input end of the third power management unit 7 are electrically connected with the external power supply device 13, the output end of the first power management unit 5 is electrically connected with a first voltage (VBAT _ RF) interface of the module test socket 1, the output end of the second power management unit 6 is electrically connected with a second voltage (VBAT _ BB) interface of the module test socket 1, and the output end of the third power management unit 7 is electrically connected with a third Voltage (VCC) interface of the control module 8; one end of the first current limiting resistor R1 is electrically connected to the first analog-to-digital conversion interface (ADC1), one end of the second current limiting resistor R2 is electrically connected to the second analog-to-digital conversion interface (ADC2), and the other ends of the first current limiting resistor R1 and the second current limiting resistor R2 are both electrically connected to the output terminal of the second power management unit 6. The external power supply device 13 has an operating voltage of 5V and an operating current of 3A.
The first power management unit 5 is configured to convert a voltage of 5V obtained from the external power supply 13 into an operating voltage of 3.8V required by the first voltage (VBAT _ RF) interface of the module test socket 1, so as to supply power to the first voltage (VBAT _ RF) interface of the module test socket 1.
The second power management unit 6 is configured to convert the 5V voltage obtained from the external power supply 13 into an operating voltage of 3.8V required by the second voltage (VBAT _ BB) interface of the module test socket 1, so as to supply power to the second voltage (VBAT _ BB) interface of the module test socket 1. The first current limiting resistor R1 and the second current limiting resistor R2 are both used for detecting the operating voltage of the second voltage (VBAT _ BB) interface of the module test socket 1.
The third power management unit 7 is configured to convert the 5V voltage obtained from the external power supply device 13 into an operating voltage of 3.6V required by a third Voltage (VCC) interface of the control module 8, so as to supply power to the control module 8.
When the first analog-to-digital conversion (ADC1) interface and the second analog-to-digital conversion (ADC2) interface of the test module test socket 1 are used, the upper computer 2 is used for sending a target test instruction to the communication interfaces USB2.0/2.1 and USB3.0/3.1 through the USB3.1 interface; the module test socket 1 is used for sending the data to be tested corresponding to the first analog-to-digital conversion (ADC1) interface and the second analog-to-digital conversion (ADC2) interface to the second data conversion module 4 through the USB2.0/2.1 interface and the USB3.0/3.1 interface according to a target test instruction received by the communication interfaces USB2.0/2.1 and USB 3.0/3.1; the second data conversion module 4 is used for performing format conversion processing on the corresponding data to be tested received through the USB2.0/2.1 interface and the USB3.0/3.1 interface and sending the corresponding data to be tested after the format conversion processing to the upper computer 2 through the USB3.1 interface; the upper computer 2 is also used for detecting data to be tested and generating a test result.
In this embodiment, the base of the first transistor Q1 is electrically connected to the third input/output (GPIO3) interface of the control module 8, the emitter of the first transistor Q1 is grounded, the collector of the first transistor Q1 is electrically connected to one end of the third current limiting resistor R3, and the other end of the third current limiting resistor R3 is electrically connected to the enable pin EN-5 of the first power management unit 5.
The base of the second triode Q2 is electrically connected to the fourth input/output (GPIO4) interface of the control module 8, the emitter of the second triode Q2 is grounded, the collector of the second triode Q2 is electrically connected to one end of a fourth current-limiting resistor R4, and the other end of the fourth current-limiting resistor R3 is electrically connected to the enable pin EN-6 of the second power management unit 6.
The first input/output (GPIO1) interface of the control module 8 is electrically connected to the power supply (PWRKEY) interface of the module test socket 1.
The second input/output (GPIO2) interface of the control module 8 is electrically connected to the RESET (RESET) interface of the module test socket 1.
The third analog-to-digital conversion (ADC3) interface of the control module 8 is electrically connected to the fifth input/output (GPIO5) interface of the module socket 1.
The control module 8 is used for supplying power to the module test socket 1 and controlling the startup and shutdown of the module test socket 1 and pairing the test development board through Bluetooth, and the third current-limiting resistor R3 and the fourth current-limiting resistor R4 are used for preventing the first triode Q1 and the second triode Q2 from being directly grounded to damage pins.
Specifically, when the communication module that awaits measuring is effectively placed on module test socket 1, open the test software of automatic test development board on host computer 2, this moment, BT1 (bluetooth) of control module 8 searches for the BT2 of host computer 2, accomplish the back of pairing, and the Power (PWRKEY) interface that last 4S (4 seconds) low level signal was given to module test socket 1 is exported to first input/output (GPIO1) interface in the control module 8, and the communication module that awaits measuring on the module test socket 1 starts. In this embodiment, the test development board is paired through bluetooth, so that the remote encryption of the test development board is facilitated.
When the third input/output (GPIO3) interface of the control module 8 inputs a high level signal to the base of the first transistor Q1, the collector of the first transistor Q1 outputs a low level signal to the enable pin EN-5 of the first power management unit 5, and at this time, the first power management unit 5 stops supplying power to the first voltage (VBAT _ RF) interface of the module test socket 1; meanwhile, a fourth input/output (GPIO4) interface of the control module 8 inputs a high level signal to a base of the second transistor Q2, and a collector of the second transistor Q2 outputs a low level signal to an enable pin EN-6 of the second power management unit 6, at this time, the second power management unit 6 also stops supplying power to the second voltage (VBAT _ BB) interface of the module test socket 1, and the module test socket 1 (i.e., the communication module to be tested) is shut down.
In this embodiment, when the second interface to be tested is the fifth input/output (GPIO5) interface, the fifth input/output (GPIO5) interface of the module test socket 1 is tested under the condition that the module test socket 1 (i.e., the communication module to be tested) is turned off, and the upper computer 2 is configured to send the target test instruction to the communication interfaces USB2.0/2.1 and USB3.0/3.1 through the USB3.1 interface; the module test socket 1 is used for sending data to be tested corresponding to the fifth input/output (GPIO5) interface to the second data conversion module 4 through the USB2.0/2.1 interface and the USB3.0/3.1 interface according to a target test instruction received by the communication interfaces USB2.0/2.1 and USB 3.0/3.1; the second data conversion module 4 is used for performing format conversion processing on the corresponding data to be tested received through the USB2.0/2.1 interface and the USB3.0/3.1 interface and sending the corresponding data to be tested after the format conversion processing to the upper computer 2 through the USB3.1 interface; the upper computer 2 is further configured to check the data to be tested with the setting standards and generate a test result, specifically, if the data to be tested is between the setting standards, the fifth input/output (GPIO5) interface function test PASS is performed, and if the data to be tested is not between the setting standards, the fifth input/output (GPIO5) interface function test fails, where the setting standards are 1M to 10M ohms.
In this embodiment, when the second interface to be tested is a RESET (RESET) interface, the RESET key of the test software is first clicked on the upper computer 2, and at this time, the second input/output (GPIO2) interface of the control module 8 pulls down the RESET (RESET) interface of the test module test socket 1 (i.e., the communication module to be tested), so that the test module test socket 1 (i.e., the communication module to be tested) is RESET. After the test module test seat 1 (namely the communication module to be tested) is reset, the upper computer 2 is used for sending a target test instruction to the communication interfaces USB2.0/2.1 and USB3.0/3.1 through the USB3.1 interface; the module test socket 1 is used for sending data to be tested corresponding to a RESET (RESET) interface to the second data conversion module 4 through the USB2.0/2.1 interface and the USB3.0/3.1 interface according to a target test instruction received by the communication interfaces USB2.0/2.1 and USB 3.0/3.1; the second data conversion module 4 is used for performing format conversion processing on the corresponding data to be tested received through the USB2.0/2.1 interface and the USB3.0/3.1 interface and sending the corresponding data to be tested after the format conversion processing to the upper computer 2 through the USB3.1 interface; the upper computer 2 is also used for detecting data to be tested and generating a test result.
In this embodiment, when the third interface to be tested is a UART interface, the USB2.0 interface of the upper computer 2 is electrically connected to the UART interface of the module test socket 1 through a UART data line.
When the test module tests the UART interface of the seat 1, the upper computer 2 is used for sending a target test instruction to the communication interfaces USB2.0/2.1 and USB3.0/3.1 through the USB2.0 interface; the module test seat 1 is used for sending data to be tested corresponding to the UART interface to the upper computer 2 through the UART data line according to target test instructions received by the communication interfaces USB2.0/2.1 and USB 3.0/3.1; the upper computer 2 is also used for detecting data to be tested and generating a test result.
In this embodiment, when the upper computer 2 displays that the whole process test PASS (PASS), the communication module to be tested performs the function test PASS, and the communication module to be tested is taken out to perform the test of the next communication module.
When the module test seat 1 (i.e. the communication module to be tested) or the control module 8 has a system fault or is halted, the USB power supply data line connected to the upper computer 2 is plugged again, and the whole system is powered on again for resetting, so that the module test seat 1 (i.e. the communication module to be tested) or the control module 8 is recovered to be normal.
When the test development board needs to analyze and debug logs, the test development board can grab through a USB virtual COM (serial communication port) port, and can also connect a UART data line to the upper computer 2 or the bottom Log through a UART interface, so that debugging and analysis are facilitated.
In this embodiment, the upper computer 2 communicates with the module test socket 1 (i.e., the upper computer 2 communicates with the communication module to be tested) through AT least one virtual COM port of the USB2.0/2.1 data line and the USB3.0/USB3.1 data line connected to the upper computer 2, and AT (attention) command communication may be used. When testing the communication module that awaits measuring, produce the line operation personnel and only need hit the start-up button, can go up the electricity and realize automated testing to the communication module that awaits measuring, use test development board to carry out automated testing to the communication module that awaits measuring, do not need extra design hardware, improved test speed and test productivity, reduced test cost.
Although specific embodiments of the present invention have been described above, it will be understood by those skilled in the art that this is by way of example only and that the scope of the invention is defined by the appended claims. Various changes and modifications to these embodiments may be made by those skilled in the art without departing from the spirit and the principles of the present invention, and these changes and modifications are all within the scope of the present invention.
Claims (10)
1. The automatic test development board for the communication module is characterized by comprising a development board body, a module test seat fixedly arranged on the development board body, an upper computer and a plurality of first data conversion modules;
the module test seat comprises a communication interface, a plurality of first interfaces to be tested and a plurality of second interfaces to be tested; the communication interface is electrically connected with the second interface to be tested and the upper computer respectively;
each first data conversion module is electrically connected with the first interface to be tested and the upper computer respectively;
the communication module to be tested is fixedly arranged on the module test seat;
the upper computer is used for generating a target test instruction and sending the target test instruction to the communication interface;
the module test seat is used for sending the data to be tested corresponding to the first interface to be tested to the first data conversion module according to the target test instruction received by the communication interface;
each first data conversion module is used for converting the corresponding data to be tested into target data and sending the target data to the upper computer;
the upper computer is also used for detecting the target data and generating a test result; or the like, or, alternatively,
the module test seat is used for sending the data to be tested corresponding to the second interface to be tested to the upper computer through the communication interface according to the target test instruction received by the communication interface;
the upper computer is also used for detecting the data to be tested and generating a test result.
2. The test development board of claim 1, wherein the first data conversion module comprises a first data interface and a second data interface; the upper computer comprises a third data interface;
the interface type of the first data interface is the same as that of the first interface to be tested, and the interface type of the second data interface is the same as that of the third data interface;
the upper computer is used for sending the target test instruction to the communication interface through the third data interface;
the module test socket is used for sending the to-be-tested data corresponding to the first to-be-tested interface to the first data conversion module through the first data interface according to the target test instruction received by the communication interface;
the first data conversion module is used for converting the corresponding data to be tested into the target data and sending the target data to the upper computer through the second data interface;
the upper computer is also used for detecting the target data and generating a test result.
3. The test development board of claim 1, further comprising a second data conversion module secured to the development board body;
the second data conversion module comprises a first USB type interface and a second USB type interface; the upper computer comprises a fourth data interface;
the first USB type interface and the communication interface are the same in interface type, and the second USB type interface and the fourth data interface are the same in interface type;
the upper computer is used for sending the target test instruction to the communication interface through the fourth data interface;
the module test socket is used for sending the data to be tested corresponding to the second interface to be tested to the second data conversion module through the first USB type interface according to the target test instruction received by the communication interface;
the second data conversion module is used for carrying out format conversion processing on the corresponding data to be tested received through the first USB type interface and sending the corresponding data to be tested after the format conversion processing to the upper computer through the second USB type interface;
the upper computer is also used for detecting the data to be tested and generating a test result.
4. The test development board of claim 3, wherein the module test socket further comprises a third interface under test; the upper computer also comprises a USB2.0 interface;
the USB2.0 interface is electrically connected with the third interface to be tested through a UART data line;
the upper computer is used for sending the target test instruction to the communication interface through the USB2.0 interface;
the module test seat is used for sending the data to be tested corresponding to the third interface to be tested to the upper computer through the UART data wire according to the target test instruction received by the communication interface;
the upper computer is also used for detecting the data to be tested and generating a test result.
5. The test development board of claim 1, wherein the test development board further comprises a first power management unit, a second power management unit, a third power management unit and a control module, the first power management unit, the second power management unit, the third power management unit and the control module are fixedly arranged on the development board body, the module test socket further comprises a first voltage interface, a second voltage interface and a power interface, and the control module comprises a first input/output interface and a third voltage interface;
the input end of the first power management unit, the input end of the second power management unit and the input end of the third power management unit are electrically connected with external power supply equipment, the output end of the first power management unit is electrically connected with the first voltage interface, and the output end of the second power management unit is electrically connected with the second voltage interface;
the output end of the third power management unit is electrically connected with the third voltage interface;
the first input/output interface is electrically connected with the power interface;
the first power management unit and the second power management unit are respectively used for supplying power to the first voltage interface and the second voltage interface of the module test socket;
the third power management unit is used for supplying power to the control module;
the control module is used for supplying power to the module test seat.
6. The test development board of claim 5, wherein the test development board further comprises a first current limiting resistor and a second current limiting resistor fixed on the development board body, and the module test socket further comprises a first analog-to-digital conversion interface and a second analog-to-digital conversion interface;
one end of the first current limiting resistor is electrically connected with the first analog-to-digital conversion interface, one end of the second current limiting resistor is electrically connected with the second analog-to-digital conversion interface, and the other end of the first current limiting resistor and the other end of the second current limiting resistor are both electrically connected with the output end of the second power management unit.
7. The test development board of claim 5, wherein the test development board further comprises a first transistor, a second transistor, a third current limiting resistor, and a fourth current limiting resistor fixed on the development board body, the control module further comprises a second input/output interface, a third input/output interface, a fourth input/output interface, and a third analog-to-digital conversion interface, and the module test socket further comprises a fifth input/output interface and a reset interface;
a base electrode of the first triode is electrically connected with the third input/output interface, an emitting electrode of the first triode is grounded, a collector electrode of the first triode is electrically connected with one end of the third current limiting resistor, and the other end of the third current limiting resistor is electrically connected with an enabling pin of the first power management unit;
a base electrode of the second triode is electrically connected with the fourth input/output interface, an emitting electrode of the second triode is grounded, a collector electrode of the second triode is electrically connected with one end of the fourth current limiting resistor, and the other end of the fourth current limiting resistor is electrically connected with an enabling pin of the second power management unit;
the second input/output interface is electrically connected with the reset interface;
the third analog-to-digital conversion interface is electrically connected with the fifth input/output interface.
8. The test development board of claim 3, wherein the first interface under test comprises a PCIe2.0/3.0 interface or an RGMII interface;
the second interface to be tested comprises a UISM interface, a digital audio interface, a radio frequency interface, an analog-to-digital conversion interface, an input/output interface or a reset interface;
the first USB type interface comprises a USB2.0/2.1 interface and a USB3.0/3.1 interface;
the second USB type interface and the fourth data interface each comprise a USB3.1 interface.
9. The test development board of claim 2, wherein the third data interface comprises a solid state disk interface or a network cable interface.
10. The test development board of claim 4 wherein the first USB type interface comprises a USB2.0/2.1 interface and a USB3.0/3.1 interface;
and/or the third interface to be tested comprises a UART interface.
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| CN202021612686.7U CN212809187U (en) | 2020-08-05 | 2020-08-05 | Automatic test development board of communication module |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113676946A (en) * | 2021-10-21 | 2021-11-19 | 湖南欧智通科技有限公司 | Extensible multiplexing WIFI module automatic test system |
| CN113765739A (en) * | 2021-08-02 | 2021-12-07 | 合肥移瑞通信技术有限公司 | Testing device and testing method for Internet of things interface module |
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2020
- 2020-08-05 CN CN202021612686.7U patent/CN212809187U/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113765739A (en) * | 2021-08-02 | 2021-12-07 | 合肥移瑞通信技术有限公司 | Testing device and testing method for Internet of things interface module |
| CN113676946A (en) * | 2021-10-21 | 2021-11-19 | 湖南欧智通科技有限公司 | Extensible multiplexing WIFI module automatic test system |
| CN113676946B (en) * | 2021-10-21 | 2022-02-11 | 湖南欧智通科技有限公司 | Extensible multiplexing WIFI module automatic test system |
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