CN212693964U

CN212693964U - Circuit structure capable of detecting on-off signal of switch

Info

Publication number: CN212693964U
Application number: CN202021204075.9U
Authority: CN
Inventors: 崔建武; 杨斌
Original assignee: Xi'an Tronwe Electronics Measurement And Control Co ltd
Current assignee: Xi'an Tronwe Electronics Measurement And Control Co ltd
Priority date: 2020-06-28
Filing date: 2020-06-28
Publication date: 2021-03-12
Anticipated expiration: 2030-06-28

Abstract

The utility model discloses a circuit structure of detectable switch break-make signal, including FPGA core control circuit, a plurality of detection interface circuit and a plurality of state change output interface circuit, detect interface circuit with state change output interface circuit connects respectively FPGA core control circuit, FPGA core control circuit passes through detection interface circuit carries out switching value to level signal's conversion and isolation, state change output interface circuit is used for receiving PFGA core control circuit's latch output signal to export to oscilloscope interface connector. Has the advantages that: the detection response of the embedded FPGA technology to the switch state change can reach 0.1uS, so that the omission is greatly avoided; the initial state of the switch can be set, and the user is reminded to check when the actual state is inconsistent with the set state, so that the effectiveness of the test is improved; the signals are isolated and antistatic at the detection interface, so that the equipment can be effectively protected in the test process.

Description

Circuit structure capable of detecting on-off signal of switch

Technical Field

The utility model relates to a technical field is measured in the test, concretely relates to circuit structure of detectable switch break-make signal.

Background

In the initiating explosive device ignition test, because the environmental noise is too big, it is not suitable for personnel to use equipment to detect closely, need to carry out synchronous record and output of the switch change state that needs monitoring in the test. The switch in the test may have high voltage interference, reduce the test effectiveness, and may damage the oscilloscope probe or all the equipment.

SUMMERY OF THE UTILITY MODEL

The utility model aims at providing a circuit structure of detectable switch break-make signal just in order to solve above-mentioned problem, the utility model provides an among a great deal of technical scheme preferred technical scheme have: the test effectiveness is improved, the isolation and antistatic measures are good, the equipment can be protected, and the like, and the technical effects are described in detail below.

In order to achieve the above purpose, the utility model provides a following technical scheme:

the utility model provides a pair of circuit structure of detectable switch break-make signal, including FPGA core control circuit, a plurality of detection interface circuit and a plurality of state change output interface circuit, detect interface circuit with state change output interface circuit connects respectively FPGA core control circuit, FPGA core control circuit passes through detection interface circuit carries out switching value to level signal's conversion and isolation, state change output interface circuit is used for receiving PFGA core control circuit's latch output signal to export to oscilloscope interface connector.

Preferably, the device further comprises an isolation circuit module, wherein the isolation circuit module is used for providing an isolation power supply for the detection interface circuit and the state change output interface circuit after being connected with the power supply module.

Preferably, the input interfaces of the detection interface circuit and the state change output interface circuit are both provided with an anti-transient high-voltage module.

Preferably, the device also comprises a power conversion circuit which is connected with the detection interface circuit, the state change output interface circuit and the FPGA core control circuit.

Preferably, the FPGA core control circuit is further connected with a reset circuit and a reference clock.

Preferably, the FPGA core control circuit is connected with a red/green state indication module for indicating an output signal.

To sum up, the utility model has the advantages that: 1. the detection response of the embedded FPGA technology to the switch state change can reach 0.1uS, so that the omission is greatly avoided;

2. the initial state of the switch can be set, and the user is reminded to check when the actual state is inconsistent with the set state, so that the effectiveness of the test is improved;

3. the signals are isolated and antistatic at the detection interface, so that the equipment can be effectively protected in the test process.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.

Fig. 1 is a schematic structural diagram of the present invention;

FIG. 2 is a schematic diagram of the power isolation circuit of the present invention;

fig. 3 is a schematic diagram of an interface conversion circuit of the present invention;

FIG. 4 is a schematic diagram of a power conversion circuit of the present invention;

fig. 5 is a schematic diagram of the integrated reset management circuit of the present invention;

FIG. 6 is a schematic diagram of the reference clock circuit of the present invention;

FIG. 7 is a schematic diagram of the FPGA core control circuit of the present invention;

FIG. 8 is a schematic diagram of the JTAG debug interface and FPGA program power-on auto-loading circuit of the present invention;

fig. 9 is a schematic diagram of a reset normal or reset fault and state change indicating circuit of the present invention;

fig. 10 is a schematic diagram of a state change output interface circuit according to the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention clearer, the technical solutions of the present invention will be described in detail below. It is to be understood that the embodiments described are only some embodiments of the invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by a person skilled in the art without creative efforts belong to the protection scope of the present invention.

Referring to fig. 1-10, the present invention provides a circuit structure capable of detecting on/off signals of a switch, including an FPGA core control circuit, a plurality of detection interface circuits and a plurality of state change output interface circuits, wherein the FPGA core control circuit is used for detecting 20 level signals and latching and outputting the first change after reset, the state change output interface circuit receives the latched output signal of the FPGA core control circuit and outputs the latched output signal to an oscilloscope interface connector, the detection interface circuit realizes the conversion and isolation from the switching value to the level signals, the detection interface circuits and the state change output interface circuits are respectively connected with the FPGA core control circuit, the FPGA core control circuit performs the conversion and isolation from the switching value to the level signals through the detection interface circuit, the state change output interface circuit is used for receiving the latched output signal of the PFGA core control circuit, and output to the oscilloscope interface connector.

As an optional implementation, the system further comprises an isolation circuit module, wherein the isolation circuit module is used for providing an isolation power supply for the detection interface circuit and the state change output interface circuit after being connected with the power supply module;

the input interfaces of the detection interface circuit and the state change output interface circuit are provided with anti-transient high-voltage modules, so that the transient high voltage in the circuits is prevented from causing adverse effects on the interface conversion circuit;

the circuit is connected with the detection interface circuit, the state change output interface circuit and the FPGA core control circuit, converts various voltages required by the circuit through voltages and supplies power to all chips;

the FPGA core control circuit is also connected with a reset circuit and a reference clock, as shown in fig. 5, the reset circuit mainly realizes the power-on reset and the delay processing of the reset signal of the utility model, thereby ensuring the reliable reset; as shown in fig. 6, the reference clock circuit provides a reference clock for the FPGA core control circuit;

the FPGA core control circuit is connected with a red/green state indicating module for indicating an output signal;

fig. 7 is a schematic diagram of an FPGA core control circuit that stores settings of an initial state after 20 resets and detects 20 level signals and latches outputs for a first change after reset. The circuit is the core circuit of the utility model and is connected with all the peripheral circuits;

FIG. 8 is a schematic diagram of a JTAG debug interface and an FPGA program power-on automatic loading circuit, which mainly provides a debug interface for the circuit in FIG. 7, stores its hardware program code, and automatically loads its program code when power is on, and the circuit is connected with an FPGA core control module;

fig. 9 is a state indication after reset, where the reset button is pressed, the FPGA detects an initial state of the channel switch, and if the line state is consistent with the setting state of the rocker switch, the green LED of the corresponding channel is turned on, and if the initial state is inconsistent, the red LED of the corresponding channel is turned on; ignition test detection can be entered only when all the states are indicated as green after reset; in the ignition process, when the state of a certain channel of the on-off signal changes, the indicator light corresponding to the channel changes from green to red;

FIG. 10 is a schematic diagram of a state change output interface circuit that outputs signals from the FPGA through a buffer to the BNC output terminal.

By adopting the structure, the on/off signal can be conditioned in the ignition test of the dynamic power source initiating explosive device, the on/off signal is converted into a standard TTL signal, and the relative action time of the on/off signal is observed through an external oscilloscope, so that the test efficiency is improved, and the safety of personnel in the test is ensured; the detection response of the embedded FPGA technology to the switch state change can reach 0.1uS, so that the omission is greatly avoided; the initial state of the switch can be set, and the user is reminded to check when the actual state is inconsistent with the set state, so that the effectiveness of the test is improved; the signals are isolated and antistatic at the detection interface, so that the equipment can be effectively protected in the test process.

The above description is only for the specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto, and any person skilled in the art can easily think of the changes or substitutions within the technical scope of the present invention, and all should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A circuit structure capable of detecting on-off signals of a switch is characterized by comprising an FPGA core control circuit, a plurality of detection interface circuits and a plurality of state change output interface circuits, wherein the detection interface circuits and the state change output interface circuits are respectively connected with the FPGA core control circuit, the FPGA core control circuit carries out switching value to level signal conversion and isolation through the detection interface circuits, and the state change output interface circuits are used for receiving latching output signals of the PFGA core control circuit and outputting the latching output signals to an oscilloscope interface connector.

2. The circuit structure of claim 1, wherein the circuit structure is capable of detecting the on/off signal of the switch, and comprises: the isolation circuit module is used for providing an isolation power supply for the detection interface circuit and the state change output interface circuit after being connected with the power supply module.

3. The circuit structure of claim 1, wherein the circuit structure is capable of detecting the on/off signal of the switch, and comprises: and the input interfaces of the detection interface circuit and the state change output interface circuit are provided with anti-transient high-voltage modules.

4. The circuit structure of claim 1, wherein the circuit structure is capable of detecting the on/off signal of the switch, and comprises: the power supply conversion circuit is connected with the detection interface circuit, the state change output interface circuit and the FPGA core control circuit.

5. The circuit structure of claim 1, wherein the circuit structure is capable of detecting the on/off signal of the switch, and comprises: the FPGA core control circuit is also connected with a reset circuit and a reference clock.

6. The circuit structure of claim 1, wherein the circuit structure is capable of detecting the on/off signal of the switch, and comprises: the FPGA core control circuit is connected with a red/green state indicating module for indicating an output signal.