CN212676291U - Full back electrode solar cell and full back electrode cell assembly - Google Patents
Full back electrode solar cell and full back electrode cell assembly Download PDFInfo
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- CN212676291U CN212676291U CN202021108338.6U CN202021108338U CN212676291U CN 212676291 U CN212676291 U CN 212676291U CN 202021108338 U CN202021108338 U CN 202021108338U CN 212676291 U CN212676291 U CN 212676291U
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Abstract
The utility model provides a full back of body electrode solar cell and full back of body electrode battery pack relates to photovoltaic technology field. The full back electrode solar cell comprises a silicon substrate, wherein the backlight surface of the silicon substrate is divided into a second part and a first part; the first part is doped to form a first carrier collecting region; a metal chalcogenide layer having a blocking structure electrically dividing the metal chalcogenide layer into a first carrier conduction region and a second carrier collection region; the first carrier conduction region is a part of the metal oxygen group compound layer, which is positioned in the projection of the first part, and the second carrier collection region is a part of the metal oxygen group compound layer, which is positioned in the projection of the second part; the first electrodes are correspondingly arranged on the first carrier conduction regions; the second electrode is correspondingly arranged on the second carrier collecting region. The vertical series resistance is low, electric leakage or short circuit can be avoided, extra alignment is not needed, the process is simple, the composition is reduced, and the photoelectric conversion efficiency is improved.
Description
Technical Field
The utility model relates to the field of photovoltaic technology, especially, relate to a full back electrode solar cell and full back electrode battery pack.
Background
At present, a full back electrode solar cell generally needs to form two doped regions on a backlight surface of a silicon substrate by doping means such as diffusion or ion implantation. Because the two doped regions are located in the same plane, the two doped regions cannot be superposed together, and very accurate alignment is required.
SUMMERY OF THE UTILITY MODEL
The utility model provides a full back electrode solar cell and full back electrode battery pack aims at solving the problem that the accurate technology of preparation counterpoint is complicated.
According to the utility model discloses an aspect provides a full back electrode solar cell, include:
the backlight surface of the silicon substrate is divided into a first part and a second part; the first portion is doped to form a first carrier-collection region;
a metal-oxygen-group compound layer deposited on a backlight surface of the entire silicon substrate, in which a blocking structure electrically dividing the metal-oxygen-group compound layer into a first carrier conduction region and a second carrier collection region is provided; wherein the first carrier conduction region corresponds to the first portion; the second carrier-collection region corresponds to the second portion;
a first electrode correspondingly disposed on the first carrier conduction region;
and a second electrode disposed correspondingly to the second carrier collecting region.
The utility model discloses in the embodiment, first carrier collecting region is through the doping of the first part of the backlight face of silicon base member and forms, can absorb first carrier and repel the second carrier, plays first carrier selectivity effect, and then in first carrier collecting region, first carrier density is higher, and second carrier density is lower. The blocking structure electrically divides the metal oxygen group compound layer into a first carrier conduction region and a second carrier collection region, and the conduction band energy level of the second carrier in the second carrier collection region is close to the conduction energy level of the second carrier in the second part at the position close to the interface of the second part, so that the effect of absorbing the second carrier and repelling the first carrier can be achieved. The first carrier collecting region is high in first carrier density and low in second carrier density, and the conduction energy level of the first carrier conduction region is close to the conduction energy level of the first carrier corresponding to the first part, so that the first carrier in the first carrier collecting region can directly enter the first carrier conduction region, and collection and transmission of the first carrier are achieved. Meanwhile, the first carrier conduction region and the second carrier collection region are divided by the blocking structure, so that the transverse transmission capability of the whole metal oxygen group compound layer is very low, the longitudinal conduction capability of the metal oxygen group compound layer can be improved, transverse electric leakage is avoided, and longitudinal series resistance can be reduced to a great extent. And the first carrier conduction region and the second carrier collection region are divided by the blocking structure, different types of carriers are longitudinally transmitted into corresponding electrodes after being collected, and are not communicated with each other to cause electric leakage or short circuit due to transverse transmission, so that accurate doping alignment is not needed, the process is simple, the recombination is reduced, and the photoelectric conversion efficiency is improved. Meanwhile, the first carrier collecting region, the second carrier collecting region and the metal oxygen family compound layer are not contacted with each other to generate reverse pn junction. And the metal oxygen group compound layer has strong structure and performance adjustability, can realize lower transverse conductivity and stronger longitudinal conductivity, and has better thermal stability and wide process selection window.
Optionally, the blocking structure is a slot; and/or, the blocking structure is an insulator.
Optionally, the thickness of the blocking structure is greater than or equal to the thickness of the metal-oxygen group compound layer;
in a case where the blocking structure has a thickness greater than that of the metal chalcogenide layer, the blocking structure protrudes toward a backlight surface of the metal chalcogenide layer.
Optionally, a first transparent conductive film and/or a first work function adjusting layer are disposed between the first carrier conducting region and the first electrode; the first transparent conductive film and/or the first work function adjusting layer are/is positioned in a projection area of the first carrier conduction area;
and/or a second transparent conductive film and/or a second work function adjusting layer are/is arranged between the second carrier collecting region and the second electrode; the second transparent conductive film and/or the second work function adjusting layer are/is located in a projection area of the second carrier collecting area.
Optionally, the thicknesses of the first work function adjusting layer and the second work function adjusting layer are both 0.1-2 nm.
Optionally, in a case that a first transparent conductive thin film is disposed between the first carrier conducting region and the first electrode, the first electrode is disposed on a backlight surface of the first transparent conductive thin film in a form of a gate line;
and/or, under the condition that a second transparent conductive film is arranged between the second carrier collecting region and the second electrode, the second electrode is arranged on the backlight surface of the second transparent conductive film in the form of a grid line.
Optionally, the metal chalcogenide layer has a thickness of 1 to 600nm, more preferably 5 to 100 nm.
Optionally, the area of the projection of the first carrier collection region on the backlight surface of the silicon substrate accounts for 5% to 45% of the total area of the backlight surface of the silicon substrate.
Optionally, a passivation tunneling layer is disposed between the backlight surface of the silicon substrate and the metal oxygen group compound layer; the thickness of the passivation tunneling layer is 0.1nm-5nm, and the passivation tunneling layer is of a one-layer or multi-layer structure.
Optionally, the passivation tunneling layer is a dielectric layer.
Optionally, a backlight surface of the silicon substrate is a planar structure or a light trapping structure;
and/or the light facing surface of the silicon substrate is of a plane structure or a light trapping structure.
Optionally, the top view of the first carrier collection region is a dot or line pattern.
Optionally, at least one of a passivation layer, a front surface field effect layer, a front surface antireflection film layer, a scattering structure layer and a light-gathering structure layer is arranged on a light-facing surface of the silicon substrate;
and/or the presence of a gas in the gas,
and in the backlight surface of the metal oxygen group compound layer, a back antireflection film is arranged at the part except the first electrode and the second electrode.
According to the utility model discloses a second aspect still provides a full back electrode battery pack, include: any of the foregoing full back electrode solar cells.
The all-back-electrode cell assembly has the same or similar beneficial effects as the all-back-electrode solar cell.
Drawings
In order to more clearly illustrate the technical solution of the embodiments of the present invention, the drawings required to be used in the description of the embodiments of the present invention will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without inventive labor.
Fig. 1 shows a schematic structural diagram of a first full back electrode solar cell in an embodiment of the present invention;
fig. 2 shows a schematic structural diagram of a second full back electrode solar cell according to an embodiment of the present invention;
fig. 3 shows a schematic structural diagram of a third full back electrode solar cell according to an embodiment of the present invention;
fig. 4 shows a schematic structural diagram of a fourth full back electrode solar cell in an embodiment of the present invention;
fig. 5 shows a schematic structural diagram of a fifth full back electrode solar cell according to an embodiment of the present invention.
Description of the figure numbering:
the solar cell comprises a 1-silicon substrate, 2-a first part, 3-a passivation tunneling layer, 4-a metal oxygen group compound layer, 6-a first electrode, 5-a second electrode, 53-a second conductive film, 52-a second work function adjusting layer, 63-the first conductive film, 62-the first work function adjusting layer, 7-a front antireflection film layer and 8-a back antireflection film.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all embodiments of the present invention. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.
In the embodiment of the present invention, referring to fig. 1, fig. 1 shows a schematic structural diagram of a first full back electrode solar cell in the embodiment of the present invention. The full back electrode solar cell includes: a silicon substrate 1, a backlight surface of the silicon substrate 1 is divided into a second part and a first part 2. In fig. 1, the backlight surface of the silicon substrate 1 except the first portion 2 is the second portion. The first portion 2 is doped to form a first carrier-collection region. The first carrier collection region may enable collection and transport of the first carriers. It should be noted that the doping types of the first portion 2 and the first portion itself in the silicon substrate 1 are the same, but the doped elements may be the same or different, and the embodiment of the present invention is not limited thereto.
It is understood that the first carrier is selected from one of a majority carrier or a minority carrier and the second carrier is selected from the other of a majority carrier or a minority carrier. That is, when the first carrier is a majority carrier, the second carrier must be a minority carrier; when the second carrier is a majority carrier, the first carrier must be a minority carrier; note that, in the present invention, whether the majority-minority carriers or minority-minority carriers are electrons or holes is determined mainly by the doping type of the silicon substrate 1. If the doping type of the silicon substrate 1 is n-type, then many photons refer to electrons and few photons refer to holes in the full back electrode solar cell of the present invention. If the doping type of the silicon substrate 1 is p-type, then, in the full back electrode solar cell of the present invention, majority of electrons refer to holes, and minority of electrons refer to electrons.
Optionally, the doping concentration of the first carrier collecting region is greater than or equal to 1015cm-3And is greater than the doping concentration of the silicon substrate 1 of the second portion, so that the collection and transmission effects on the first carriers are better.
The metal oxygen group compound layer 4 is deposited on the backlight surface of the whole silicon substrate 1, and compared with the situation that other material layers are deposited on the backlight surface of the whole silicon substrate 1, the structure and performance adjustability is strong, the lower transverse conduction capability and the higher longitudinal conduction capability can be realized, the thermal stability is better, and the process selection window is wide.
The metal chalcogenide layer 4 has therein a blocking structure 9 that electrically divides the metal chalcogenide layer 4 into a first carrier conduction region and a second carrier collection region. The number of the blocking structures 9 is not particularly limited. The second carrier collecting region is located at a portion corresponding to the second portion of the backlight surface of the silicon substrate 1, and the second carrier collecting region can collect and transmit the second carrier. The first carrier conduction region is located at a portion corresponding to a first portion of the backlight surface of the silicon substrate 1, and the first carrier conduction region can realize transmission of first carriers.
The second carrier collecting region is correspondingly provided with a second electrode 5, and the second electrode 5 is used for conducting second carriers. The first carrier conduction region is correspondingly provided with a first electrode 6, and the first electrode 6 is used for conducting first carriers. It should be noted that an electrical insulation gap needs to be reserved between the second electrode 5 and the first electrode 6, and the electrical insulation gap is not less than the breakdown distance at the normal operating voltage. The second electrode 5 and the first electrode 6 can be manufactured by printing, deposition and other processes. The first electrode 6 and the second electrode 5 may be metal electrodes.
Referring to fig. 1, if the silicon substrate 1 is an n-type silicon substrate, the first carrier is an electron and the second carrier is a hole. The first carrier collecting region is the electron collecting region. The first carrier collecting region is of a doped structure, and can cause the n-type silicon substrate to bend downwards in the energy band of the first part 2, attract electrons to repel holes and play a role in selective collection of the electrons. The second carrier collecting region is a hole collecting region. The second carrier collecting region is represented by a hole selective contact material, the conduction band energy level of the material is close to the valence band energy level of the n-type silicon substrate, and the material can have interface negative charges or negative fixed defects, so that the energy band at the interface can be bent upwards to form an interface p-type layer, and the function of attracting holes and repelling electrons is achieved.
In the present invention, the conduction band energy level and the valence band energy level generally refer to the energy level of the material itself, that is, the energy level when the material exists alone, and do not refer to the actual energy level in the battery structure.
In the first carrier conduction region, the electron density and the hole density of the part are higher, so that the conduction band bottom energy level of the part is lower and is close to the conduction band bottom energy level of the first carrier collection region, and therefore electrons can directly enter the first carrier conduction region, corresponding to the first carrier collection region, in the metal oxygen group compound layer, and the transmission of the electrons is achieved.
If the silicon substrate 1 is an n-type silicon substrate, the second carrier is a hole if the first carrier is an electron. In the metal oxygen group compound layer 4, two parts electrically divided by the blocking structure 9 can respectively realize the collection of holes and the transmission of electrons, meanwhile, the material can be enabled to have lower transverse conductivity by adjusting crystallinity, crystalline phase and doping elements, the holes in the second carrier collecting region and the electrons in the first carrier conducting region are longitudinally transmitted into corresponding electrodes after different types of carriers are collected due to the electrical division of the blocking structure 9, the carriers cannot be mutually communicated due to transverse transmission to cause electric leakage or short circuit, therefore, the collecting ends of the carriers of different types do not need to be additionally electrically isolated, and reverse pn junctions cannot be generated due to mutual contact.
In the embodiment of the utility model, the first carrier collecting region adopts a local doping selective contact structure, and the metal oxygen group compound layer 4 adopts a deposited selective contact structure, so that compared with the traditional full-diffusion back contact structure, the metal oxygen group compound structure has the advantage of low body area recombination, and has few diffusion steps and relatively simple process; compared with a structure adopting amorphous silicon as back contact, the metal oxygen family compound layer 4 has stronger selectivity and higher thermal stability, and meanwhile, the requirement on equipment in the material deposition process is lower, and the safety is higher. The metal oxygen group compound layer 4 can fully cover the back of the battery, and the process flow is further simplified.
The part of the metal oxygen group compound layer 4 corresponding to the second part is adopted to form a second carrier collecting region, compared with an amorphous silicon material, the amorphous silicon material has stronger selectivity and longitudinal transmission capability, the second carrier collecting region and the longitudinal transmission capability are stronger, and lower contact resistance can be realized; meanwhile, the first carrier collecting region is matched with the local doping structure, the first carrier is transmitted through the band edge of the oxide material, a trans-energy level tunneling mechanism is not involved, the transmission obstruction of the first carrier is small, and lower contact resistance can be realized.
Optionally, the blocking structure is a slot; and/or, the blocking structure is an insulator. The blocking structure in the form has the advantages of good blocking effect and simple realization process. For example, the insulator may be provided by ion implantation.
Optionally, the thickness of the blocking structure is greater than or equal to that of the metal-oxygen group compound layer, so that the electrical blocking effect is good. For example, referring to fig. 1, the thickness of the blocking structure 9 is equal to the thickness of the metal chalcogenide layer 4. In the case where the thickness of the blocking structure is greater than the thickness of the metal chalcogenide layer, the blocking structure protrudes toward the backlight surface of the metal chalcogenide layer.
For example, referring to fig. 2, in addition to fig. 1, the thickness of the blocking structure 9 is larger than the thickness of the metal chalcogenide layer 4, and the blocking structure 9 protrudes toward the back surface of the metal chalcogenide layer 4.
Alternatively, the metal oxygroup compound layer 4 may have one or more layers, and as shown in fig. 1, the thickness d1 of the metal oxygroup compound layer 4 may be 1-600nm, and more preferably, d1 is 5-100nm, which facilitates the transmission and collection of the second carrier and the first carrier.
Alternatively, in the case where the silicon substrate is an n-type silicon substrate and the first carrier is a majority carrier, or in the case where the silicon substrate is a p-type silicon substrate and the first carrier is a minority carrier, the material of the metal oxide group compound layer 4 is selected from: at least one of the first materials. The first material is: an n-type metal oxide having a work function of 5eV or more, or a p-type metal oxide having a work function of 6eV or less. For both cases, the first carrier conduction region in the metal oxygroup compound layer 4 of the material facilitates the transmission of the first carriers, and the second carrier collection region in the metal oxygroup compound layer 4 of the material facilitates the transmission and collection of the second carriers.
Specifically, in the case where the silicon substrate is an n-type silicon substrate and the first carrier is an electron, or in the case where the silicon substrate is a p-type silicon substrate and the first carrier is an electron, the material of the metal oxide group compound layer 4 is selected from: at least one of the first materials described above.
Optionally, the first material is selected from: molybdenum oxide, tungsten oxide, vanadium oxide, niobium oxide, nickel oxide, mercury doped niobium oxide (e.g., Hg)2Nb2O7) Mercury doped tantalum oxide (e.g., Hg)2Ta2O7) At least one of (1). In the case where the silicon substrate is an n-type silicon substrate and the first carrier is an electron, or in the case where the silicon substrate is a p-type silicon substrate and the first carrier is an electron, the second carrier collection region in the metal-oxygen group compound layer 4 of the above material facilitates the transmission and collection of the second carrier, and the first carrier conduction region in the metal-oxygen group compound layer 4 of the above material facilitates the transmission of the first carrier.
Optionally, in a case where the silicon substrate is a p-type silicon substrate and the first carrier is a majority carrier, or in a case where the silicon substrate is an n-type silicon substrate and the first carrier is a minority carrier, the material of the metal-oxygen group compound layer is selected from at least one of the second materials; the second material is a metal chalcogenide with a work function greater than or equal to 3 eV. The first carrier conduction region in the metal chalcogenide layer 4 of the material facilitates the transmission of first carriers, and the second carrier collection region in the metal chalcogenide layer 4 of the material facilitates the transmission and collection of second carriers.
Specifically, in the case where the silicon substrate is a p-type silicon substrate and the first carrier is a hole, or in the case where the silicon substrate is an n-type silicon substrate and the first carrier is a hole, the material of the metal-oxygen group compound layer 4 is selected from: at least one of the above second materials.
Optionally, the second material is selected from: zinc oxide, tin oxide, titanium oxide, copper oxide, thallium oxide, cadmium sulfide, molybdenum sulfide, zinc sulfide, molybdenum selenide, copper selenide, niobium doped copper oxide (e.g., CuNb)3O8) Cadmium germanium oxide (e.g., Ce)0.8Gd0.2O2) Iridium zinc oxide (e.g., ZnIr)2O4) Cobalt calcium oxide (e.g. Ca)3Co4O9) At least one of (1). In the case that the silicon substrate is a p-type silicon substrate and the first carriers are holes, or in the case that the silicon substrate is an n-type silicon substrate and the first carriers are holes, the first carrier conduction region in the metal-oxygen group compound layer 4 of the material is favorable for the transmission of the first carriers, and the second carrier collection region in the metal-oxygen group compound layer 4 of the material is favorable for the transmission and collection of the second carriers.
Optionally, the metal chalcogen compound contains a doping element selected from: at least one of halogen elements, transition metal elements, alkali metal elements, rare earth elements, group III elements, group IV elements and group V elements. The first carrier conduction region in the metal chalcogenide layer 4 of the above material facilitates the transmission of the first carriers, and the second carrier collection region in the metal chalcogenide layer 4 of the above material facilitates the transmission and collection of the second carriers.
Optionally, the transverse conductivity of the metal-oxygen group compound layer 4 is 1.0 × 10 or less-3S/cm, transverse resistance greater than or equal to 1.0 x 103Omega/cm, thereby improving the longitudinal conductivity of the metal-oxygen compound layer 4 and avoiding transverse electric leakage, and further having good barrier effect on transverse current. The reduction of the lateral conductivity can be achieved by adjusting the material structure, such as crystallinity, crystalline phase or doping.
Alternatively, in the case where the silicon substrate is a p-type silicon substrate and the first carrier is a majority carrier, or in the case where the silicon substrate is an n-type silicon substrate and the first carrier is a majority carrierIn the case of minority carriers, the second carrier collecting region in the metal-oxygen group compound layer 4 is used for collecting and transmitting second carrier electrons, and the first carrier conducting region in the metal-oxygen group compound layer 4 is used for transmitting first carrier holes. The fixed positive charge density at the interface or inside of the metal chalcogenide layer 4 is 10 or more11cm-2And/or the acceptor defect density at the interface or inside of the metal chalcogenide layer 4 is 10 or more11cm-2And/or the interface or internal limiting charge density of the metal chalcogenide layer 4 is greater than or equal to 1011cm-2. The first carrier conduction region in the metal chalcogenide layer 4 of the material facilitates the transmission of first carriers, and the second carrier collection region in the metal chalcogenide layer 4 of the material facilitates the transmission and collection of second carriers.
Optionally, in a case where the silicon substrate is an n-type silicon substrate and the first carrier is a majority carrier, or in a case where the silicon substrate is a p-type silicon substrate and the first carrier is a minority carrier, the second carrier collecting region in the metal oxide layer 4 is configured to collect and transport holes of the second carrier, and the first carrier conducting region in the metal oxide layer 4 is configured to transport electrons of the first carrier. The fixed negative charge density at the interface or inside of the metal chalcogenide layer 4 is 10 or more12cm-2And/or the donor defect density at the interface or inside of the metal chalcogenide layer 4 is greater than or equal to 1012cm-2And/or the interface or internal limiting charge density of the metal chalcogenide layer 4 is greater than or equal to 1012cm-2. The first carrier conduction region in the metal chalcogenide layer 4 of the material facilitates the transmission of first carriers, and the second carrier collection region in the metal chalcogenide layer 4 of the material facilitates the transmission and collection of second carriers.
Optionally, the average light transmittance of the metal oxygen group compound layer 4 in the visible light band is greater than or equal to 70%, and further, the shielding of the metal oxygen group compound layer 4 on visible light is less, which is beneficial to improving the photoelectric conversion efficiency.
Optionally, the area of the projection of the first carrier collecting region on the backlight surface of the silicon substrate 1 accounts for 5% to 45% of the total area of the backlight surface of the silicon substrate, and under the area proportion, the first carrier collecting and transmitting effect is good, and meanwhile, the collecting and transmitting of the second carrier cannot be influenced.
Alternatively, the top view of the first carrier-collection region may be a dot-like or line-like pattern, such as a circle or an ellipse. A line pattern such as a rectangle or a polygon, etc. The top view of the first carrier collecting region is in a dot or line pattern, and the doping of the first part is simple.
Optionally, the backlight surface of the silicon substrate 1 is of a planar structure or a light trapping structure, and the light facing surface of the metal-oxygen group compound layer 4 is adapted to the backlight surface of the silicon substrate 1. And/or the light-facing surface of the silicon substrate 1 is of a planar structure or a light trapping structure. For the light trapping structure, the optical path can be increased, and the photoelectric conversion efficiency is improved. The light trapping structure can be a suede, an inverted pyramid, a nano light trapping structure and the like.
Optionally, the light-facing surface of the silicon substrate may further be provided with at least one of a passivation layer, a front surface field effect layer, a front surface antireflection film layer, a scattering structure layer, and a light-gathering structure layer. And/or in the backlight surface of the metal oxygen group compound layer, the second electrode and the part except the first electrode are provided with a back antireflection film to realize passivation, optical improvement and the like.
For example, referring to fig. 3, fig. 3 is a schematic structural diagram of a 3 rd full back electrode solar cell in an embodiment of the present invention. On the basis of fig. 1, fig. 3 may be 7 a front antireflection film layer, and 8 a back antireflection film layer.
Optionally, a passivation tunneling layer is disposed between the backlight surface of the silicon substrate and the metal-oxygen compound layer. The passivation tunneling layer can be of one-layer or multi-layer structure, and the thickness of the passivation tunneling layer is 0.1nm-5 nm. The passivation tunneling layer plays a good role in surface passivation and can reduce the recombination of current at an interface.
For example, referring to fig. 4, fig. 4 shows a schematic structural diagram of a fifth full back electrode solar cell according to an embodiment of the present invention. On the basis of the above fig. 3, a passivation tunneling layer 3 is disposed between the backlight surface of the silicon substrate 1 and the metal oxygen group compound layer 4, and the thickness d2 of the passivation tunneling layer 3 is 0.1nm-5 nm.
Optionally, the material of the passivation tunneling layer is selected from: at least one of silicon oxide, silicon nitride, silicon oxynitride, and silicon halide. The surface of the passivation tunneling layer of the material has better chemical passivation effect. The passivation tunneling layer can be formed separately, for example, by an in-situ reaction process such as a wet thermal oxidation process or a dry thermal oxidation process, or by a chemical vapor deposition process or a physical vapor deposition process. Or as a passivation tunneling layer by a process integrated with the metal-oxygen compound layer, such as an interfacial silicon oxide layer formed during the growth of the metal-oxygen compound or during post-annealing. It should be noted that if the passivation tunneling layer is a material not containing silicon, it may include a chemical transition layer with silicon material.
Optionally, the material of the passivation tunneling layer may be a dielectric layer, and the dielectric constant is greater than 2. The dielectric layer can be polarized to insulating material, and the material of passivation tunneling layer can the dielectric layer, and the dielectric constant is greater than 2, not only plays good surface chemical passivation effect, moreover, has good field passivation effect, can play good blocking effect to horizontal electrically conductive.
Optionally, the breakdown voltage of the passivation tunneling layer is greater than or equal to 3MV/cm, the surface passivation effect is good, and a good blocking effect on transverse conduction is achieved.
Optionally, the material of the passivation tunneling layer is selected from: silicon oxide (e.g. SiO)x) Silicon nitride (e.g., SiN)x) Fluorinated silicon (e.g., SiF)4) Fluorine silicon oxide (e.g., SiOF), silicon oxycarbide (e.g., SiOC), aluminum oxide (e.g., Al)2O3) Aluminum fluoride (e.g., AlF)x) And aluminum oxynitride (such as AlON). The passivation tunneling layer of the material has good surface passivation effect and plays a good role in blocking transverse conduction. It should be noted that x in the chemical formula is a suitable value that can be selected by those skilled in the art according to actual situations.
Optionally, a first transparent conductive film and/or a first work function adjusting layer is disposed between the first carrier conducting region and the first electrode. That is, the first conductive thin film, or the first work function adjusting layer, or both may be provided between the first carrier conducting region and the first electrode. The first transparent conductive film and/or the first work function adjusting layer are/is located in a projection region of the first carrier conduction region. In both cases, the first transparent conductive film may be located on a backlight surface or a light-facing surface of the first work function adjustment layer. A projection of the first electrode may be located within a projection of the first conductive film and/or the first work function adjusting layer.
And/or a second transparent conductive film and/or a second work function adjusting layer are/is arranged between the second carrier collecting region and the second electrode. That is, the second conductive film, or the second work function adjusting layer, or both of them may be provided between the second carrier collecting region and the second electrode. The second transparent conductive film and/or the second work function adjusting layer are/is located in the projection area of the second carrier collecting area. In both cases, the second transparent conductive film may be located on a backlight surface or a light-facing surface of the second work function adjustment layer. A projection of the second electrode may be located within a projection of the second conductive film and/or the second work function adjusting layer.
The first conductive film and the second conductive film can play a role in assisting carrier transmission, and are transparent, so that the photoelectric conversion efficiency can be further improved. The first work function adjusting layer and the second work function adjusting layer play a role in reducing contact resistance.
Fig. 5 shows a schematic structural diagram of a fifth full back electrode solar cell according to an embodiment of the present invention. As with fig. 5, a first conductive film 63 and a first work function adjusting layer 62 are provided between the first carrier conducting region and the first electrode 6. The first conductive film 63 is located on a backlight surface of the first work function adjusting layer 62. A second conductive film 53 and a second work function adjusting layer 52 are provided between the second carrier collecting region and the second electrode 5. The second conductive film 53 is located on the light-facing surface of the second work function adjusting layer 52.
Alternatively, as shown in fig. 5, the thickness d4 of the first work function adjusting layer 62 and the thickness d3 of the second work function adjusting layer 52 are both 0.1 to 5 nm. This thickness range can reduce the contact resistance to a greater extent.
Optionally, the first transparent conductive film is formed by combining or mixing a transparent conductive material and a work function adjusting material. And/or the second transparent conductive film is formed by compounding or mixing a transparent conductive material and a work function adjusting material. That is, the first conductive film and the second conductive film can not only play a role of assisting carrier transmission, but also transmit light, thereby further improving photoelectric conversion efficiency and reducing contact resistance or longitudinal resistance.
Optionally, under the condition that the first transparent conductive film is arranged between the first carrier conduction region and the first electrode, the first electrode is arranged on a backlight surface of the first transparent conductive film in a grid line mode, so that the back surface is fully utilized to transmit light, and the photoelectric conversion efficiency can be further improved.
And/or under the condition that a second transparent conductive film is arranged between the second carrier collecting region and the second electrode, the second electrode is arranged on the backlight surface of the second transparent conductive film in a grid line mode, the back surface is fully utilized to transmit light, and the photoelectric conversion efficiency can be further improved.
Optionally, the materials of the first conductive film and the second conductive film are independently selected from: at least one of zinc oxide, aluminum-doped zinc oxide, tin oxide, indium-doped tin oxide, and indium-gallium-doped tin oxide. The first conductive film and the second conductive film of the material have better carrier transmission performance, and can further improve the photoelectric conversion efficiency.
Optionally, the work functions of the first work function adjusting layer and the second work function adjusting layer are both 1eV to 5.5eV, so that the contact resistance can be further reduced.
Optionally, the materials of the first work function adjusting layer and the second work function adjusting layer, the first transparent conductive film, and/or the work function adjusting materials in the second transparent conductive film may be independently selected from: at least one of an alkali metal, a transition metal, an alkali metal halide or a transition metal halide can further reduce the contact resistance.
Optionally, the materials of the first work function adjusting layer and the second work function adjusting layer, and the first transparent conductive film and/or the work function adjusting material in the second transparent conductive film may be independently selected from: ca. Mg, Ba, LiFx、KFx、MgFx、BaClxAnd the like. Wherein, x in the chemical formula can be selected by a person skilled in the art according to actual conditions.
Optionally, the work function of the work function adjusting material in the first transparent conductive film and/or the second transparent conductive film is 1eV to 5.5eV, which can further reduce the contact resistance.
The utility model discloses embodiment mode still provides a full back electrode battery pack, include: any of the foregoing full back electrode solar cells. The silicon substrate, the first carrier collecting region, the second carrier collecting region, the first carrier conducting region, the second electrode and the first electrode in the component can specifically refer to the related descriptions, and can achieve the same or similar beneficial effects, and the details are not repeated herein to avoid repetition.
The embodiments of the present invention have been described with reference to the accompanying drawings, but the present invention is not limited to the above-mentioned embodiments, which are only illustrative and not restrictive, and those skilled in the art can make many forms without departing from the spirit and scope of the present invention, and all of them fall within the protection scope of the present invention.
Claims (14)
1. An all back electrode solar cell, comprising: the backlight surface of the silicon substrate is divided into a first part and a second part; the first portion is doped to form a first carrier-collection region;
a metal-oxygen-group compound layer deposited on a backlight surface of the entire silicon substrate, in which a blocking structure electrically dividing the metal-oxygen-group compound layer into a first carrier conduction region and a second carrier collection region is provided; wherein the first carrier conduction region corresponds to the first portion; the second carrier-collection region corresponds to the second portion;
a first electrode correspondingly disposed on the first carrier conduction region;
and a second electrode disposed correspondingly to the second carrier collecting region.
2. The all back electrode solar cell in accordance with claim 1, wherein the blocking structure is a trench; and/or, the blocking structure is an insulator.
3. The all back electrode solar cell according to claim 1 or 2, wherein a thickness of the blocking structure is greater than or equal to a thickness of the metal chalcogenide layer;
in a case where the blocking structure has a thickness greater than that of the metal chalcogenide layer, the blocking structure protrudes toward a backlight surface of the metal chalcogenide layer.
4. The all-back-electrode solar cell according to claim 1 or 2, wherein a first transparent conductive thin film and/or a first work function adjusting layer is provided between the first carrier conducting region and the first electrode; the first transparent conductive film and/or the first work function adjusting layer are/is positioned in a projection area of the first carrier conduction area;
and/or a second transparent conductive film and/or a second work function adjusting layer are/is arranged between the second carrier collecting region and the second electrode; the second transparent conductive film and/or the second work function adjusting layer are/is located in a projection area of the second carrier collecting area.
5. The all-back-electrode solar cell according to claim 4, wherein the first work function adjusting layer and the second work function adjusting layer each have a thickness of 0.1 to 2 nm.
6. The all-back-electrode solar cell according to claim 4, wherein in a case where a first transparent conductive thin film is provided between the first carrier conducting region and the first electrode, the first electrode is provided in the form of a grid line on a backlight surface of the first transparent conductive thin film;
and/or, under the condition that a second transparent conductive film is arranged between the second carrier collecting region and the second electrode, the second electrode is arranged on the backlight surface of the second transparent conductive film in the form of a grid line.
7. The all back electrode solar cell according to claim 1 or 2, wherein the thickness of the metal chalcogenide layer is 1 to 600 nm.
8. The all-back-electrode solar cell according to claim 1 or 2, wherein the area of the projection of the first carrier-collection region on the back-light surface of the silicon substrate is 5% to 45% of the total area of the back-light surface of the silicon substrate.
9. The all-back-electrode solar cell according to claim 1 or 2, wherein a passivation tunneling layer is disposed between the backlight surface of the silicon substrate and the metal-oxygen group compound layer; the thickness of the passivation tunneling layer is 0.1nm-5nm, and the passivation tunneling layer is of a one-layer or multi-layer structure.
10. The all back electrode solar cell of claim 9, wherein the passivation tunneling layer is a dielectric layer.
11. The solar cell according to claim 1 or 2, wherein the backlight surface of the silicon substrate is a planar structure or a light trapping structure;
and/or the light facing surface of the silicon substrate is of a plane structure or a light trapping structure.
12. The all back electrode solar cell of claim 1 or 2, wherein the top view of the first carrier collection region is in a dotted or linear pattern.
13. The solar cell as claimed in claim 1 or 2, wherein the light-facing surface of the silicon substrate is provided with at least one of a passivation layer, a front-side field effect layer, a front-side antireflection film layer, a scattering structure layer and a light-gathering structure layer;
and/or the presence of a gas in the gas,
and in the backlight surface of the metal oxygen group compound layer, a back antireflection film is arranged at the part except the first electrode and the second electrode.
14. An all-back electrode cell assembly, comprising: the all back electrode solar cell of any one of claims 1 to 13.
Priority Applications (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202021108338.6U CN212676291U (en) | 2020-06-15 | 2020-06-15 | Full back electrode solar cell and full back electrode cell assembly |
| AU2020453832A AU2020453832A1 (en) | 2020-06-15 | 2020-12-10 | Back contact solar cell and production method, and back contact battery assembly |
| EP20941464.8A EP4167300A1 (en) | 2020-06-15 | 2020-12-10 | Back contact solar cell and production method, and back contact battery assembly |
| PCT/CN2020/135400 WO2021253751A1 (en) | 2020-06-15 | 2020-12-10 | Back contact solar cell and production method, and back contact battery assembly |
| US18/001,821 US20230238463A1 (en) | 2020-06-15 | 2020-12-10 | Back contact solar cell and production method, and back contact battery assembly |
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| CN202021108338.6U CN212676291U (en) | 2020-06-15 | 2020-06-15 | Full back electrode solar cell and full back electrode cell assembly |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113345969A (en) * | 2021-04-28 | 2021-09-03 | 中国科学院宁波材料技术与工程研究所 | Passivated contact structure, preparation method and application thereof |
| CN114937707A (en) * | 2022-05-19 | 2022-08-23 | 苏州大学 | Electron passivation contact structure and crystalline silicon solar cell |
| CN117727822A (en) * | 2024-02-07 | 2024-03-19 | 浙江晶科能源有限公司 | Solar cell, method for manufacturing solar cell, and photovoltaic module |
-
2020
- 2020-06-15 CN CN202021108338.6U patent/CN212676291U/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113345969A (en) * | 2021-04-28 | 2021-09-03 | 中国科学院宁波材料技术与工程研究所 | Passivated contact structure, preparation method and application thereof |
| CN114937707A (en) * | 2022-05-19 | 2022-08-23 | 苏州大学 | Electron passivation contact structure and crystalline silicon solar cell |
| CN117727822A (en) * | 2024-02-07 | 2024-03-19 | 浙江晶科能源有限公司 | Solar cell, method for manufacturing solar cell, and photovoltaic module |
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