CN212676273U

CN212676273U - Field effect transistor with same grid source doping and cellular structure thereof

Info

Publication number: CN212676273U
Application number: CN202020593696.4U
Authority: CN
Inventors: 黄兴; 陈欣璐; 陈然
Original assignee: Pn Junction Semiconductor Hangzhou Co ltd
Current assignee: Pn Junction Semiconductor Hangzhou Co ltd
Priority date: 2020-04-20
Filing date: 2020-04-20
Publication date: 2021-03-09
Anticipated expiration: 2030-04-20

Abstract

The utility model discloses a field effect transistor with same grid source doping and cell structure thereof. Wherein field effect transistor cell structure with the same gate-source doping includes: the silicon carbide substrate is made of a silicon carbide substrate material, and the doping type of the silicon carbide substrate material is a first conduction type; a first conductive type semiconductor epitaxial layer and a first electrode are respectively arranged on the front surface and the back surface of the silicon carbide substrate; the semiconductor epitaxial layer of the first conduction type is sequentially provided with a second conduction type suspension region, a first conduction type grid injection region and a first conduction type source injection region, a grid is arranged on the grid injection region, a source is arranged on the source injection region, an inter-electrode medium is arranged between the grid injection region and the source injection region, and the inter-electrode medium is used for isolating the grid from the source.

Description

Field effect transistor with same grid source doping and cellular structure thereof

Technical Field

The utility model belongs to the technical field of the semiconductor, concretely relates to field effect transistor and cellular structure with same grid source doping.

Background

With the development and maturation of the material technology, the wide bandgap characteristic of the SiC material enables the SiC material to have higher temperature characteristic and voltage resistance characteristic, and the limitation of Si-based devices can be broken through. Because of SiC/SiO₂The performance and reliability of the interface still need to be further improved, and the structure of a Junction Field Effect Transistor (JFET) device is receiving wide attention. SiC JFET avoids SiC/SiO₂The problem caused by interface defect is that the cell size is easier to reduce, and the lower on resistance is caused. Due to SiO₂More interface states can be excited at high temperature, so that the SiC JFET device can maximally explore the high-temperature and high-pressure characteristics of the SiC material.

The conventional SiC JFET is controlled by a PN junction, and carriers flow out of a source electrode of a device, flow into a drift region of the device through a long and narrow channel region and are finally collected by a drain electrode of the device. The channel of the device is controlled by two PN junctions between the gate and the source, thereby controlling the turn-off and turn-on of the device. However, the P-type gate of the conventional JFET brings many adverse effects on the device application level: first, when the device is on, to avoid the PN junction from turning on, the device gate bias Vgs cannot exceed the PN junction forward turn-on voltage V_F0(taking silicon carbide as an example, V_F02.6V, Vgs<V_F0) (ii) a Meanwhile, if the device is in a normally-on type, when the gate is conducted under zero bias, the built-in potential formed between the P-type gate and the N-type channel (hereinafter referred to as "gate built-in potential") depletes the channel to a certain extent, resulting in higher channel resistance; when the device is in a high-current (near saturation region) operation, the built-in potential of the gate causes the channel to enter a pinch-off state prematurely, the current is saturated prematurely, and the conduction loss in the operation is too high.

SUMMERY OF THE UTILITY MODEL

In view of the above-mentioned technical problems, the present invention is directed to providing a field effect transistor with the same gate source doping and a cell structure thereof.

In order to solve the technical problem, the utility model discloses a following technical scheme:

the utility model discloses a first aspect provides a field effect transistor cell structure with same grid source doping, include:

a silicon carbide substrate material doped with a first conductivity type,

a first conductive type semiconductor epitaxial layer and a first electrode are respectively arranged on the front surface and the back surface of the silicon carbide substrate;

the semiconductor epitaxial layer of the first conduction type is sequentially provided with a second conduction type suspension region, a first conduction type grid injection region and a first conduction type source injection region, a grid is arranged on the grid injection region, a source is arranged on the source injection region, an inter-electrode medium is arranged between the grid injection region and the source injection region, and the inter-electrode medium is used for isolating the grid from the source.

Preferably, the thickness of the first conductive type semiconductor epitaxial layer is 5-250 um, and the doping concentration is 1 x 10¹⁴cm^-3-5×10¹⁸cm^-3。

Preferably, the gate implant region of one side of the cell is connected to the gate, and the gate implant region and the source implant region of the other side of the cell are commonly connected to the source.

Preferably, the doping of the first conductivity type and the second conductivity type is 1 × 10¹⁴cm^-3-2×10²¹cm^-3Uniform or non-uniform doping.

Preferably, the first conductivity type is N-type, and the second conductivity type is P-type.

Preferably, the first conductivity type is P-type, and the second conductivity type is N-type.

The utility model discloses the second aspect provides a field effect transistor with same grid source doping, including a plurality of as above cell structure and field limiting ring terminal knot, and when making the knot terminal, the sculpture pours into the second conductive type suspended region of knot terminal and cell structure into and uses the same piece photoetching mask version sculpture simultaneously and pours into.

The utility model discloses the third aspect provides a field effect transistor with same grid source doping, including a plurality of as above cell structure and knot terminal extension and add field limit ring knot terminal, and when the preparation knot terminal, the sculpture pours into the second conductive type suspended region of knot terminal and cell structure and uses the same piece photoetching mask version etching simultaneously and pours into.

Adopt the utility model discloses following beneficial effect has:

(1) introducing a gate with a first conductivity type and a suspension region with a second conductivity type surrounding the gate on the basis of a conventional JFET to control a device channel can increase the forward bias voltage of the device gate, so that Vgs can be biased at a position larger than the forward turn-on voltage of a pn junction.

(2) When Vgs is 0V, the device on-resistance is lower because there is no built-in potential induced reverse bias of the PN junction at the channel.

(3) Under the condition of high-current conduction, the device enters a saturation state to conduct larger current.

(4) One gate is connected to the source so that the structure can reduce Cgd, thereby reducing switching losses.

Drawings

FIG. 1 is a schematic diagram of a gate and a source formed in a first embodiment of the structure;

FIG. 2 is a schematic structural diagram illustrating the formation of a channel implantation region according to a second embodiment;

FIG. 3 is a schematic diagram of a gate to source configuration in a third embodiment;

FIG. 4 is a schematic structural diagram of a fourth structural embodiment in which an active region of a cell structure and an end terminal are etched and implanted simultaneously;

FIG. 5 is a schematic structural diagram of a fifth example of a structure in which an active region of a cell structure is simultaneously etched and implanted with an etch implant junction terminal.

Fig. 6 is a schematic structural view of a space charge region between a channel implant region and a second conductivity type floating region being closed when the device is turned off;

FIG. 7 is a schematic diagram of a structure in which space charge regions are separated when the device is turned on;

FIG. 8 is a comparison of the improvement in gate-applied voltage compared to a conventional JFET device;

figure 9 is a graph comparing the improvement in saturation current compared to a conventional JFET device.

Detailed Description

The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, not all, of the embodiments of the present invention. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.

Structural example 1

The embodiment of the utility model provides a field effect transistor cellular structure with same grid source doping, see fig. 1, include:

a silicon carbide substrate 001, the silicon carbide substrate material having a doping type of a first conductivity type,

a first conductivity type semiconductor epitaxial layer 002 and a first electrode 003 (i.e., a drain electrode in the drawing) are provided on the front surface and the back surface of the silicon carbide substrate 001, respectively;

the second conductive type suspension region 005, the first conductive type gate injection region 006 and the first conductive type source injection region 007 are sequentially arranged on the first conductive type semiconductor epitaxial layer 002, the gate 008 is arranged on the gate injection region 006, the source 009 is arranged on the source injection region, an inter-electrode medium 010 is arranged between the gate injection region 006 and the source injection region 007, and the inter-electrode medium 010 is used for isolating the gate 008 and the source 009.

In the preferred embodiment, the first conductive type semiconductor epitaxial layer 002 has a thickness of 5-250 um and a doping concentration of 1 × 10¹⁴cm^-3-5×10¹⁸cm^-3。

The embodiment of the utility model provides an in passingThe system JFET is based on the introduction of a gate having a first conductivity type and a floating region of a second conductivity type surrounding the gate to control a device channel. The forward bias of the device gate can be increased so that Vgs can be biased at a level greater than the pn junction forward turn-on voltage (in the case of silicon carbide, V can be used_GS20V). Meanwhile, when Vgs is 0V, the on-resistance of the device is lower because there is no reverse bias introduced by built-in potential of the PN junction at the channel. Under the condition of high-current conduction, the device enters a saturation state to conduct larger current. That is, compared to the conventional JFET device, the present invention improves the voltage and saturation current that can be applied to the gate, as shown in fig. 8 and 9.

In a preferred embodiment, the doping of the first conductivity type and the second conductivity type is 1 × 10¹⁴cm^-3-2×10²¹cm^-3Uniform or non-uniform doping.

Structural example 2

A field effect transistor cell structure with the same gate-source doping prepared by method example 2, referring to fig. 2, on the basis of structure example 1, a channel implantation region 004 is formed by adding at least one tilt implantation on the epitaxial layer.

By adjusting the doping concentration of the channel implant region 004 and the second conductivity type suspension region 005, the threshold voltage of the JFET device can be adjusted. Referring to fig. 6, when the device is turned off, a space charge region between the channel injection region 004 and the second conductive-type floating region 005 is closed; referring to fig. 7, when the device is turned on, the space charge zones are separated.

Structural example 3

On the basis of structural embodiment 1 and structural embodiment 2, referring to fig. 3, the gate implant region 006 on one side of the cell is connected to the gate 008, and the gate implant region 006 and the source implant region 007 on the other side of the cell are commonly connected to the source 009, so that the structure can reduce Cgd, thereby reducing switching loss.

Structural example 4

Referring to fig. 4, an embodiment of the present invention provides a field effect transistor with the same gate source doping, which includes a plurality of cell structures and field limiting ring terminal junctions as in any one of structural embodiments 1 to 3, and when fabricating the junction terminal, the junction terminal is etched and implanted using the same lithographic mask as the second conductive type floating region of the cell structure.

Structural example 5

Referring to fig. 5, a field effect transistor with the same gate-source doping includes a plurality of cell structures as in any one of structural embodiments 1 to 3, and a junction terminal extension and a field-limiting ring junction terminal, and when the junction terminal is fabricated, the junction terminal and a second conductive type floating region of the cell structure are etched and implanted using the same lithographic mask at the same time.

It is to be understood that the exemplary embodiments described herein are illustrative and not restrictive. While one or more embodiments of the present invention have been illustrated in the accompanying drawings, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims

1. A field effect transistor cell structure having a same gate-source doping, comprising:

a silicon carbide substrate (001) of a doping type of a first conductivity type,

a first conductive type semiconductor epitaxial layer (002) and a first electrode (003) are respectively arranged on the front surface and the back surface of a silicon carbide substrate (001);

the semiconductor epitaxial layer (002) is sequentially provided with a second conductive type suspension region (005), a first conductive type grid injection region (006) and a first conductive type source injection region (007), the grid electrode (008) is arranged on the grid injection region (006), the source electrode (009) is arranged on the source injection region, an inter-electrode medium (010) is arranged between the grid injection region (006) and the source injection region (007), and the inter-electrode medium (010) is used for isolating the grid electrode (008) and the source electrode (009).

2. The field effect transistor cell structure of claim 1, wherein said first conductivity type semiconductor epitaxial layer (002) is 5-250 um thick.

3. The cell structure of claim 1, wherein the gate implant region (006) on one side of the cell is connected to the gate (008) and the gate implant region (006) and the source implant region (007) on the other side of the cell are commonly connected to the source (009).

4. The field effect transistor cell structure of claim 1, wherein said first conductivity type is N-type and said second conductivity type is P-type.

5. The field effect transistor cell structure of claim 1, wherein said first conductivity type is P-type and said second conductivity type is N-type.

6. A field effect transistor with the same gate source doping comprising a plurality of cell structures according to any of claims 1 to 5 and field limiting ring junction terminals, and wherein the etching of the implanted junction terminals and the second conductivity type of the suspended region of the cell structures is performed simultaneously using the same lithographic reticle etching implant during the fabrication of the junction terminals.

7. A field effect transistor with identical gate source doping comprising a plurality of cell structures according to any of claims 1 to 5 and junction termination extensions and field limited ring junction terminations, and wherein the etch implant junction terminations are implanted simultaneously with the second conductivity type suspended regions of the cell structures using the same lithographic reticle etch during fabrication of the junction terminations.