CN212588560U - A chip frame, packaged chip, driving system and lighting device - Google Patents

A chip frame, packaged chip, driving system and lighting device Download PDF

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CN212588560U
CN212588560U CN202021035688.4U CN202021035688U CN212588560U CN 212588560 U CN212588560 U CN 212588560U CN 202021035688 U CN202021035688 U CN 202021035688U CN 212588560 U CN212588560 U CN 212588560U
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base island
rectifier
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邵蕴奇
徐勇
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Shanghai Looall Electronics Co ltd
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Abstract

本实用新型公开了一种芯片框架、封装芯片、驱动系统及照明装置,属于芯片设计领域。针对现有技术中存在的现有单基岛无法同时封装整流器和芯片,双基岛稳定性差和形状过于狭长的问题,本实用新型提供了一种芯片框架、封装芯片、驱动系统及照明装置,本方案通过双基岛设置的芯片框架,通过一体成型的筋爪可以保证芯片的稳定性,通过在不同的基岛上设置整流桥的不同部分,将整流器和芯片同时集成到芯片封装上,可以保证整体的应用电路尺寸大大减小,且双基岛的设置可以保证整流桥的性能不受影响,连线方式简单,通过对负载进行不同连接,来针对不同情况下的负载形式进行驱动,实现对负载功率的控制。

Figure 202021035688

The utility model discloses a chip frame, a packaged chip, a driving system and a lighting device, which belong to the field of chip design. Aiming at the problems in the prior art that the existing single-base island cannot encapsulate the rectifier and the chip at the same time, the double-base island has poor stability and the shape is too narrow, the utility model provides a chip frame, a packaged chip, a driving system and a lighting device, In this solution, the chip frame set on the double base islands and the integrated claws can ensure the stability of the chip. By setting different parts of the rectifier bridge on different base islands, the rectifier and the chip are integrated into the chip package at the same time. It ensures that the overall application circuit size is greatly reduced, and the setting of the double-base island can ensure that the performance of the rectifier bridge is not affected, and the connection method is simple. Control of load power.

Figure 202021035688

Description

一种芯片框架、封装芯片、驱动系统及照明装置A chip frame, packaged chip, driving system and lighting device

本申请要求申请日为2019年11月13日的中国专利申请CN201911107801.7的优先权。This application claims the priority of Chinese patent application CN201911107801.7 with an application date of November 13, 2019.

本申请要求申请日为2020年1月2日的中国专利申请CN202010002650.5的优先权。This application claims the priority of Chinese patent application CN202010002650.5 with an application date of January 2, 2020.

本申请引用上述中国专利申请的全文。This application cites the full text of the above Chinese patent application.

技术领域technical field

本实用新型涉及芯片设计领域,更具体地说,涉及一种芯片框架、封装芯片、驱动系统及照明装置。The utility model relates to the field of chip design, in particular to a chip frame, a packaged chip, a driving system and a lighting device.

背景技术Background technique

当前LED照明使用线性恒流驱动电路为LED器件提供稳定供电电流,其工作原理是:当供电电压改变时,相应地改变线性恒流驱动电路输出的电压,维持LED器件上的导通压降不变,从而达到电流稳定的效果。The current LED lighting uses a linear constant current drive circuit to provide a stable supply current for the LED device. Its working principle is: when the power supply voltage changes, the output voltage of the linear constant current drive circuit is correspondingly changed, and the conduction voltage drop on the LED device is maintained. change, so as to achieve the effect of current stability.

如图1所示,交流电压AC经整流器输出整流电压为LED单元和芯片供电,LED单元和芯片串联后并联在整流器的输出两端,所述芯片内部的电路为线性恒流驱动电路,当交流电压AC波动升高时,芯片两端的电压随之升高,芯片本身的功耗也随之升高,产生较大的热量,因而,该芯片通常采用带有散热片的封装形式,例如ESOP-8,该芯片具有一个金属基岛,其底部裸露的金属部分能够将芯片的热量传递到电路板上;整流器通常为四个二极管组成的全桥整流,具有四个引脚。随着LED装置的愈来愈小型化,通常需要将整流器、芯片和LED单元组装在一个紧凑的电路板上,因而有必要设法将整流器和芯片的体积尽可能的减小。传统的ESOP-8框架具有一个基岛,不能将处于不同电位的整流器和芯片集成封装在一起。As shown in Figure 1, the alternating voltage AC is outputted by the rectifier to supply power to the LED unit and the chip. The LED unit and the chip are connected in series and then connected in parallel to the output ends of the rectifier. The circuit inside the chip is a linear constant current drive circuit. When the AC voltage fluctuates, the voltage across the chip increases, and the power consumption of the chip itself also increases, which generates a large amount of heat. Therefore, the chip is usually packaged with a heat sink, such as ESOP- 8. The chip has a metal base island, and the exposed metal part at the bottom can transfer the heat of the chip to the circuit board; the rectifier is usually a full-bridge rectifier composed of four diodes, with four pins. With the increasingly miniaturization of LED devices, it is usually necessary to assemble the rectifier, the chip and the LED unit on a compact circuit board, so it is necessary to try to reduce the size of the rectifier and the chip as much as possible. The traditional ESOP-8 framework has a base island and cannot integrate rectifiers and chips at different potentials together.

现有技术也有使用两个基岛的框架结构,如中国专利申请,申请号201920418685.X,公开日2019年10月25日,公开了一种ESOP8双基岛封装框架,其可以满足多个芯片或不同极性的芯片共同作用的要求,可提高使用的灵活性、降低成本,避免集成电路板结构复杂、产品整体性能差的问题出现,其包括基岛、引脚,所述引脚和基岛上的芯片连接,引脚通过塑封料封装,所述引脚包括八个:所述八个引脚分为两组分布于框架的上侧、下侧,其特征在于,所述基岛包括两个:第一基岛、第二基岛,所述第一基岛、第二基岛以所述框架的横向中心线为轴对称布置,上侧的引脚和下侧的引脚分别与其邻近的基岛上的所述芯片连接。当时其仅仅是将一个基岛拆分成两个基岛,由于原先一个基岛是通过两端的筋爪固定和保证稳定的,当拆分成两个后,其稳定性会下降,制作难度增加,不稳定性增加,且基岛的形状过于狭长,对放置于其上的芯片形状的限制过于苛刻。There are also frame structures using two base islands in the prior art, such as Chinese patent application, application number 201920418685.X, published on October 25, 2019, which discloses an ESOP8 dual-base island packaging frame, which can satisfy multiple chips Or the requirements of the joint action of chips of different polarities can improve the flexibility of use, reduce costs, and avoid the problems of complex structure of the integrated circuit board and poor overall product performance, including the base island, the pins, the pins and the base. The chips on the island are connected, and the pins are encapsulated by plastic encapsulation materials, and the pins include eight: the eight pins are divided into two groups and are distributed on the upper side and the lower side of the frame. It is characterized in that, the base island includes Two: the first base island and the second base island, the first base island and the second base island are arranged symmetrically with the transverse centerline of the frame as the axis, and the pins on the upper side and the pins on the lower side are The chips on adjacent base islands are connected. At that time, it only split one base island into two base islands. Since the original base island was fixed and guaranteed by the claws at both ends, when it is split into two, its stability will decrease and the manufacturing difficulty will increase. , the instability increases, and the shape of the base island is too narrow and long, and the restrictions on the shape of the chip placed on it are too strict.

发明内容SUMMARY OF THE INVENTION

1.要解决的技术问题1. Technical problems to be solved

针对现有技术中存在的现有单基岛无法同时封装整流器和芯片,双基岛稳定性差和形状过于狭长的问题,本实用新型提供了一种芯片框架、封装芯片、驱动系统及照明装置,它可以实现使整流器和芯片集成封装在一个芯片内,稳定性好,性能好。Aiming at the problems in the prior art that the existing single-base island cannot encapsulate the rectifier and the chip at the same time, the double-base island has poor stability and the shape is too narrow and long, the utility model provides a chip frame, a packaged chip, a driving system and a lighting device, It can realize the integrated package of the rectifier and the chip in one chip, with good stability and good performance.

2.技术方案2. Technical solutions

本实用新型的目的通过以下技术方案实现。The purpose of the present utility model is achieved through the following technical solutions.

一种芯片框架,包括相邻设置的第一基岛A和第二基岛B,每一个基岛分别包括不少于四条边,且两个基岛中间具有间隔,两个基岛相邻的两条边为相邻边,相背离的边为背离边;基岛的其余侧边为引脚边,每个基岛相对的引脚边至少各设置一个筋爪,所述的筋爪配置为芯片的引脚。A chip frame, comprising a first base island A and a second base island B arranged adjacently, each base island respectively including no less than four sides, and there is a space between the two base islands, and the two base islands are adjacent to each other. The two sides are adjacent sides, and the side facing away from each other is the side away from each other; the other sides of the base island are pin sides, and at least one claws are arranged on the opposite pin sides of each base island, and the claws are configured as follows: chip pins.

更进一步的,所述的背离边还设置有至少一个筋爪。Furthermore, at least one tendon is provided on the side facing away from the side.

更进一步的,筋爪与其所在的边呈夹角设置。Further, the claws are arranged at an included angle with the side where they are located.

更进一步的,所述的夹角为90°。Further, the included angle is 90°.

更进一步的,还包括若干分离引脚,分离引脚设置在第一基岛A和第二基岛B外围,分离引脚与第一基岛A和第二基岛B上的器件电连接。Further, it also includes a plurality of separation pins, the separation pins are arranged on the periphery of the first base island A and the second base island B, and the separation pins are electrically connected to the devices on the first base island A and the second base island B.

更进一步的,所述的分离引脚为四个,分别设置在芯片框架四角。Further, the number of said separation pins is four, which are respectively arranged at the four corners of the chip frame.

一种封装芯片,采用上述任一所述芯片框架。A packaged chip adopts any one of the above-mentioned chip frames.

更进一步的,封装芯片包括至少一芯片和一整流器,第一基岛A上设置有整流器的部分器件,第二基岛B上设置有芯片和整流器的其余器件。Further, the packaged chip includes at least one chip and a rectifier. The first base island A is provided with some components of the rectifier, and the second base island B is provided with the chip and other components of the rectifier.

更进一步的,所述的芯片包括芯片地和驱动端;Further, the chip includes a chip ground and a drive terminal;

二极管DN3和二极管DN4的阴极与第一基岛A共电位,二极管DN3和二极管DN4的阴极连接,作为整流器的一个输出端,并作为封装芯片的整流正极,连接整流正极引脚V+;The cathodes of the diode DN3 and the diode DN4 share the potential with the first base island A, and the cathodes of the diode DN3 and the diode DN4 are connected as an output end of the rectifier, and as the rectifier anode of the packaged chip, connected to the rectifier anode pin V+;

二极管DP1和二极管DP2的阳极、芯片地和第二基岛B共电位,作为封装芯片的公共地,二极管DN1和二极管DN2的阳极连接,并作为整流器的另一个输出端,连接整流负极引脚V-;The anodes of the diodes DP1 and DP2, the chip ground and the second base island B have a common potential, which is used as the common ground of the packaged chip. The anodes of the diodes DN1 and DN2 are connected, and as another output terminal of the rectifier, connected to the rectifier negative pin V -;

二极管DN4的阳极与二极管DP2的阴极连接的所在端作为整流器的一个输入端,连接输入引脚L;The terminal where the anode of the diode DN4 is connected to the cathode of the diode DP2 is used as an input terminal of the rectifier, and is connected to the input pin L;

二极管DN3的阳极与二极管DP1的阴极连接的所在端作为整流器的另一个输入端,连接输入引脚N;The terminal where the anode of the diode DN3 is connected to the cathode of the diode DP1 is used as another input terminal of the rectifier, and is connected to the input pin N;

连接封装芯片的功率引脚OUT。Connect to the power pin OUT of the packaged chip.

更进一步的,封装芯片还包括设置端,该设置端用于设置芯片驱动端的功率或电流,设置端连接设置引脚CS。Further, the packaged chip further includes a setting terminal, the setting terminal is used to set the power or current of the chip driving terminal, and the setting terminal is connected to the setting pin CS.

更进一步的,所述的设置端直接或间接检测信号,在驱动端产生与检测信号单调变化关系的电压或电流。Furthermore, the setting terminal directly or indirectly detects the signal, and the driving terminal generates a voltage or current in a monotonically varying relationship with the detection signal.

一种包括上述任一所述封装芯片的驱动系统,包括负载结构,所述的负载结构包括负载装置,包括或不包括储能器件;A drive system comprising any one of the above-mentioned packaged chips, comprising a load structure, the load structure comprising a load device, including or not including an energy storage device;

当不包括储能器件时,所述的负载装置并联在整流正极引脚V+和功率引脚OUT之间;When the energy storage device is not included, the load device is connected in parallel between the positive rectifier pin V+ and the power pin OUT;

当包括储能器件时,储能器件并联在整流正极引脚V+和功率引脚OUT之间,负载装置并联在储能器件两端或并联在整流正极引脚V+和整流负极引脚V-之间。When an energy storage device is included, the energy storage device is connected in parallel between the rectifier positive pin V+ and the power pin OUT, and the load device is connected in parallel between both ends of the energy storage device or between the rectifier positive pin V+ and the rectifier negative pin V-. between.

一种照明装置,包括上述的芯片框架、封装芯片或驱动系统。A lighting device includes the above-mentioned chip frame, packaged chip or driving system.

3.有益效果3. Beneficial effects

相比于现有技术,本实用新型的优点在于:Compared with the prior art, the advantages of the present utility model are:

本方案通过双基岛设置的芯片框架,通过在不同的基岛上设置整流桥的不同部分,将整流器和芯片同时集成到芯片框架上,可以保证整体的应用电路尺寸大大减小,且双基岛的设置可以保证整流桥的性能不受影响,连线方式简单,通过对负载进行不同形式的连接,实现对负载功率的控制,降低了整流器的尺寸,且改善了功率因数。In this scheme, the chip frame set with double base islands is used, and different parts of the rectifier bridge are set on different base islands, and the rectifier and the chip are integrated into the chip frame at the same time, which can ensure that the overall application circuit size is greatly reduced, and the double base island can be greatly reduced. The setting of the island can ensure that the performance of the rectifier bridge is not affected, and the connection method is simple. By connecting the load in different forms, the control of the load power is realized, the size of the rectifier is reduced, and the power factor is improved.

附图说明Description of drawings

图1为线性恒流驱动电路示意图;Figure 1 is a schematic diagram of a linear constant current drive circuit;

图2为本方案的芯片框架结构示意图;FIG. 2 is a schematic diagram of the chip frame structure of the scheme;

图3为本方案的封装芯片的一种电路结构示意图;FIG. 3 is a schematic diagram of a circuit structure of the packaged chip of the scheme;

图4为本方案的封装芯片引线连接示意图;FIG. 4 is a schematic diagram of the lead connection of the packaged chip of the scheme;

图5为使用本芯片框架的一种驱动系统示意图;5 is a schematic diagram of a driving system using the chip frame;

图6为使用本芯片框架的另一种驱动系统示意图;6 is a schematic diagram of another driving system using the chip frame;

图7为使用本芯片框架的再一种驱动系统示意图。FIG. 7 is a schematic diagram of still another driving system using the chip frame.

具体实施方式Detailed ways

下面结合说明书附图和具体的实施例,对本实用新型作详细描述。The present utility model will be described in detail below with reference to the accompanying drawings and specific embodiments.

实施例Example

如图2所示,本方案设计了一种芯片框架,包括两个基岛,基岛可以由金属构成,常用的金属为铜或铁,两个基岛间隔设置在框架中,间隔距离越小芯片尺寸就可以做的越小,当然需要保证两个基岛之间是隔离的,不会因为过近影响芯片的性能,两个基岛侧边的引脚边至少各设置一个筋爪,形成一对筋爪。一般情况下,筋爪设置在相对的两侧,这两侧一般都是引脚设置的框架两侧,筋爪和基岛是一体成型的,筋爪延伸到框架外侧作为产品的引脚,筋爪的作用保证了对应的基岛可以牢固,每个筋爪与对应的基岛的边形成夹角,夹角的角度优选的为90°。As shown in Figure 2, a chip frame is designed in this scheme, which includes two base islands. The base islands can be made of metal, and the commonly used metal is copper or iron. The two base islands are arranged in the frame at intervals, and the smaller the distance The smaller the chip size can be, of course, it is necessary to ensure that the two base islands are isolated, and the performance of the chip will not be affected by being too close. A pair of claws. In general, the claws are set on opposite sides, and these two sides are generally both sides of the frame where the pins are set. The claws and the base island are integrally formed, and the claws extend to the outside of the frame as the pins of the product. The action of the claws ensures that the corresponding base island can be firm, and each claws forms an included angle with the side of the corresponding base island, and the angle of the included angle is preferably 90°.

用一个实际的实施例来说明,如图2所示,示意了一种本方案结构的芯片框架,包括位于框架两边的两组引脚:第一组引脚和第二组引脚,还包括第一基岛A和第二基岛B,每一个基岛包括四条边,两个基岛有一条边相对设置,另外三条分别设置有一个筋爪;两个基岛相邻的两条边分别为每个基岛的相邻边,相背离的边为背离边;基岛的另外两条侧边为引脚边,具体的如图所示,四条边依次为第一边、第二边、第三边和第四边,第一边和第二边为引脚边,第三边为背离边,第四边为相邻边,四条边围成的区域为对应的基岛,用于放置芯片,第一边、第二边和第三边上分别一体成型连接三个筋爪,分别为第一筋爪C,第二筋爪D和第三筋爪E,用以增强基岛的稳定性,两个基岛的第四边相对设置,中间留有间隙;第三筋爪E起到的作用是额外增加基岛的稳定性,当然第三筋爪E可以不设置,只需要一个基岛设置一对相对设置的筋爪即可,第一筋爪C,第二筋爪D分别向两侧拉伸,就可以保证基岛的平衡稳定。当然每个基岛上可以设置两对或者两对以上的筋爪,因为功能性引脚的需求,可以设置更多的筋爪作为引脚,也可以通过设置多条侧边来设置对应引脚,都符合我们的设计方案和思路。To illustrate with an actual embodiment, as shown in Figure 2, a chip frame with the structure of this scheme is illustrated, including two groups of pins on both sides of the frame: a first group of pins and a second group of pins, and also includes The first base island A and the second base island B, each base island includes four sides, one side of the two base islands is oppositely arranged, and the other three are respectively arranged with a tendon claw; the two adjacent sides of the two base islands are respectively is the adjacent side of each base island, and the side facing away from each other is the side away from each other; the other two sides of the base island are the pin sides. Specifically, as shown in the figure, the four sides are the first side, the second side, the The third side and the fourth side, the first side and the second side are the pin sides, the third side is the away side, the fourth side is the adjacent side, and the area enclosed by the four sides is the corresponding base island, which is used for placing Chip, the first side, the second side and the third side are integrally formed and connected with three claws, respectively the first claws C, the second claws D and the third claws E, to enhance the stability of the base island The fourth sides of the two base islands are set opposite each other, leaving a gap in the middle; the function of the third claws E is to additionally increase the stability of the base islands. Of course, the third claws E may not be set, and only one base A pair of oppositely arranged tendon claws can be arranged on the island. The first tendon claws C and the second tendon claws D are stretched to both sides respectively, so as to ensure the balance and stability of the base island. Of course, two or more pairs of claws can be set on each base island. Due to the requirements of functional pins, more claws can be set as pins, and corresponding pins can also be set by setting multiple sides. , all in line with our design scheme and ideas.

现有技术中,一般是单基岛的形式,其通过两端设置的一对筋爪来固定单基岛,在图2中就相当于第三筋爪E的位置,两端的筋爪因为会有分别向端部的受力,在进行固封后,起到稳定基岛的作用,但是由于基岛现在为双基岛,每个基岛都会被对应的第三筋爪E向各自方向拉伸受力,不稳定会增强,所以本方案设置了与基岛一体成型的成对筋爪,可以保证双基岛的框架结构依旧稳定。In the prior art, it is generally in the form of a single base island, which fixes the single base island by a pair of claws arranged at both ends, which is equivalent to the position of the third claws E in FIG. There is a force to the end respectively. After solid sealing, it plays the role of stabilizing the base island. However, since the base island is now a double base island, each base island will be pulled in its own direction by the corresponding third claws E. Stretching force and instability will increase, so this scheme sets up a pair of claws integrally formed with the base island, which can ensure that the frame structure of the double base island is still stable.

具体的,在使用过程中,两个基岛的第一筋爪C分别配置为第一组引脚中的第2引脚和第3引脚;两个基岛的第二筋爪D分别配置为第二组引脚中的第7引脚和第6引脚;每个筋爪与对应的边形成的夹角为90度。Specifically, during use, the first claws C of the two base islands are respectively configured as the second pin and the third pin in the first group of pins; the second claws D of the two base islands are respectively configured It is the 7th pin and the 6th pin in the second group of pins; the included angle formed by each claws and the corresponding edge is 90 degrees.

优选的还可以设置有对应的分离引脚,分离引脚的数量不受限制,此实施例中,框架还包含位于第一基岛A的第一筋爪C和第三筋爪E之间的第1引脚、位于第一基岛A的第二筋爪D和第三筋爪E之间的第8引脚、位于第二基岛B的第一筋爪C和第三筋爪E之间的第4引脚、位于第二框架B的第二筋爪D和第三筋爪E之间的第5引脚。第1引脚、第4引脚、第5引脚和第8引脚都不与基岛直接连接,这里的直接连接指一体成型连接或者其它机械其它连通的方式,在封装时候可以通过打线的方式来进行引脚和芯片的电连接。当然,如果有需要或者工艺需要,对应的第1引脚、第4引脚、第5引脚和第8引脚可以有选择的与基岛连接。一体成型对应筋爪作为引脚,分离引脚的数量也可以根据需要增加。Preferably, corresponding separation pins may also be provided, and the number of separation pins is not limited. In this embodiment, the frame further includes a The 1st pin, the 8th pin located between the second claws D and the third claws E of the first base island A, the first claws C and the third claws E of the second base island B The 4th pin between the second frame B and the 5th pin between the second claws D and the third claws E of the second frame B. The 1st pin, 4th pin, 5th pin and 8th pin are not directly connected to the base island. The direct connection here refers to integral molding connection or other mechanical connection methods, which can be connected by wire bonding during packaging. way to make the electrical connection between the pins and the chip. Of course, if there is a need or a process requirement, the corresponding 1st pin, 4th pin, 5th pin and 8th pin can be selectively connected to the base island. The corresponding claws are integrally formed as pins, and the number of separated pins can also be increased as required.

基于上述的芯片框架结构,可以设计一种封装芯片,如图3和图4所示,Based on the above chip frame structure, a packaged chip can be designed, as shown in Figures 3 and 4,

利用所述双基岛框架,包括至少一芯片CHIP和一整流器,所述整流器包括以全桥整流方式连接的四个二极管,分别为二极管DP1、二极管DP2、二极管DN3和二极管DN4,芯片CHIP包括芯片地和驱动端。Using the double-base island frame, it includes at least one chip CHIP and a rectifier. The rectifier includes four diodes connected in a full-bridge rectification manner, which are diode DP1, diode DP2, diode DN3, and diode DN4. The chip CHIP includes a chip ground and drive side.

二极管DP1和二极管DP2、芯片放置于第二基岛B上,二极管DP1和二极管DP2的阳极、芯片地和第二基岛B共电位,作为封装芯片的公共地;The diode DP1, the diode DP2, and the chip are placed on the second base island B, and the anodes of the diode DP1 and the diode DP2, the chip ground and the second base island B have a common potential as the common ground of the packaged chip;

二极管DN3和二极管DN4放置于第一基岛A上,二极管DN3和二极管DN4的阴极与第一基岛A共电位,作为封装芯片的整流正极引脚V+;The diode DN3 and the diode DN4 are placed on the first base island A, and the cathodes of the diode DN3 and the diode DN4 share the potential with the first base island A, which are used as the rectifier positive pin V+ of the packaged chip;

二极管DN4的阳极与二极管DP2的阴极连接的所在端作为整流器的一个输入端,连接输入引脚L;二极管DN3的阳极与二极管DP1的阴极连接的所在端作为整流器的另一个输入端,连接输入引脚N;二极管DN3和二极管DN4的阴极连接所在作为整流器的一个输出端,连接整流正极引脚V+,二极管DP1和二极管DP2的阳极连接所在作为整流器的另一个输出端,连接整流负极引脚V-;整流负极引脚V-作为封装芯片的公共地,芯片CHIP的驱动端连接封装芯片的功率引脚OUT,其作为封装芯片的功率端OUT。The terminal where the anode of the diode DN4 is connected to the cathode of the diode DP2 is used as an input terminal of the rectifier, which is connected to the input pin L; the terminal where the anode of the diode DN3 is connected to the cathode of the diode DP1 is used as another input terminal of the rectifier, which is connected to the input lead. Pin N; the cathode connection of diode DN3 and diode DN4 is used as an output terminal of the rectifier, and is connected to the rectifier anode pin V+, and the anode connection of diode DP1 and diode DP2 is the other output terminal of the rectifier, which is connected to the rectifier cathode pin V- ; The rectifier negative pin V- is used as the common ground of the packaged chip, and the driving end of the chip CHIP is connected to the power pin OUT of the packaged chip, which serves as the power end OUT of the packaged chip.

所述二极管DP2和二极管DP1的阳极通过导电材料与第二基岛B短路连接,导电材料可以为导电胶。阴极通过打线分别连接集成驱动电路的输入引脚L和输入引脚N;所述二极管DN4和二极管DN3的阴极通过导电材料与第一基岛A短路连接;阳极通过打线分别连接集成驱动电路的输入引脚L和输入引脚N。The anodes of the diode DP2 and the diode DP1 are short-circuited to the second base island B through a conductive material, and the conductive material may be conductive glue. The cathode is respectively connected to the input pin L and the input pin N of the integrated drive circuit through wire bonding; the cathodes of the diode DN4 and the diode DN3 are short-circuited to the first base island A through conductive materials; the anode is respectively connected to the integrated drive circuit through wire bonding of input pin L and input pin N.

所述芯片还包括一设置端,设置端连接到封装芯片的设置引脚CS,设置端CS用于设置芯片驱动端的功率或电流,设置端可以直接或者间接的检测其它信号,获得相应的性能,例如通过一电阻接公共地V-,在功率端OUT产生与该电阻值成单调变化关系的电压或者电流,再例如,直接检测其它信号或者通过电阻间接检测其它信号,在功率端OUT产生与所述其它信号成单调变化关系的电压或者电流。当然,根据实际需要,设置端也可以增加为多个。The chip also includes a setting terminal, the setting terminal is connected to the setting pin CS of the packaged chip, the setting terminal CS is used to set the power or current of the chip driving terminal, and the setting terminal can directly or indirectly detect other signals to obtain the corresponding performance, For example, through a resistor connected to the common ground V-, a voltage or current with a monotonically varying relationship with the resistance value is generated at the power terminal OUT, and for example, other signals are directly detected or indirectly detected through a resistor, and the power terminal OUT is generated at the power terminal OUT and all other signals are detected. A voltage or current that describes other signals in a monotonically varying relationship. Of course, according to actual needs, the number of setting terminals can also be increased.

前述的单调变化关系包括正单调变化和反单调变化,正单调变化指当自变量增加时,因变量随之增加,或者自变量减小时,因变量随之减小;反单调变化指当自变量增加时,因变量随之减小,或者自变量减小时,因变量随之增加。例如将因变量配置为自变量的一次函数。The aforementioned monotonic change relationship includes positive monotonic change and inverse monotonic change. Positive monotonic change means that when the independent variable increases, the dependent variable increases, or when the independent variable decreases, the dependent variable decreases; When it increases, the dependent variable decreases, or when the independent variable decreases, the dependent variable increases. For example, configure the dependent variable as a primary function of the independent variable.

以下也是如此。The same is true below.

一种驱动系统,基于上述的封装芯片,可以构建驱动负载的驱动系统,对应的驱动系统中可以有两种负载结构:A drive system, based on the above packaged chip, can build a drive system that drives a load, and the corresponding drive system can have two load structures:

一种负载结构是不包括储能器件,仅仅包括负载装置,负载装置可以为LED单元,所述LED单元包括至少一个LED或者多个串并联组合的LED,优化地,也包括控制上述LED电流的控制电路,例如包括一路或多路限流的控制电路。A load structure does not include an energy storage device, but only includes a load device. The load device can be an LED unit, and the LED unit includes at least one LED or a plurality of LEDs combined in series and parallel. The control circuit, for example, includes one or more current-limiting control circuits.

如图5所示,LED单元并联在整流正极引脚V+和功率引脚OUT之间,阳极连接整流正极引脚V+,阴极连接功率引脚OUT,所述LED单元包括一个LED或多个串并联组合的LED;当交流电AC电压大于LED单元的导通门限时,LED单元导通,LED单元上的电流由芯片CHIP的功率端OUT控制,功率端OUT的电流可以通过在CS端连接电阻至整流负极引脚V-获得设置。通过在整流正极引脚V+和整流负极引脚V-两端并联一储能器件,电容,可以在交流电AC电压低于其两端电压VCAP时,维持LED单元的电流不变,获得无频闪的效果,这种方案电路简单,成本低。As shown in Figure 5, the LED unit is connected in parallel between the rectifier positive pin V+ and the power pin OUT, the anode is connected to the rectifier positive pin V+, and the cathode is connected to the power pin OUT. The LED unit includes one LED or multiple series-parallel connection Combined LED; when the AC voltage of the alternating current is greater than the conduction threshold of the LED unit, the LED unit is turned on, the current on the LED unit is controlled by the power terminal OUT of the chip CHIP, and the current of the power terminal OUT can be rectified by connecting a resistor at the CS terminal Negative pin V- gets set. By connecting an energy storage device and capacitor in parallel at both ends of the rectifier positive pin V+ and the rectifier negative pin V-, when the AC voltage of the alternating current is lower than the voltage VCAP at both ends, the current of the LED unit can be maintained unchanged, and no flicker can be obtained. The effect of this scheme is simple circuit and low cost.

这种方案在交流电上升到大于电容CAP两端电压时,会在交流电AC上流过较大的脉冲电流,功率因数低,当负载功率较大时,对应的整流器包括的四个二极管也需要较大的体积,以抵抗大的脉冲电流,这将会增大集成驱动芯片使用的框架尺寸,相应地,本发明给出了如下另一种负载结构的解决方案。In this scheme, when the alternating current rises to be greater than the voltage across the capacitor CAP, a large pulse current will flow through the alternating current AC, and the power factor is low. When the load power is large, the corresponding rectifier includes four diodes that also need to be larger. In order to resist the large pulse current, this will increase the frame size used by the integrated driver chip. Accordingly, the present invention provides another load structure solution as follows.

另一种负载结构是包括储能器件和负载装置,本方案的储能器件为电容CAP,也可以为其他类型的储能器件,并联在整流正极引脚V+和功率引脚OUT之间;Another load structure includes an energy storage device and a load device. The energy storage device in this solution is a capacitor CAP, or other types of energy storage devices, which are connected in parallel between the rectifier positive pin V+ and the power pin OUT;

有储能装置的负载装置连接方式有两种,一种直接并联在储能器件,即电容CAP的两端,如图6,电容CAP用于降低LED单元的电流纹波,抑制频闪,在交流电AC电压低于其两端电压VCAP时,维持LED单元的电流持续,在交流电AC电压大于电容CAP两端电压VCAP时,由交流电AC经整流桥给LED单元供电,同时给电容CAP充电,给LED单元供电和给电容CAP充电的总电流由功率端OUT的电流控制,功率端OUT的电流可以通过CS端设置。There are two ways to connect the load device with the energy storage device. One is directly connected to the energy storage device, that is, the two ends of the capacitor CAP, as shown in Figure 6. The capacitor CAP is used to reduce the current ripple of the LED unit and suppress flicker. When the AC voltage of the alternating current is lower than the voltage VCAP at both ends, the current of the LED unit is maintained. When the AC voltage of the alternating current is greater than the voltage VCAP at both ends of the capacitor CAP, the alternating current AC supplies power to the LED unit through the rectifier bridge, and charges the capacitor CAP at the same time. The total current of supplying power to the LED unit and charging the capacitor CAP is controlled by the current of the power terminal OUT, and the current of the power terminal OUT can be set through the CS terminal.

另一种负载装置的连接方式是:负载装置并联在整流正极引脚V+和整流负极引脚V-之间,如图7,电容CAP用于降低LED单元的电流纹波,抑制频闪,在交流电AC电压低于其两端电压VCAP时,电容CAP的正端输出电流,经过LED单元、公共地V-、芯片的功率端OUT返回电容CAP的负端;在交流电AC电压大于电容CAP两端电压VCAP时,由交流电AC经整流桥给LED单元供电,同时给电容CAP充电,给电容CAP充电的总电流由功率端OUT的电流控制,功率端OUT的电流可以通过在CS端连接电阻至V-获得设置。Another connection method of the load device is: the load device is connected in parallel between the rectifier positive pin V+ and the rectifier negative pin V-, as shown in Figure 7, the capacitor CAP is used to reduce the current ripple of the LED unit and suppress flicker. When the AC voltage of the alternating current is lower than the voltage VCAP at both ends, the positive terminal of the capacitor CAP outputs the current, and returns to the negative terminal of the capacitor CAP through the LED unit, the common ground V-, and the power terminal OUT of the chip; when the AC voltage of the alternating current is greater than the two ends of the capacitor CAP When the voltage is VCAP, the alternating current AC supplies power to the LED unit through the rectifier bridge, and at the same time charges the capacitor CAP. The total current charging the capacitor CAP is controlled by the current of the power terminal OUT. The current of the power terminal OUT can be connected to the CS terminal by connecting a resistor to V - Get settings.

图6和图7中,将CS端通过电阻连接至整流负极引脚V-,在CS端获得确定的电压或者电流,在功率端OUT产生与之呈正单调变化关系的电压或者电流,实现对负载功率的设置;In Figure 6 and Figure 7, the CS terminal is connected to the rectifier negative pin V- through a resistor, a certain voltage or current is obtained at the CS terminal, and a voltage or current with a positive monotonic relationship is generated at the power terminal OUT to realize the load. power setting;

或者,or,

CS端通过电阻或电阻网络检测电容CAP的正极或负极的电压,感知到与交流电AC电压关联的参数,并调整功率端OUT的电流,使之与交流电AC电压呈反单调变化关系,获得对电容CAP两端电压的控制,实现对负载功率的控制,当交流电AC电压升高时,OUT端对电容CAP的充电电流减小,反之,当交流电AC电压升高时,功率端OUT对电容CAP的充电电流增加,既提升了功率因数,又获得了较好的电路转换效率,这在现有公开文件“高功率因数、无频闪的LED驱动电路”,专利申请号201610160462.9中有相关描述,在此不多赘述。The CS terminal detects the positive or negative voltage of the capacitor CAP through a resistor or a resistor network, senses the parameters related to the AC voltage of the alternating current, and adjusts the current of the power terminal OUT so that it has an inverse monotonic relationship with the AC voltage of the alternating current. The control of the voltage at both ends of the CAP realizes the control of the load power. When the AC voltage of the alternating current increases, the charging current of the OUT terminal to the capacitor CAP decreases. On the contrary, when the AC voltage of the alternating current increases, the power terminal OUT charges the capacitor CAP. The increase of the charging current not only improves the power factor, but also obtains a better circuit conversion efficiency, which is described in the existing publication "LED drive circuit with high power factor and flicker-free", patent application number 201610160462.9, which is described in I won't go into details here.

本实施例中,电容CAP的电流由芯片的功率端OUT控制,降低了流过交流电AC的脉冲电流,既改善了功率因数,也降低了整流器的脉冲电流,使得较小体积的二极管可以被采用,降低了本发明的集成驱动芯片的框架尺寸。In this embodiment, the current of the capacitor CAP is controlled by the power terminal OUT of the chip, which reduces the pulse current flowing through the alternating current AC, which not only improves the power factor, but also reduces the pulse current of the rectifier, so that a diode with a smaller volume can be used. , reducing the frame size of the integrated driving chip of the present invention.

具体的可以将上述的驱动芯片或者驱动系统做相应的应用,例如LED照明装置设置有对应的芯片或驱动电路。Specifically, the above-mentioned driving chip or driving system can be applied accordingly, for example, the LED lighting device is provided with a corresponding chip or driving circuit.

以上示意性地对本发明创造及其实施方式进行了描述,该描述没有限制性,在不背离本发明的精神或者基本特征的情况下,能够以其他的具体形式实现本发明。附图中所示的也只是本发明创造的实施方式之一,实际的结构并不局限于此,权利要求中的任何附图标记不应限制所涉及的权利要求。所以,如果本领域的普通技术人员受其启示,在不脱离本创造宗旨的情况下,不经创造性的设计出与该技术方案相似的结构方式及实施例,均应属于本专利的保护范围。此外,“包括”一词不排除其他元件或步骤,在元件前的“一个”一词不排除包括“多个”该元件。产品权利要求中陈述的多个元件也可以由一个元件通过软件或者硬件来实现。第一,第二等词语用来表示名称,而并不表示任何特定的顺序。The invention and its embodiments have been described above schematically, and the description is not restrictive. The invention can be implemented in other specific forms without departing from the spirit or essential features of the invention. What is shown in the accompanying drawings is only one of the embodiments of the present invention, and the actual structure is not limited thereto, and any reference signs in the claims shall not limit the related claims. Therefore, if those of ordinary skill in the art are inspired by it, and without departing from the purpose of the present invention, any structure and embodiment similar to this technical solution are designed without creativity, which shall belong to the protection scope of this patent. Furthermore, the word "comprising" does not exclude other elements or steps, and the word "a" preceding an element does not exclude the inclusion of "a plurality" of that element. Several elements recited in a product claim can also be implemented by one element by means of software or hardware. The terms first, second, etc. are used to denote names and do not denote any particular order.

Claims (14)

1.一种芯片框架,其特征在于:包括相邻设置的第一基岛A和第二基岛B,每个基岛分别包括不少于四条边,且两个基岛中间具有间隔,两个基岛相邻的两条边为相邻边,相背离的边为背离边;基岛的其余侧边为引脚边,每个基岛相对的引脚边至少各设置一个筋爪,所述的筋爪配置为芯片的引脚。1. a chip frame, it is characterized in that: comprise the first base island A and the second base island B that are arranged adjacently, each base island comprises not less than four sides respectively, and there is interval in the middle of two base islands, two The two adjacent sides of each base island are adjacent sides, and the side facing away from each other is the away side; the other sides of the base island are the lead sides, and at least one claws are set on the opposite lead sides of each base island. The described claws are configured as the pins of the chip. 2.根据权利要求1所述的一种芯片框架,其特征在于:所述的背离边还设置有至少一个筋爪。2 . The chip frame according to claim 1 , wherein at least one tendon is further provided on the side facing away from the chip. 3 . 3.根据权利要求1或2所述的一种芯片框架,其特征在于:筋爪与其所在的边呈夹角设置。3. A chip frame according to claim 1 or 2, wherein the claws are arranged at an included angle with the side where they are located. 4.根据权利要求3所述的一种芯片框架,其特征在于:所述的夹角为90°。4 . The chip frame according to claim 3 , wherein the included angle is 90°. 5 . 5.根据权利要求1或2所述的一种芯片框架,其特征在于:还包括若干分离引脚,分离引脚设置在第一基岛A和第二基岛B外围,分离引脚与第一基岛A和第二基岛B上的器件电连接。5. A chip frame according to claim 1 or 2, characterized in that: further comprising several separation pins, the separation pins are arranged on the periphery of the first base island A and the second base island B, and the separation pins are connected to the first base island A and the second base island B. Devices on a base island A and a second base island B are electrically connected. 6.根据权利要求5所述的一种芯片框架,其特征在于:所述的分离引脚为四个,分别设置在芯片框架四角。6 . The chip frame according to claim 5 , wherein the number of said separation pins is four, which are respectively arranged at four corners of the chip frame. 7 . 7.一种封装芯片,其特征在于:采用权利要求1-6任一所述芯片框架。7. A packaged chip, characterized in that: a chip frame according to any one of claims 1-6 is used. 8.根据权利要求7所述的封装芯片,其特征在于:封装芯片包括至少一芯片和一整流器,第一基岛A上设置有整流器的部分器件,第二基岛B上设置有芯片和整流器的其余器件。8 . The packaged chip according to claim 7 , wherein the packaged chip comprises at least one chip and a rectifier, the first base island A is provided with some devices of the rectifier, and the second base island B is provided with a chip and a rectifier. 9 . the rest of the devices. 9.根据权利要求8所述的封装芯片,其特征在于:所述的整流器包括以全桥整流方式连接的四个二极管,分别为二极管DP1、二极管DP2、二极管DN3和二极管DN4,二极管DN3和二极管DN4放置于第一基岛A上,二极管DP1和二极管DP2放置于第二基岛B上。9. The packaged chip according to claim 8, wherein the rectifier comprises four diodes connected in a full-bridge rectification manner, which are diode DP1, diode DP2, diode DN3 and diode DN4, diode DN3 and diode respectively DN4 is placed on the first base island A, and diodes DP1 and DP2 are placed on the second base island B. 10.根据权利要求8或9所述的封装芯片,其特征在于:所述的芯片包括芯片地和驱动端;10. The packaged chip according to claim 8 or 9, wherein the chip comprises a chip ground and a drive terminal; 二极管DN3和二极管DN4的阴极与第一基岛A共电位,二极管DN3和二极管DN4的阴极连接,作为整流器的一个输出端,并作为封装芯片的整流正极,连接整流正极引脚V+;The cathodes of the diode DN3 and the diode DN4 share the potential with the first base island A, and the cathodes of the diode DN3 and the diode DN4 are connected as an output end of the rectifier, and as the rectifier anode of the packaged chip, connected to the rectifier anode pin V+; 二极管DP1和二极管DP2的阳极、芯片地和第二基岛B共电位,作为封装芯片的公共地,二极管DP1和二极管DP2的阳极连接,并作为整流器的另一个输出端,连接整流负极引脚V-;The anodes of the diodes DP1 and DP2, the chip ground and the second base island B have a common potential, which is used as the common ground of the packaged chip. -; 二极管DN4的阳极与二极管DP2的阴极连接的所在端作为整流器的一个输入端,连接输入引脚L;The terminal where the anode of the diode DN4 is connected to the cathode of the diode DP2 is used as an input terminal of the rectifier, and is connected to the input pin L; 二极管DN3的阳极与二极管DP1的阴极连接的所在端作为整流器的另一个输入端,连接输入引脚N;The terminal where the anode of the diode DN3 is connected to the cathode of the diode DP1 is used as another input terminal of the rectifier, and is connected to the input pin N; 驱动端连接封装芯片的功率引脚OUT。The driving end is connected to the power pin OUT of the packaged chip. 11.根据权利要求10所述的封装芯片,其特征在于:封装芯片还包括设置端,该设置端用于设置芯片驱动端的功率或电流,设置端连接设置引脚CS。11 . The packaged chip according to claim 10 , wherein the packaged chip further comprises a setting terminal, the setting terminal is used to set the power or current of the chip driving terminal, and the setting terminal is connected to the setting pin CS. 12 . 12.根据权利要求11所述的封装芯片,其特征在于:所述的设置端直接或间接检测信号,在驱动端产生与检测信号单调变化关系的电压或电流。12 . The packaged chip according to claim 11 , wherein the setting terminal directly or indirectly detects the signal, and the driving terminal generates a voltage or current in a monotonically varying relationship with the detection signal. 13 . 13.一种包括权利要求7-12任一所述封装芯片的驱动系统,其特征在于:包括负载结构,所述的负载结构包括负载装置,包括或不包括储能器件;13. A drive system comprising the packaged chip according to any one of claims 7-12, characterized in that: comprising a load structure, the load structure comprising a load device, including or not including an energy storage device; 当不包括储能器件时,所述的负载装置并联在整流正极引脚V+和功率引脚OUT之间;When the energy storage device is not included, the load device is connected in parallel between the positive rectifier pin V+ and the power pin OUT; 当包括储能器件时,储能器件并联在整流正极引脚V+和功率引脚OUT之间,负载装置并联在储能器件两端或并联在整流正极引脚V+和整流负极引脚V-之间。When an energy storage device is included, the energy storage device is connected in parallel between the rectifier positive pin V+ and the power pin OUT, and the load device is connected in parallel between both ends of the energy storage device or between the rectifier positive pin V+ and the rectifier negative pin V-. between. 14.一种照明装置,其特征在于:包括权利要求1-13任一所述的芯片框架、封装芯片或驱动系统。14. A lighting device, characterized in that it comprises the chip frame, packaged chip or driving system according to any one of claims 1-13.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113597057A (en) * 2019-11-13 2021-11-02 上海路傲电子科技有限公司 Chip frame, packaged chip, driving system and lighting device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113597057A (en) * 2019-11-13 2021-11-02 上海路傲电子科技有限公司 Chip frame, packaged chip, driving system and lighting device

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