CN212586723U - Data acquisition terminal based on LORA - Google Patents
Data acquisition terminal based on LORA Download PDFInfo
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- CN212586723U CN212586723U CN202021778765.5U CN202021778765U CN212586723U CN 212586723 U CN212586723 U CN 212586723U CN 202021778765 U CN202021778765 U CN 202021778765U CN 212586723 U CN212586723 U CN 212586723U
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Abstract
The utility model provides a data acquisition terminal based on LORA, including singlechip, LORA wireless module and data transceiver. The I/O interface and the SPI interface of the LORA wireless module are respectively connected with the single chip microcomputer, the first end of the data transceiver is connected with the single chip microcomputer through a serial port, and the second end of the data transceiver is connected with the data interface of the acquisition object. The utility model discloses a LORA wireless module carries out the wireless transmission at data acquisition terminal, has reduced transmission distance's restriction, has simplified the circuit, and it is more convenient to use.
Description
Technical Field
The utility model relates to a data acquisition technical field especially relates to a data acquisition terminal based on LORA.
Background
The data acquisition terminal is mainly used for acquiring working and running state data of the numerical control object and realizing monitoring and control of the equipment. The traditional data acquisition terminal needs to be connected with a numerical control object through a data interface to acquire various parameters of the numerical control object, and needs to be connected with a background through a communication interface to send acquired data to the background for management. The traditional data acquisition terminal mostly adopts a wired mode to send acquired data to a background, the wired mode is limited by transmission distance, wiring is inconvenient, and the data acquisition terminal is inconvenient to use.
SUMMERY OF THE UTILITY MODEL
In view of this the utility model provides a data acquisition terminal based on LORA to solve traditional data acquisition terminal and adopt wired mode to carry out data transmission and receive the restriction of transmission distance and the inconvenient problem of wiring.
The technical scheme of the utility model is realized like this: a data acquisition terminal based on LORA comprises a singlechip, an LORA wireless module and a data transceiver;
the I/O interface and the SPI interface of the LORA wireless module are respectively connected with the single chip microcomputer, the first end of the data transceiver is connected with the single chip microcomputer through a serial port, and the second end of the data transceiver is connected with the data interface of the acquisition object.
Optionally, the LORA wireless module includes a ZM470SX-M chip.
Optionally, the data transceiver includes an RS232 transceiver, a first end of the RS232 transceiver is connected to the single chip microcomputer through a serial port, and a second end of the RS232 transceiver is connected to the data interface of the acquisition object.
Optionally, the RS232 transceiver includes an SP3232EEN chip, the first end of the RS232 transceiver is pins 9 and 10 of the SP3232EEN chip, and the second end of the RS232 transceiver is pins 7 and 8 of the SP3232EEN chip.
Optionally, the data transceiver includes an RS485 transceiver and a transceiver controller;
the first end of the RS485 transceiver is connected with the single chip microcomputer through a serial port, and the second end of the RS485 transceiver is connected with a data interface of an acquisition object;
the input end of the transceiving controller is connected with the TXD port of the single chip microcomputer, the output end of the transceiving controller is connected with the enabling end of the RS485 transceiver, the transceiving controller outputs low level when the TXD port of the single chip microcomputer is high level, and outputs high level when the TXD port of the single chip microcomputer is low level.
Optionally, the RS485 transceiver includes an SP485EEN chip, the first end of the RS485 transceiver is pins No. 1 and No. 4 of the SP485EEN chip, the second end of the RS485 transceiver is pins No. 6 and No. 7 of the SP485EEN chip, and the enable end of the RS485 transceiver is pins No. 2 and No. 3 of the SP485EEN chip.
Optionally, the transceiver controller includes an SN74LVC1G00DBVR chip, the input terminals of the transceiver controller are pins No. 1 and No. 2 of the SN74LVC1G00DBVR chip, and the output terminal of the transceiver controller is pin No. 4 of the SN74LVC1G00DBVR chip.
Optionally, the data transceiver further includes a digital isolator, and the digital isolator is connected between the first end of the RS485 transceiver and the single chip microcomputer.
Optionally, the digital isolator includes an admm 3201ARZ chip, pins No. 2 and No. 3 of the admm 3201ARZ chip are respectively connected to the single chip, and pins No. 6 and No. 7 of the admm 3201ARZ chip are respectively connected to the first end of the RS485 transceiver.
The utility model discloses a data acquisition terminal based on LORA has following beneficial effect for prior art:
(1) the utility model uses the LORA wireless module to transmit the data acquisition terminal wirelessly, thus reducing the limit of transmission distance, simplifying the circuit and being more convenient to use;
(2) the utility model discloses the RS232 communication of singlechip and external equipment is realized to accessible RS232 transceiver, and the RS485 communication of singlechip and external equipment is realized to accessible RS485 transceiver, just so provides two kinds of interface communication mode 232 and 485, extensive applicability.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
Fig. 1 is a structural block diagram of the LORA-based data acquisition terminal of the present invention;
fig. 2 is a circuit diagram of the single chip microcomputer of the present invention;
FIG. 3 is a circuit diagram of a ZM470SX-M chip of the present invention;
FIG. 4 is a circuit diagram of an SP3232EEN chip according to the present invention;
FIG. 5 is a circuit diagram of ADUM3201ARZ chip and SN74LVC1G00DBVR chip of the present invention;
fig. 6 is a circuit diagram of the SP485EEN chip of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely below with reference to the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work all belong to the protection scope of the present invention.
As shown in fig. 1, the data acquisition terminal based on LORA of this embodiment includes a single chip microcomputer, a LORA wireless module, and a data transceiver. The I/O interface and the SPI interface of the LORA wireless module are respectively connected with the single chip microcomputer, the first end of the data transceiver is connected with the single chip microcomputer through a serial port, and the second end of the data transceiver is connected with the data interface of the acquisition object.
Specifically, as shown in fig. 2 and 3, the single chip includes an STM32F103C8T6 chip, the LORA wireless module includes a ZM470SX-M chip, an I/O interface of the LORA wireless module includes pins 5, 6, 7, 8, and 10 of the ZM470SX-M chip, an SPI interface of the LORA wireless module includes pins 14, 15, 16, and 17 of the ZM470SX-M chip, pins 39, 40, 41, 42, and 43 of the STM32F103C8T6 chip are connected to pins 5, 6, 7, 8, and 10 of the ZM470SX-M chip, respectively, and pins 15, 17, 16, and 14 of the STM32F103C8T6 chip are connected to pins 14, 15, 16, and 17 of the STM 470SX-M chip, respectively.
Compared with the traditional modulation technology, the ZM470SX-M chip has obvious advantages in the performance of inhibiting same frequency interference, overcomes the defect that the traditional scheme cannot give consideration to distance, interference resistance and power consumption at the same time, integrates an adjustable power amplifier with +20dBm, can obtain the receiving sensitivity exceeding-148 dBm, and has long transmission distance and high reliability.
In the embodiment, the data transceiver is used for providing a data interface channel between the acquisition object and the singlechip, various parameters of the acquisition object can be transmitted to the singlechip through the data transceiver, and the singlechip controls the LORA wireless module to send out data; the external data received by the LORA wireless module can also be transferred by the single chip microcomputer and then sent to the collection object through the data transceiver. Like this embodiment carries out data acquisition terminal's wireless transmission through LORA wireless module, has reduced transmission distance's restriction, has simplified the circuit, and it is more convenient to use.
As shown in fig. 1, the data transceiver of this embodiment includes an RS232 transceiver, a first end of the RS232 transceiver is connected to the single chip via a serial port, and a second end of the RS232 transceiver is connected to the data interface of the acquisition object. As shown in FIG. 4, the RS232 transceiver includes an SP3232EEN chip, the first end of the RS232 transceiver is pins 9 and 10 of the SP3232EEN chip, and the second end of the RS232 transceiver is pins 7 and 8 of the SP3232EEN chip. Pins 9 and 10 of the SP3232EEN chip are correspondingly connected with pins 13 and 12 of the STM32F103C8T6 chip one by one, and pins 7 and 8 of the SP3232EEN chip are connected with an external device interface. Thus, the embodiment can realize the RS232 communication between the singlechip and the external equipment through the RS232 transceiver.
As shown in fig. 1, the data transceiver of the present embodiment further includes an RS485 transceiver and a transceiver controller. The first end of the RS485 transceiver is connected with the single chip microcomputer through a serial port, and the second end of the RS485 transceiver is connected with a data interface of the acquisition object. The input end of the receiving and transmitting controller is connected with the TXD port of the single chip microcomputer, the output end of the receiving and transmitting controller is connected with the enabling end of the RS485 receiver, the receiving and transmitting controller outputs low level when the TXD port of the single chip microcomputer is high level, and outputs high level when the TXD port of the single chip microcomputer is low level.
Specifically, as shown in fig. 6, the RS485 transceiver includes an SP485EEN chip, the first end of the RS485 transceiver is the pins No. 1 and No. 4 of the SP485EEN chip, the second end of the RS485 transceiver is the pins No. 6 and No. 7 of the SP485EEN chip, and the enable end of the RS485 transceiver is the pins No. 2 and No. 3 of the SP485EEN chip. As shown in fig. 5, the transceiver controller includes an SN74LVC1G00DBVR chip, the input terminals of the transceiver controller are pins 1 and 2 of the SN74LVC1G00DBVR chip, and the output terminal of the transceiver controller is pin 4 of the SN74LVC1G00DBVR chip.
Further, as shown in fig. 1, in this embodiment, it is preferable that the data transceiver further includes a digital isolator, and the digital isolator is connected between the first end of the RS485 transceiver and the single chip. As shown in fig. 5, the digital isolator includes an admm 3201ARZ chip, pins 2 and 3 of the admm 3201ARZ chip are connected to the single chip respectively, and pins 6 and 7 of the admm 3201ARZ chip are connected to the first end of the RS485 transceiver respectively.
The ADUM3201ARZ chip is a dual-channel digital isolator, provides two independent isolation channels with various channel configurations and data rates, provides compatibility with a low-voltage system and a voltage conversion function across an isolation gate, and can ensure the direct current correctness of input logic conversion and power-on/power-off conditions.
In this embodiment, pins 22 and 21 of the STM32F103C8T6 chip are connected to pins 2 and 3 of the ADUM3201ARZ chip in a one-to-one correspondence manner, pin 7 of the ADUM3201ARZ chip is connected to pin 1 of the SP485EEN chip, pin 6 of the ADUM3201ARZ chip is connected to pins 1 and 2 of the SN74LVC1G00DBVR chip at the same time, pin 4 of the SN74LVC1G00DBVR chip is connected to pins 2 and 3 of the SP485EEN chip at the same time, and pin 6 of the ADUM3201ARZ chip is also connected to pin 4 of the SP485EEN chip. As shown in fig. 4, the RS232 transceiver and the RS485 transceiver may be connected to external devices through an integrated interface J4.
In this embodiment, the RS485 communication of singlechip and external equipment can be realized through the RS485 transceiver, so this embodiment just provides two interface communication modes of 232 and 485, and the applicability is wide. In 485 communication, a transceiving controller is used for controlling the transceiving state of an RS485 transceiver, when a single chip receives data, a TXD pin is set to be high level by default, an SN74LVC1G00DBVR chip is an NAND gate, when pins 2 and 3 are high level at the same time, a pin 4 outputs low level, a pin 2 of an SP485EEN chip is effective, and the SP485EEN chip works in the receiving state. Because interference such as a grounding loop, transient voltage and the like often exists in the process of long-distance transmission, reliable isolation design is very important, and the digital isolator is used for carrying out digital isolation on the single chip microcomputer and the RS485 transceiver, so that the influence of the interference in a circuit on the single chip microcomputer is avoided.
The above description is only a preferred embodiment of the present invention, and should not be taken as limiting the invention, and any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (9)
1. A data acquisition terminal based on LORA is characterized by comprising a single chip microcomputer, an LORA wireless module and a data transceiver;
the I/O interface and the SPI interface of the LORA wireless module are respectively connected with the single chip microcomputer, the first end of the data transceiver is connected with the single chip microcomputer through a serial port, and the second end of the data transceiver is connected with the data interface of the acquisition object.
2. The LORA-based data collection terminal of claim 1, wherein the LORA wireless module comprises a ZM470SX-M chip.
3. The LORA-based data acquisition terminal of claim 1, wherein the data transceiver comprises an RS232 transceiver, a first end of the RS232 transceiver is connected to the single chip via a serial port, and a second end of the RS232 transceiver is connected to a data interface of an acquisition object.
4. The LORA-based data acquisition terminal of claim 3, wherein the RS232 transceiver comprises an SP3232EEN chip, the first end of the RS232 transceiver is pins 9 and 10 of the SP3232EEN chip, and the second end of the RS232 transceiver is pins 7 and 8 of the SP3232EEN chip.
5. The LORA-based data acquisition terminal of claim 1 wherein the data transceiver comprises an RS485 transceiver and a transceiver controller;
the first end of the RS485 transceiver is connected with the single chip microcomputer through a serial port, and the second end of the RS485 transceiver is connected with a data interface of an acquisition object;
the input end of the transceiving controller is connected with the TXD port of the single chip microcomputer, the output end of the transceiving controller is connected with the enabling end of the RS485 transceiver, the transceiving controller outputs low level when the TXD port of the single chip microcomputer is high level, and outputs high level when the TXD port of the single chip microcomputer is low level.
6. The LORA-based data acquisition terminal of claim 5, wherein the RS485 transceiver comprises an SP485EEN chip, the first end of the RS485 transceiver is pins No. 1 and No. 4 of the SP485EEN chip, the second end of the RS485 transceiver is pins No. 6 and No. 7 of the SP485EEN chip, and the enable end of the RS485 transceiver is pins No. 2 and No. 3 of the SP485EEN chip.
7. A LORA-based data acquisition terminal according to claim 5, wherein the transceiver controller comprises an SN74LVC1G00DBVR chip, the input terminals of the transceiver controller are pins 1 and 2 of the SN74LVC1G00DBVR chip, and the output terminal of the transceiver controller is pin 4 of the SN74LVC1G00DBVR chip.
8. The LORA-based data acquisition terminal of any of claims 5-7, wherein the data transceiver further comprises a digital isolator, the digital isolator being coupled between the first end of the RS485 transceiver and the single-chip microcomputer.
9. The LORA-based data acquisition terminal as recited in claim 8, wherein the digital isolator comprises an ADUM3201ARZ chip, pins 2 and 3 of the ADUM3201ARZ chip are respectively connected to the single chip, and pins 6 and 7 of the ADUM3201ARZ chip are respectively connected to the first end of the RS485 transceiver.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202021778765.5U CN212586723U (en) | 2020-08-24 | 2020-08-24 | Data acquisition terminal based on LORA |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202021778765.5U CN212586723U (en) | 2020-08-24 | 2020-08-24 | Data acquisition terminal based on LORA |
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| Publication Number | Publication Date |
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| CN212586723U true CN212586723U (en) | 2021-02-23 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202021778765.5U Active CN212586723U (en) | 2020-08-24 | 2020-08-24 | Data acquisition terminal based on LORA |
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