CN212540612U - Pulse peak holding circuit and partial discharge monitoring circuit - Google Patents
Pulse peak holding circuit and partial discharge monitoring circuit Download PDFInfo
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- CN212540612U CN212540612U CN202021786256.7U CN202021786256U CN212540612U CN 212540612 U CN212540612 U CN 212540612U CN 202021786256 U CN202021786256 U CN 202021786256U CN 212540612 U CN212540612 U CN 212540612U
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Abstract
The utility model provides a pulse peak holding circuit, partial discharge monitoring circuit, in the pulse peak holding circuit, the non inverting input end of the first operational amplifier is connected with the signal input end, the inverting input end is respectively connected with the inverting input end and the output end of the second operational amplifier, the output end of the first operational amplifier is connected with the input end of the first pulse peak holding circuit; the non-inverting input end of the second operational amplifier is connected with the output end of the pulse peak holding circuit, and the output end of the second operational amplifier is connected with the signal output end. The utility model discloses set up first operational amplifier, second operational amplifier in pulse peak hold circuit, make the pulse signal maximum value of first pulse peak hold circuit latch signal input and eliminated the pulse signal error through first operational amplifier and second operational amplifier, the sampling module of the back level of being convenient for samples, has reduced the requirement to sampling module and analog to digital converter, has reduced the monitoring cost of putting in office.
Description
Technical Field
The utility model relates to a pulse signal gathers the field, especially relates to pulse peak holding circuit, partial discharge monitoring circuit.
Background
Partial discharge monitoring is a short for high-voltage partial discharge detection. Over time, the high-voltage electrical equipment is slowly aged, the insulation performance is reduced, and partial discharge may occur inside the high-voltage electrical equipment, which is a great hidden danger for the safety of the electrical equipment. Therefore, in order to eliminate the potential hidden trouble, the power plant staff can regularly check the condition of the equipment, check whether the equipment has partial discharge phenomenon and how serious the equipment so as to take corresponding measures in time.
When carrying out the partial discharge monitoring, need sample the pulse to the partial discharge, in order to guarantee that the sampling is accurate, need reduce the pulse signal loss, consequently, need set up the pulse hold circuit in the circuit, however, there is the error in the pulse signal of current pulse hold circuit output, and, often use low-speed sampling module to sample pulse signal among the current partial discharge monitoring circuit, can't sample the signal peak value in the high frequency pulse, in order to solve these problems, often need to change sampling module and use better analog-to-digital converter in order to provide more accurate pulse signal, the partial discharge monitoring cost has been improved.
SUMMERY OF THE UTILITY MODEL
In order to overcome prior art not enough, the utility model provides a pulse peak value holding circuit, the monitoring circuit is put in office, set up first operational amplifier in pulse peak value holding circuit, second operational amplifier, make the pulse signal maximum value of first pulse peak value holding circuit latch signal input and eliminated the pulse signal error through first operational amplifier and second operational amplifier, the sampling module of the back level of being convenient for samples, the requirement to sampling module and analog-to-digital converter has been reduced, the monitoring cost is put in office.
In order to solve the above problem, the utility model discloses a technical scheme do: a pulse peak hold circuit, the pulse peak hold circuit comprising: the pulse peak value holding circuit comprises a first pulse peak value holding circuit, a first operational amplifier and a second operational amplifier, wherein the non-inverting input end of the first operational amplifier is connected with the signal input end, the inverting input end of the first operational amplifier is respectively connected with the inverting input end and the output end of the second operational amplifier, and the output end of the first operational amplifier is connected with the input end of the first pulse peak value holding circuit; and the non-inverting input end of the second operational amplifier is connected with the output end of the pulse peak holding circuit, and the output end of the second operational amplifier is connected with the signal output end.
Further, the first pulse peak holding circuit comprises a first diode, wherein the anode of the first diode is connected with the output end of the first operational amplifier, and the cathode of the first diode is connected with the non-inverting input end of the second operational amplifier.
Furthermore, the pulse peak holding circuit further comprises a second diode and a first resistor, wherein the anode of the second diode is connected with the cathode of the first diode, the cathode of the second diode is connected with the non-inverting input end of the second operational amplifier, one end of the first resistor is connected with the anode of the second diode, and the other end of the first resistor is connected with the inverting input end of the second operational amplifier.
Furthermore, the first pulse peak holding circuit further comprises a first capacitor, one end of the first capacitor is grounded, and the other end of the first capacitor is connected with the non-inverting input end of the second operational amplifier.
Furthermore, the first pulse peak holding circuit further comprises a load resistor, one end of the load resistor is grounded, and the other end of the load resistor is connected with the output end of the second operational amplifier.
Based on the same inventive concept, the utility model also provides a partial discharge monitoring circuit, which comprises a pulse peak holding circuit and a singlechip, wherein the pulse peak holding circuit is connected with the singlechip; the single chip microcomputer receives the pulse signal sent by the pulse peak holding circuit and samples the pulse signal; the pulse peak hold circuit includes: the pulse peak value holding circuit comprises a first pulse peak value holding circuit, a first operational amplifier and a second operational amplifier; the non-inverting input end of the first operational amplifier is connected with the signal input end, the inverting input end of the first operational amplifier is respectively connected with the inverting input end and the output end of the second operational amplifier, and the output end of the first operational amplifier is connected with the input end of the first pulse peak holding circuit; and the non-inverting input end of the second operational amplifier is connected with the output end of the pulse peak holding circuit, and the output end of the second operational amplifier is connected with the signal output end.
Further, the first pulse peak holding circuit comprises a first diode, wherein the anode of the first diode is connected with the output end of the first operational amplifier, and the cathode of the first diode is connected with the non-inverting input end of the second operational amplifier.
Furthermore, the pulse peak holding circuit further comprises a second diode and a first resistor, wherein the anode of the second diode is connected with the cathode of the first diode, the cathode of the second diode is connected with the non-inverting input end of the second operational amplifier, one end of the first resistor is connected with the anode of the second diode, and the other end of the first resistor is connected with the inverting input end of the second operational amplifier.
Furthermore, the first pulse peak holding circuit further comprises a first capacitor, one end of the first capacitor is grounded, and the other end of the first capacitor is connected with the non-inverting input end of the second operational amplifier.
Furthermore, the first pulse peak holding circuit further comprises a load resistor, one end of the load resistor is grounded, and the other end of the load resistor is connected with the output end of the second operational amplifier.
Compared with the prior art, the beneficial effects of the utility model reside in that: the first operational amplifier and the second operational amplifier are arranged in the pulse peak holding circuit, the first pulse peak holding circuit latches the maximum value of the pulse signal input by the signal input end through the first operational amplifier and the second operational amplifier, the pulse signal error is eliminated, the sampling module at the later stage is convenient to sample, the requirements on the sampling module and the analog-to-digital converter are reduced, and the partial discharge monitoring cost is reduced.
Drawings
Fig. 1 is a circuit diagram of an embodiment of a pulse peak hold circuit of the present invention;
fig. 2 is a circuit diagram of another embodiment of the pulse peak hold circuit of the present invention;
FIG. 3 is a circuit diagram of an embodiment of a first pulse peak hold circuit;
fig. 4 is a structural diagram of an embodiment of the partial discharge monitoring circuit of the present invention.
In the figure: vi, an input signal; vo, output signal; c1, a first capacitance; r1, a first resistor; RL, load resistance; c1, a first capacitance; u1, a first operational amplifier; u2, a second operational amplifier; d1, a first diode; d2, a second diode.
Detailed Description
The present invention will be further described with reference to the accompanying drawings and the detailed description, and it should be noted that the embodiments or technical features described below can be arbitrarily combined to form a new embodiment without conflict.
Referring to fig. 1-3, fig. 1 is a circuit diagram of an embodiment of a pulse peak hold circuit according to the present invention; fig. 2 is a circuit diagram of another embodiment of the pulse peak hold circuit of the present invention; fig. 3 is a circuit diagram of an embodiment of a first pulse peak hold circuit. The pulse peak hold circuit of the present invention will be described in detail with reference to fig. 1 to 3.
In the present embodiment, the pulse peak hold circuit includes: the pulse peak value holding circuit comprises a first pulse peak value holding circuit, a first operational amplifier U1 and a second operational amplifier U2, wherein the non-inverting input end of the first operational amplifier U1 is connected with the signal input end, the inverting input end of the first operational amplifier U3526 is respectively connected with the inverting input end and the output end of the second operational amplifier U2, and the output end of the first operational amplifier U1 is connected with the input end of the first pulse peak value holding circuit; the non-inverting input end of the second operational amplifier U2 is connected with the output end of the pulse peak holding circuit, and the output end is connected with the signal output end. The input signal Vi is input through the signal input end, and the output signal Vo is output through the signal output end.
In this embodiment, the first pulse peak hold circuit includes a first diode D1, the anode of the first diode D1 is connected to the output terminal of the first operational amplifier U1, and the cathode is connected to the non-inverting input terminal of the second operational amplifier U2.
In this embodiment, the pulse peak holding circuit further includes a second diode D2 and a first resistor R1, wherein an anode of the second diode D2 is connected to a cathode of the first diode D1, a cathode of the second diode D3526 is connected to a non-inverting input terminal of the second operational amplifier U2, one end of the first resistor R1 is connected to an anode of the second diode D2, and the other end of the first resistor R1 is connected to an inverting input terminal of the second operational amplifier U2.
In this embodiment, the first pulse peak holding circuit further includes a first capacitor C1, one end of the first capacitor C1 is grounded, and the other end is connected to the non-inverting input terminal of the second operational amplifier U2.
In this embodiment, the first pulse peak holding circuit further includes a load resistor RL, one end of which is grounded, and the other end of which is connected to the output terminal of the second operational amplifier U2.
The pulse peak hold circuits in fig. 1 and 2 will be described with reference to the first pulse peak hold circuit in fig. 3.
As the first pulse peak holding circuit of fig. 3, by using the single-phase conductivity of the first diode D1, once the input signal Vi at the signal input terminal > the output signal Vo at the signal output terminal, the input signal Vi charges the first capacitor C1 through the first diode D1 until the maximum value of the input signal Vi is reached, and if Vi < Vo, the first diode D1 is turned off in reverse, and the voltage of Vo can still be maintained, but the circuit has a drawback in that the diode D1 has an on voltage, which is generally 0.7V, that is, when Vi <0.7V is the diode D1 is turned off, and Vo is 0V. When Vi > is 0.7V, the first diode D1 is turned on, which results in Vo being Vi-0.7V due to the voltage drop of the first diode D1. When the input signal Vi is small, the pulse peak hold circuit output error is large.
As shown in fig. 1, as can be seen from the open-loop characteristics of the operational amplifiers, for the first operational amplifier U1, Vo1 ═ a (Vi-Vn 1); for the second operational amplifier U2, Vo ═ a (Vi-Vn 1); a is the open-loop gain of the operational amplifiers U1 and U2, and A is ≧ 60 dB. Assuming that initial state Vi is 0V and Vo is 0V, if Vi changes to the positive peak, Vo is still 0 at this time, and according to the formula Vo1 is a (Vi-Vn1), Vo1 changes to the positive peak at a very fast speed, limited only by the bandwidth and slew rate of the first operational amplifier U1, when Vo1 rises to 0.7V, the first diode D1 is turned on to charge the first capacitor C1, the voltage Vo2 on the first capacitor C1 rises, because the second operational amplifier U2 is a follower circuit, Vo is Vo2, that is, Vo rises following the rise of Vo 2. Vo will rise until Vo is stopped at Vi, at which time Vo1 is a (Vi-Vn1) is a (Vi-Vo) is 0V, the capacitor C1 is no longer charged through the diode D1, the voltage Vo2 on the capacitor C1 is unchanged, Vo follows Vo2, i.e. Vo is also unchanged. When Vi begins to change to the trough, the formula Vo1 is A (Vi-Vo); vi < Vo, Vo1 will be a large negative value. At this time, the diode D1 is reversely turned off, the voltage Vo2 across the capacitor C1 is unchanged, and the output voltage Vo is also unchanged. That is to say the circuit shown in fig. 1 can latch the maximum value of the input signal Vi. However, this circuit has a drawback in that the leakage current of the diode D1 has a certain effect, especially when the frequency of the input signal Vi is high.
Continuing to improve the circuit, as shown in fig. 2, when the input signal Vi changes to a positive voltage, the circuit charges the first capacitor C1 through the first diode D1 and the second diode D2 until the output signal Vo is equal to Vi. When Vi changes to the trough, the voltage across the first diode D1 is turned off by negative voltage, and the leakage current of the diode D1 is connected to the output terminal through the resistor R1, so that the voltage of the negative terminal of the diode D1 approaches the peak voltage. Therefore, there is substantially no reverse voltage across the second diode D2, and there is no reverse current flowing through the second diode D2, so that the voltage Vo2 across the second capacitor C2 can be maintained, and the final output signal Vo can be maintained to latch the maximum value of the input signal Vi.
Has the advantages that: the utility model discloses a pulse peak value holding circuit sets up first operational amplifier, second operational amplifier, makes the pulse signal maximum value of first pulse peak value holding circuit latch signal input and eliminated the pulse signal error through first operational amplifier and second operational amplifier, and the sampling module of the back level of being convenient for samples, has reduced the requirement to sampling module and analog to digital converter, has reduced the monitoring cost of putting in office.
Based on the same inventive concept, the utility model discloses still provide a partial discharge monitoring circuit, please refer to fig. 4, fig. 4 is the utility model discloses the structure diagram of partial discharge monitoring circuit embodiment, combine fig. 4 to explain utility model's partial discharge monitoring circuit.
In this embodiment, the partial discharge monitoring circuit includes a pulse peak holding circuit and a single chip microcomputer, and the pulse peak holding circuit is connected with the single chip microcomputer; the singlechip receives the pulse signal sent by the pulse peak holding circuit and samples the pulse signal.
In the present embodiment, the pulse peak hold circuit includes: the pulse peak value holding circuit comprises a first pulse peak value holding circuit, a first operational amplifier and a second operational amplifier, wherein the non-inverting input end of the first operational amplifier is connected with the signal input end, the inverting input end of the first operational amplifier is respectively connected with the inverting input end and the output end of the second operational amplifier, and the output end of the first operational amplifier is connected with the input end of the first pulse peak value holding circuit; the non-inverting input end of the second operational amplifier is connected with the output end of the pulse peak holding circuit, and the output end of the second operational amplifier is connected with the signal output end. The input signal Vi is input through the signal input end, and the output signal Vo is output through the signal output end.
In this embodiment, the first pulse peak holding circuit includes a first diode, an anode of the first diode is connected to the output terminal of the first operational amplifier, and a cathode of the first diode is connected to the non-inverting input terminal of the second operational amplifier.
In this embodiment, the pulse peak holding circuit further includes a second diode and a first resistor, an anode of the second diode is connected to a cathode of the first diode, a cathode of the second diode is connected to a non-inverting input terminal of the second operational amplifier, one end of the first resistor is connected to an anode of the second diode, and the other end of the first resistor is connected to an inverting input terminal of the second operational amplifier.
In this embodiment, the first pulse peak holding circuit further includes a first capacitor, one end of the first capacitor is grounded, and the other end of the first capacitor is connected to the non-inverting input terminal of the second operational amplifier.
In this embodiment, the first pulse peak holding circuit further includes a load resistor, one end of the load resistor is grounded, and the other end of the load resistor is connected to the output end of the second operational amplifier.
Has the advantages that: the utility model discloses a monitoring circuit is put in office sets up first operational amplifier, second operational amplifier in pulse peak holding circuit, makes the pulse signal maximum value of first pulse peak holding circuit latch signal input and eliminated the pulse signal error through first operational amplifier and second operational amplifier, and the sampling module of the back level of being convenient for samples, has reduced the requirement to sampling module and analog to digital converter, has reduced the monitoring cost is put in office.
The above embodiments are only preferred embodiments of the present invention, and the protection scope of the present invention cannot be limited thereby, and any insubstantial changes and substitutions made by those skilled in the art based on the present invention are all within the protection scope of the present invention.
Claims (10)
1. A pulse peak hold circuit, comprising: a first pulse peak hold circuit, a first operational amplifier, a second operational amplifier,
the non-inverting input end of the first operational amplifier is connected with the signal input end, the inverting input end of the first operational amplifier is respectively connected with the inverting input end and the output end of the second operational amplifier, and the output end of the first operational amplifier is connected with the input end of the first pulse peak holding circuit;
and the non-inverting input end of the second operational amplifier is connected with the output end of the pulse peak holding circuit, and the output end of the second operational amplifier is connected with the signal output end.
2. The pulse peak hold circuit of claim 1, wherein the first pulse peak hold circuit comprises a first diode having an anode connected to the output of the first operational amplifier and a cathode connected to the non-inverting input of the second operational amplifier.
3. The pulse peak hold circuit of claim 2, further comprising a second diode, a first resistor, an anode of the second diode being connected to a cathode of the first diode, a cathode of the second diode being connected to the non-inverting input of the second operational amplifier, one end of the first resistor being connected to an anode of the second diode, and the other end of the first resistor being connected to the inverting input of the second operational amplifier.
4. The pulse peak hold circuit of claim 1, wherein the first pulse peak hold circuit further comprises a first capacitor having one end connected to ground and the other end connected to a non-inverting input of the second operational amplifier.
5. The pulse peak hold circuit of claim 1, wherein the first pulse peak hold circuit further comprises a load resistor, one end of the load resistor being connected to ground, the other end being connected to the output terminal of the second operational amplifier.
6. The partial discharge monitoring circuit is characterized by comprising a pulse peak value holding circuit and a single chip microcomputer, wherein the pulse peak value holding circuit is connected with the single chip microcomputer;
the single chip microcomputer receives the pulse signal sent by the pulse peak holding circuit and samples the pulse signal;
the pulse peak hold circuit includes: the pulse peak value holding circuit comprises a first pulse peak value holding circuit, a first operational amplifier and a second operational amplifier;
the non-inverting input end of the first operational amplifier is connected with the signal input end, the inverting input end of the first operational amplifier is respectively connected with the inverting input end and the output end of the second operational amplifier, and the output end of the first operational amplifier is connected with the input end of the first pulse peak holding circuit;
and the non-inverting input end of the second operational amplifier is connected with the output end of the pulse peak holding circuit, and the output end of the second operational amplifier is connected with the signal output end.
7. The partial discharge monitoring circuit of claim 6, wherein the first pulse peak hold circuit comprises a first diode having an anode connected to the output of the first operational amplifier and a cathode connected to the non-inverting input of the second operational amplifier.
8. The partial discharge monitoring circuit according to claim 7, wherein the pulse peak hold circuit further comprises a second diode, a first resistor, an anode of the second diode being connected to a cathode of the first diode, a cathode of the second diode being connected to a non-inverting input terminal of the second operational amplifier, and one end of the first resistor being connected to an anode of the second diode, and the other end of the first resistor being connected to an inverting input terminal of the second operational amplifier.
9. The partial discharge monitoring circuit according to claim 6, wherein the first pulse peak hold circuit further comprises a first capacitor, one end of the first capacitor is connected to ground, and the other end of the first capacitor is connected to a non-inverting input terminal of the second operational amplifier.
10. The partial discharge monitoring circuit according to claim 6, wherein the first pulse peak hold circuit further comprises a load resistor, one end of the load resistor is connected to ground, and the other end is connected to the output terminal of the second operational amplifier.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202021786256.7U CN212540612U (en) | 2020-08-24 | 2020-08-24 | Pulse peak holding circuit and partial discharge monitoring circuit |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202021786256.7U CN212540612U (en) | 2020-08-24 | 2020-08-24 | Pulse peak holding circuit and partial discharge monitoring circuit |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112147476A (en) * | 2020-08-24 | 2020-12-29 | 杭州柯林电气股份有限公司 | Pulse peak holding circuit and partial discharge monitoring circuit |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112147476A (en) * | 2020-08-24 | 2020-12-29 | 杭州柯林电气股份有限公司 | Pulse peak holding circuit and partial discharge monitoring circuit |
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