CN212518916U - Crystal oscillator circuit - Google Patents
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- CN212518916U CN212518916U CN202020651623.6U CN202020651623U CN212518916U CN 212518916 U CN212518916 U CN 212518916U CN 202020651623 U CN202020651623 U CN 202020651623U CN 212518916 U CN212518916 U CN 212518916U
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Abstract
The embodiment of the utility model discloses crystal oscillator circuit, include: the low dropout regulator (LDO) comprises a first amplifier, a second amplifier and a low dropout regulator (LDO); the signal output end of the first amplifier is connected with the signal input end of the second amplifier; a crystal is connected in parallel between the signal input end and the signal output end of the first amplifier; a first capacitor is connected in series between the signal input end of the first amplifier and the ground, and a second capacitor is connected in series between the signal output end of the first amplifier and the ground; the signal output end of the second amplifier is the clock signal output end of the crystal oscillator circuit; the first amplifier comprises N first MOS circuits which are connected in parallel; the first MOS circuit includes: at least one first PMOS tube and at least one first NMOS tube; the at least one first PMOS tube and the at least one first NMOS tube are connected in series; the LDO is configured to provide a supply voltage to the first amplifier and the second amplifier. Through the scheme of the embodiment, the power consumption is reduced, and the wide voltage input is realized.
Description
Technical Field
The present disclosure relates to crystal oscillator design, and more particularly to a crystal oscillator circuit.
Background
32.768KHz is 1Hz after 15 times of frequency division by 2 (32.768K/215 is 1), so the circuit is widely used in timing circuits, the timing circuit is usually in operation all the time, the circuit is particularly sensitive to power consumption, the lower the power consumption of the crystal oscillator is, the better the crystal oscillator is, and in addition, 1.5V button batteries and 3.6V rechargeable lithium batteries which are common in power supply voltage are required to normally operate at 1.5V-3.6V.
The crystal oscillator circuit structure is shown in fig. 1, wherein XTAL is 32.768K crystal, C1 and C2 are capacitors, X1 is an amplifier for providing crystal oscillation energy to ensure that the crystal can oscillate at about 32.768KHz, X2 is output Buffer (Buffer), and outputs 32.768KHz square wave clock. The transconductance of the X1 amplifier is gm1, and in order to ensure that the crystal can start oscillation normally, the minimum gm1_ min of gm1 needs to satisfy:
gm1_min≥ωn 2rm C1C 2 formula 1
Wherein, ω isnThe oscillation frequency (2 × pi × 32.728K) is shown, and Rm is the internal equivalent resistance of the crystal.
To ensure the crystal can start up normally, gm1 is at least 5 times larger than gm1_ min, and gm1 is directly related to the current, so the design of gm1 directly determines the power consumption level of the circuit. In addition, in chip production, chips are at different process corners, and in consideration of the problem of consistency among chips, a large current is usually required to ensure that all chips can start oscillation normally.
SUMMERY OF THE UTILITY MODEL
An embodiment of the utility model provides a crystal oscillator circuit can reduce the consumption, realizes wide voltage input.
The embodiment of the utility model provides a crystal oscillator circuit is still provided, can include: the low dropout regulator (LDO) comprises a first amplifier, a second amplifier and a low dropout regulator (LDO); the signal output end of the first amplifier is connected with the signal input end of the second amplifier; a crystal is connected in parallel between the signal input end and the signal output end of the first amplifier; a first capacitor is connected in series between a signal input end of the first amplifier and the ground, and a second capacitor is connected in series between a signal output end of the first amplifier and the ground; the signal output end of the second amplifier is a clock signal output end of the crystal oscillator circuit;
the first amplifier comprises N first MOS circuits which are connected in parallel, wherein N is more than or equal to 1 and is a positive integer; the first MOS circuit includes: at least one first PMOS tube and at least one first NMOS tube; the at least one first PMOS tube and the at least one first NMOS tube are connected in series;
the LDO is configured to provide a power supply voltage to the first amplifier and the second amplifier after stabilizing an external power supply.
In an exemplary embodiment of the present invention, the source and the drain of the first PMOS transistor are connected to a first diode, and the source and the drain of the first NMOS transistor are connected to a second diode;
the source electrode of the first PMOS tube is connected with the input power supply of the first amplifier;
the drain electrode of the first PMOS tube is connected with the drain electrode of the first NMOS tube and then serves as a signal output end of the first amplifier;
the source electrode of the first NMOS tube is grounded;
and the grid electrode of the first PMOS tube is connected with the grid electrode of the first NMOS tube and then is used as the signal input end of the first amplifier.
In an exemplary embodiment of the present invention, a first resistor is connected in series between the drain of the first PMOS transistor and the gate of the first PMOS transistor.
In an exemplary embodiment of the present invention, the crystal oscillator circuit may further include: a master control circuit;
the master control circuit may be connected to the signal output terminal of the first amplifier.
In an exemplary embodiment of the present invention, a first control switch is connected in series between the source of the first PMOS transistor and the first amplifier input power supply; and/or a second control switch is connected in series between the source electrode of the first NMOS tube and the ground;
the master control circuit may be connected to the first control switch and/or the second control switch in each first MOS circuit.
In an exemplary embodiment of the present invention, the crystal oscillator circuit may further include a first comparator and a second comparator;
the main control circuit is connected with the signal output end of the first amplifier through the first comparator and the second comparator.
In an exemplary embodiment of the present invention, the main control circuit is connected to the first output terminal of the first comparator and the second output terminal of the second comparator;
a first input end of the first comparator and a second input end of the second comparator are both connected with a signal output end of the first amplifier;
a third input end of the first comparator is an input end of the voltage lower limit threshold;
and the fourth input end of the second comparator is the input end of the voltage upper limit threshold.
In an exemplary embodiment of the present invention, the LDO may include: a first voltage input terminal and a first voltage output terminal;
the first voltage input end is connected with an external input power supply;
the first voltage output end is respectively connected with the power supply input ends of the first amplifier and the second amplifier and is set to output the power supply voltages of the first amplifier and the second amplifier.
In an exemplary embodiment of the present invention, the LDO may further include: a second voltage input terminal, a second voltage output terminal and a third voltage output terminal;
the second voltage input end is connected with the voltage output end of a second MOS circuit, and the second MOS circuit is set to generate a lower voltage threshold and an upper voltage threshold which are used for calculating the number N of the first MOS circuits;
the second voltage output end is set to output the lower voltage limit threshold;
the third voltage output end is set to output the voltage upper limit threshold value.
In an exemplary embodiment of the present invention, the second MOS circuit may include: a second PMOS tube and a second NMOS tube; the source electrode and the drain electrode of the second PMOS tube are connected with a third diode, and the source electrode and the drain electrode of the second NMOS tube are connected with a fourth diode;
the source electrode of the second PMOS tube is an input end of preset current;
the drain electrode of the second PMOS tube is connected with the drain electrode of the second NMOS tube;
the source electrode of the second NMOS tube is grounded;
and the drain electrode of the second PMOS tube, the grid electrode of the second PMOS tube and the grid electrode of the second NMOS tube are connected and then serve as the voltage output end of the second MOS circuit.
The utility model discloses crystal oscillator circuit can include: the low dropout regulator (LDO) comprises a first amplifier, a second amplifier and a low dropout regulator (LDO); the signal output end of the first amplifier is connected with the signal input end of the second amplifier; a crystal is connected in parallel between the signal input end and the signal output end of the first amplifier; a first capacitor is connected in series between a signal input end of the first amplifier and the ground, and a second capacitor is connected in series between a signal output end of the first amplifier and the ground; the signal output end of the second amplifier is a clock signal output end of the crystal oscillator circuit; the first amplifier can comprise N first MOS circuits which are connected in parallel, wherein N is more than or equal to 1 and is a positive integer; the first MOS circuit includes: at least one first PMOS tube and at least one first NMOS tube; the at least one first PMOS tube and the at least one first NMOS tube are connected in series; the LDO may be configured to provide a supply voltage to the first amplifier and the second amplifier after stabilizing an external power supply. . Through the scheme of the embodiment, the power consumption is reduced, and the wide voltage input is realized.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the invention. The objectives and other advantages of the invention may be realized and attained by the structure particularly pointed out in the written description and drawings.
Drawings
The accompanying drawings are included to provide a further understanding of the technical solutions of the present invention, and are incorporated in and constitute a part of this specification, together with the embodiments of the present invention for explaining the technical solutions of the present invention, and do not constitute a limitation on the technical solutions of the present invention.
Fig. 1 is a schematic diagram of a circuit structure of a crystal oscillator according to an embodiment of the present invention;
fig. 2 is a schematic diagram of an LDO circuit according to an embodiment of the present invention;
fig. 3 is a schematic circuit diagram of a first amplifier according to an embodiment of the present invention;
fig. 4 is a schematic diagram of a circuit structure of a crystal oscillator including a voltage conversion circuit according to an embodiment of the present invention;
fig. 5 is a schematic connection diagram of the first comparator, the second comparator and the main control circuit according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that, in the present invention, the embodiments and features of the embodiments may be arbitrarily combined with each other without conflict.
An embodiment of the present invention provides a crystal oscillator circuit, as shown in fig. 1 and fig. 3, which may include: a first amplifier 1 and a second amplifier 2; the signal output end of the first amplifier 1 is connected with the signal input end of the second amplifier 2; a crystal 3(XTAL) is connected in parallel between the signal input end and the signal output end of the first amplifier 1; a first capacitor C1 is connected in series between the signal input end of the first amplifier and the ground, and a second capacitor C2 is connected in series between the signal output end of the first amplifier 1 and the ground; the signal output end of the second amplifier 2 is a clock signal output end of the crystal oscillator circuit;
the first amplifier 1 comprises N first MOS circuits A which are connected in parallel, wherein N is more than or equal to 1 and is a positive integer;
each first MOS circuit A comprises a plurality of MOS tubes which are connected in series;
the LDO 4 may be configured to provide a supply voltage to the first amplifier 1 and the second amplifier 2 after stabilizing an external power supply.
In an exemplary embodiment of the present invention, as shown in fig. 2, the crystal oscillator circuit may further include: a low dropout linear regulator LDO 4; the LDO 4 may include: a first voltage input terminal and a first voltage output terminal;
the first voltage input end is connected with an external input power supply VDD;
the first voltage output terminal is respectively connected to the power input terminals of the first amplifier 1 and the second amplifier 2, and is configured to output the power voltage VDD _ RTC of the first amplifier 1 and the second amplifier 2.
In an exemplary embodiment of the present invention, the LDO 4 may further include: a second voltage input terminal, a second voltage output terminal and a third voltage output terminal;
the second voltage input terminal is connected to a voltage output terminal of a second MOS circuit B, which is configured to generate a lower voltage threshold VREFL and an upper voltage threshold VREFH (described in detail below) for counting the number N of first MOS circuits a in the first amplifier 1;
the second voltage output end is set to output the lower voltage limit threshold VREFL;
the third voltage output end is set to output the upper voltage limit threshold value VREFH.
In an exemplary embodiment of the present invention, the second MOS circuit B may include: a second PMOS transistor P2 and a second NMOS transistor N2;
the source electrode and the drain electrode of the second PMOS tube P2 are connected with a third diode, and the source electrode and the drain electrode of the second NMOS tube N2 are connected with a fourth diode;
the source electrode of the second PMOS tube P2 is an input end of preset current I _ IN;
the drain electrode of the second PMOS pipe P2 is connected with the drain electrode of the second NMOS pipe N2;
the source electrode of the second NMOS transistor N2 is grounded;
the drain of the second PMOS transistor P2, the gate of the second PMOS transistor P2, and the gate of the second NMOS transistor N2 are connected to serve as a voltage output terminal of the second MOS circuit B, and output a reference voltage VREF (which is input to the second voltage input terminal of the LDO 4).
In the exemplary embodiment of the present invention, in order to realize wide voltage input, the crystal oscillator circuit structure of the embodiment of the present invention is added with LDO 4(LDO is a low dropout regulator), the reference voltage VREF of the LDO 4 is not a fixed voltage value, the voltage value of the reference voltage VREF is determined by the second PMOS transistor P2 connected with the third diode and the second NMOS transistor N2 connected with the fourth diode in the second MOS circuit B, VDD _ RTC ═ VREF ═ VgsP1+ VgsN1, the voltage of VDD _ RTC will automatically adjust with the process corner.
IN the exemplary embodiment of the present invention, the preset current I _ IN flows through the second PMOS transistor P2 and the second NMOS transistor N2, and generates the reference voltage VREF, which generates the VDD _ RTC through the LDO 4 to supply power to the first amplifier 1 and the second amplifier 2.
In an exemplary embodiment of the present invention, as shown in fig. 3, the first MOS circuit a may include: at least one first PMOS transistor P1 and at least one first NMOS transistor N1; the source electrode and the drain electrode of the first PMOS pipe P1 are connected with a first diode, and the source electrode and the drain electrode of the first NMOS pipe N1 are connected with a second diode;
the source electrode of the first PMOS pipe P1 is connected with the first amplifier input power supply;
the drain electrode of the first PMOS tube P1 is connected with the drain electrode of the first NMOS tube N1 to serve as a signal output end of the first amplifier, and a signal XOUT is output;
the source electrode of the first NMOS transistor N1 is grounded;
the grid electrode of the first PMOS pipe P1 is connected with the grid electrode of the first NMOS pipe N1 to be used as a signal input end of the first amplifier, and a signal XIN is input;
a first resistor is connected in series between the drain of the first PMOS transistor P1 and the gate of the first PMOS transistor P1.
In an exemplary embodiment of the present invention, each of the first PMOS transistor P1 and the first NMOS transistor N1 has the same size as the second PMOS transistor P2 and the second NMOS transistor N2. The supply voltage of each set of the first PMOS transistor P1 and the first NMOS transistor N1 is VDD _ RTC, so that the current of each set of the first PMOS transistor P1 and the first NMOS transistor N1 substantially matches the predetermined current I _ IN.
In the exemplary embodiment of the present invention, since both the first PMOS transistor P1 and the first NMOS transistor N1 can provide gm (transconductance of the first amplifier 1), the structure naturally has more power consumption advantage than the common source amplifier that only provides gm by only PMOS transistor or only NMOS transistor. Where gm may be determined by equation 2 below. As can be seen from equation 2, the gm value is independent of the LDO output voltage, and is only dependent on the input preset current I _ IN and the parameter u of the first PMOS transistor P1 and the first NMOS transistor N1p1And un1And (4) correlating.
In the exemplary embodiment of the present invention, if the LDO employs a fixed reference voltage (i.e. VREF is a fixed value), gm can be calculated by equation 3 and equation 4, and it can be seen that gm is also related to Vgsp1, Vgsn1, Vthp1, Vthn1, and the gm value has a large difference under different process angles, which may cause the failure of the automatic calibration algorithm in the next step (the automatic calibration algorithm will be described in detail below).
VDDRTC＝Vgsp1-Vgsn1. Formula 4
In the exemplary embodiment of the present invention, the first amplifier 1 is composed of N sets of the first PMOS transistor P1 and the first NMOS transistor N1 with the same size, and between the gate (G) and the drain (D) of the first PMOS transistor P1 [ or between the gate and the drain of the first NMOS transistor N1 ], because the gate of the first PMOS transistor P1 is connected to the gate of the first NMOS transistor N1, and the drain of the first PMOS transistor P1 is connected to the drain of the first NMOS transistor N1 ], a resistor R (i.e. the aforementioned first resistor) is bridged, and the first resistor R ensures that the first PMOS transistor P1 and the first NMOS transistor N1 operate in the saturation region, which can provide the best gm value.
In the exemplary embodiment of the present invention, with the phase inverter structure of the first PMOS transistor P1 and the first NMOS transistor N1, the first PMOS transistor P1 and the first NMOS transistor N1 can both provide gm, which reduces the power consumption requirement, and at the same time, the size of the first PMOS transistor P1 and the first NMOS transistor N1 is the same as the size of the MOS transistor (the second PMOS transistor P2 and the second NMOS transistor N2) in the VREF generation circuit, so that the gm of the first amplifier 1 will not change greatly under the process change.
In the exemplary embodiment of the present invention, as shown in fig. 4, the terminal voltage XOUT of the crystal 3 may be amplified by the second amplifier 2 and subjected to voltage conversion by the voltage conversion circuit 8, and then may output a clock signal of 32.768 KHz.
In the exemplary embodiment of the present invention, in particular, the second amplifier X2 provides an amplification function, and can amplify and output the square wave of the output signal XOUT of the first amplifier 1. The output square wave can be a clock signal of 32.768KHz directly, or the square wave can be subjected to voltage conversion and then output a clock signal CLKOUT of 32.768 KHz.
In an exemplary embodiment of the present invention, the crystal oscillator circuit may further include: a main control circuit 5;
the main control circuit 5 may be connected to the signal output end of the first amplifier 1, and may be configured to determine the magnitude of the amplitude of the clock signal according to a magnitude relationship between the output voltage XOUT of the signal output end of the first amplifier 1 and a preset lower voltage threshold VREFL and an upper voltage threshold VREFH when N is greater than or equal to 2, and determine that the number N of the first MOS circuits a connected to the first amplifier increases or decreases according to a determination result; and may indicate the group number of the first MOS circuit a accessed. This scheme is the auto-calibration algorithm described above.
In the exemplary embodiment of the present invention, how many groups of first MOS circuits a are accessed in the first amplifier 1 in total can be determined by the calculation result SEL < M > of the CAL circuit (i.e., the calculation circuit, which can be realized by the main control circuit 5).
In the exemplary embodiment of the present invention, for example, when SEL < M > is 1, it is described that the number N of first MOS circuits a that can access the circuit of the first amplifier 1 in the plurality of (e.g., M total) first MOS circuits a provided in the first amplifier 1 is added to 1, and at this time, the CAL circuit may add 1 to the number N of first MOS circuits a accessed through the corresponding counter until the sum (N) of the number of first MOS circuits a accessed reaches the total number M of first MOS circuits a provided in the first amplifier 1, where M is a positive integer, M ≧ N, and if the calculation result is still SEL < M > 1 at this time, error reporting information may be sent.
In the exemplary embodiment of the present invention, for example, when SEL < M > is 0, it is described that the number N of first MOS circuits a that can be connected to the circuit of the first amplifier 1 among the plurality of (e.g., M total) first MOS circuits a provided in the first amplifier 1 may be reduced by 1, and at this time, the CAL circuit may reduce 1 by the corresponding counter for the number N of first MOS circuits a connected until the sum (N) of the number of first MOS circuits a connected is 0, and if the calculation result is still SEL < M > is 0 at this time, error information may be sent.
In the exemplary embodiment of the present invention, after determining whether the number N of the first MOS circuits a accessing the circuit of the first amplifier 1 is increased or decreased, which one of the set M sets of the first MOS circuits a is increased may be determined according to a specific value of < M > in SEL < M >, that is, the set number of the accessed or disconnected first MOS circuit a may be determined in the form of SEL < i >, i is a positive integer, i is not more than M; the SEL < i > is a calculation result of the i-th group first MOS circuit a among the M groups of first MOS circuits a provided in the first amplifier 1, and when SEL < i > is 1, it indicates that the i-th group first MOS circuit a is accessible, and when SEL < i > is 0, it indicates that the i-th group first MOS circuit a is not accessible (if the i-th group first MOS circuit a is already accessed into the circuit of the first amplifier 1, the i-th group first MOS circuit a may be disconnected).
In the exemplary embodiment of the present invention, the main control circuit 5 may determine which of the next sets of the first MOS circuits a that can be connected or disconnected is according to the group number of the first MOS circuit a connected to the circuit of the first amplifier 1. For example, if the 1 st to 3 rd groups of the first MOS circuits a have already been incorporated into the circuit of the first amplifier 1, when it is determined that one group of the first MOS circuits a can be added, the 4 th group of the first MOS circuits a can be incorporated into the circuit of the first amplifier 1 in the order of the group numbers; when it is determined that one set of the first MOS circuits a can be reduced, the 3 rd set of the first MOS circuits a can be disconnected from the circuit of the first amplifier 1 in the order of the set numbers.
In an exemplary embodiment of the present invention, as shown in fig. 3, a first control switch K1 may be connected in series between the source of the first PMOS transistor P1 and the input power VDD _ RTC of the first amplifier 1; and/or a second control switch K2 can be connected in series between the source of the first NMOS transistor N1 and the ground;
the master circuit 5 may be connected to the first control switch K1 and/or the second control switch K2 in each first MOS circuit a, and may be configured to control the first control switch K1 and/or the second control switch K2 in one or more first MOS circuits a to be closed or opened according to a determination result of increasing or decreasing the number N of connected first MOS circuits, so as to increase or decrease the number N of parallel first MOS circuits a in the first amplifier 1.
In the exemplary embodiment of the present invention, the first control switch K1 and the second control switch K2 may be controlled switches, and the controlled end of the first control switch K1 and/or the second control switch K2 may be connected to the main control circuit 5.
In the exemplary embodiment of the present invention, when the main control circuit 5 calculates SEL < i > 1 or SEL < i > 0, the first control switch K1 and the second control switch K2 of the first MOS circuit a of the ith group may be controlled to be closed or opened, thereby realizing the connection or disconnection of the first MOS circuit a of the ith group.
In an exemplary embodiment of the present invention, as shown in fig. 5, the crystal oscillator circuit may further include a first comparator 6 and a second comparator 7;
the main control circuit 5 can be connected with the signal output end of the first amplifier 1 through the first comparator 6 and the second comparator 7;
the first comparator 6 may be configured to compare the output voltage XOUT of the signal output terminal of the first amplifier 1 with the lower voltage limit threshold VREFL, and output a first clock signal CLKL according to a magnitude relationship between the output voltage XOUT and the lower voltage limit threshold VREFL; inputting the first clock signal CLKL into the main control circuit 5 as a first judgment basis for increasing or decreasing the number N of the first MOS circuits a accessed in the first amplifier 1;
the second comparator 7 may be configured to compare the output voltage XOUT at the signal output terminal of the first amplifier 1 with the upper voltage limit threshold VREFH, and output a second clock signal CLKH according to a magnitude relationship between the output voltage XOUT and the upper voltage limit threshold VREFH; the second clock signal is input to the main control circuit 5 as a second determination criterion for increasing or decreasing the number N of the first MOS circuits a connected to the first amplifier 1.
The main control circuit 5 is further configured to determine whether the number N of the first MOS circuits a accessed in the first amplifier 1 increases or decreases according to the first determination criterion and the second determination criterion.
In an exemplary embodiment of the present invention, the main control circuit 5 is connected to the first output terminal CLKL of the first comparator 6 and the second output terminal CLKH of the second comparator 7;
a first input end of the first comparator 6 and a second input end of the second comparator 7 are both connected with a signal output end (XOUT output end) of the first amplifier;
the third input end of the first comparator 6 is the input end of the lower voltage limit threshold VREFL;
the fourth input terminal of the second comparator 7 is the input terminal of the upper voltage threshold VREFH.
In an exemplary embodiment of the present invention, the first comparator 6(comparator1) and the second comparator 7(comparator2) may monitor the magnitude of XOUT in real time, when the magnitude of XOUT is greater than the upper voltage limit threshold VREFH, CLKH may output a clock signal of 32.768KHz, and if the magnitude of XOUT is less than the upper voltage limit threshold VREFH, CLKH may output no clock; similarly, CLKL can have a 32.768KHz clock output when XOUT has a magnitude greater than the lower voltage threshold VREFL, as can be seen from table one, only three states exist.
In the exemplary embodiment of the present invention, as shown in table one, when the state of the crystal oscillator outputting the clock signal is in a small amplitude, it indicates that the power consumption is too small at this time, the crystal oscillator may not maintain oscillation, and the number N of the first MOS circuits a that are connected may be increased, for example, the value of N is changed from 7 to 8; when the state of the clock signal output by the crystal oscillator is too large, the power consumption is too large, the number N of the first MOS circuits A which are accessed can be reduced, and the power consumption is reduced, for example, the numerical value of N is changed from 8 to 7; when the state of the clock signal output by the crystal oscillator is moderate in amplitude, the state is just required by normal operation, and the current compromise between amplitude and power consumption can be realized.
In the exemplary embodiment of the present invention, whether CLKH and CLKL have clock outputs can be checked by CLKOUT, and the specific scheme is, for example: after the CLKOUT counts up to Z periods, if the period number of the CLKH is more than Z +2, the amplitude of the 32.768KHz clock output by the CLKHz is considered to be larger; when the period number of CLKL is less than Z-2, the amplitude is considered to be smaller; when the cycle number of CLKL is more than or equal to Z-2 and the cycle number of CLKH is less than or equal to Z +2, the amplitude is considered normal; z +2 and Z-2 refer to tolerances that allow for 2 (and other values may be changed as desired) counting errors.
In the exemplary embodiment of the present invention, when the auto-calibration algorithm is just started, all of the M sets of first MOS transistor circuits a provided in the first amplifier 1 may be connected to the circuit of the first amplifier 1 (all of the connection flags RST may be set, and when RST is equal to 0, all of the M sets of first MOS transistor circuits a may be connected to the circuit of the first amplifier 1), so as to ensure that the crystal oscillator can be started quickly. When CLKH has a clock output and S (S is a positive integer greater than or equal to 1) cycles are counted, CLKOUT is considered to have a clock output, CLKOUT can be used to check the clock condition of CLKH and CLKL, and to start using an auto-calibration algorithm to calculate the number N of first MOS transistor circuits a that need to be accessed in the first amplifier 1.
In the description of the present invention, it should be noted that the terms "upper", "lower", "one side", "the other side", "one end", "the other end", "side", "opposite", "four corners", "periphery", "mouth" word structure "and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for convenience of description and simplification of the description, but do not indicate or imply that the structure referred to has a specific orientation, is constructed and operated in a specific orientation, and thus, is not to be construed as limiting the present invention.
In the description of the embodiments of the present invention, unless otherwise explicitly specified or limited, the terms "connected," "directly connected," "indirectly connected," "fixedly connected," "mounted," and "assembled" are to be construed broadly and may, for example, be fixedly connected, detachably connected, or integrally connected; the terms "mounted," "connected," and "fixedly connected" may be directly connected or indirectly connected through intervening media, or may be connected through two elements. The specific meaning of the above terms in the present invention can be understood in specific cases to those skilled in the art.
Although the embodiments of the present invention have been described above, the description is only for the convenience of understanding the present invention, and the present invention is not limited thereto. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (10)
1. A crystal oscillator circuit, comprising: the low dropout regulator (LDO) comprises a first amplifier, a second amplifier and a low dropout regulator (LDO); the signal output end of the first amplifier is connected with the signal input end of the second amplifier; a crystal is connected in parallel between the signal input end and the signal output end of the first amplifier; a first capacitor is connected in series between a signal input end of the first amplifier and the ground, and a second capacitor is connected in series between a signal output end of the first amplifier and the ground; the signal output end of the second amplifier is a clock signal output end of the crystal oscillator circuit;
the first amplifier comprises N first MOS circuits which are connected in parallel, wherein N is more than or equal to 1 and is a positive integer; the first MOS circuit includes: at least one first PMOS tube and at least one first NMOS tube; the at least one first PMOS tube and the at least one first NMOS tube are connected in series;
the LDO is configured to provide a power supply voltage to the first amplifier and the second amplifier after stabilizing an external power supply.
2. The crystal oscillator circuit of claim 1, wherein a first diode is connected to the source and drain of the first PMOS transistor, and a second diode is connected to the source and drain of the first NMOS transistor;
the source electrode of the first PMOS tube is connected with the input power supply of the first amplifier;
the drain electrode of the first PMOS tube is connected with the drain electrode of the first NMOS tube and then serves as a signal output end of the first amplifier;
the source electrode of the first NMOS tube is grounded;
and the grid electrode of the first PMOS tube is connected with the grid electrode of the first NMOS tube and then is used as the signal input end of the first amplifier.
3. The crystal oscillator circuit of claim 2, wherein a first resistor is connected in series between the drain of the first PMOS transistor and the gate of the first PMOS transistor.
4. The crystal oscillator circuit of claim 2, further comprising: a master control circuit;
and the main control circuit is connected with the signal output end of the first amplifier.
5. The crystal oscillator circuit of claim 4, wherein a first control switch is connected in series between the source of the first PMOS transistor and the first amplifier input power supply; and/or a second control switch is connected in series between the source electrode of the first NMOS tube and the ground;
the main control circuit is connected with the first control switch and/or the second control switch in each first MOS circuit.
6. The crystal oscillator circuit of claim 4, further comprising a first comparator and a second comparator;
the main control circuit is connected with the signal output end of the first amplifier through the first comparator and the second comparator.
7. The crystal oscillator circuit of claim 6 wherein the master circuit is coupled to the first output of the first comparator and the second output of the second comparator;
a first input end of the first comparator and a second input end of the second comparator are both connected with a signal output end of the first amplifier;
a third input end of the first comparator is an input end of a voltage lower limit threshold;
and the fourth input end of the second comparator is the input end of the voltage upper limit threshold value.
8. The crystal oscillator circuit of claim 1, wherein the LDO comprises: a first voltage input terminal and a first voltage output terminal;
the first voltage input end is connected with an external input power supply;
the first voltage output end is respectively connected with the power supply input ends of the first amplifier and the second amplifier and is set to output the power supply voltages of the first amplifier and the second amplifier.
9. The crystal oscillator circuit of claim 8, wherein the LDO further comprises: a second voltage input terminal, a second voltage output terminal and a third voltage output terminal;
the second voltage input end is connected with the voltage output end of a second MOS circuit, and the second MOS circuit is set to generate a lower voltage threshold and an upper voltage threshold which are used for calculating the number N of the first MOS circuits;
the second voltage output end is set to output the lower voltage limit threshold;
the third voltage output end is set to output the voltage upper limit threshold value.
10. The crystal oscillator circuit of claim 9, wherein the second MOS circuit comprises: a second PMOS tube and a second NMOS tube; the source electrode and the drain electrode of the second PMOS tube are connected with a third diode, and the source electrode and the drain electrode of the second NMOS tube are connected with a fourth diode;
the source electrode of the second PMOS tube is an input end of preset current;
the drain electrode of the second PMOS tube is connected with the drain electrode of the second NMOS tube;
the source electrode of the second NMOS tube is grounded;
and the drain electrode of the second PMOS tube, the grid electrode of the second PMOS tube and the grid electrode of the second NMOS tube are connected and then serve as the voltage output end of the second MOS circuit.
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| CN202020651623.6U CN212518916U (en) | 2020-04-26 | 2020-04-26 | Crystal oscillator circuit |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202020651623.6U CN212518916U (en) | 2020-04-26 | 2020-04-26 | Crystal oscillator circuit |
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| CN212518916U true CN212518916U (en) | 2021-02-09 |
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Address after: 201210 whole floor, 8th floor, No. 1, Lane 500, shengxia Road, China (Shanghai) pilot Free Trade Zone, Pudong New Area, Shanghai Patentee after: Core and material (Shanghai) Technology Co.,Ltd. Patentee after: Hexin Xingtong Technology (Beijing) Co., Ltd Address before: 200122 3rd floor, building 8, Lane 912, Bibo Road, Pudong New Area, Shanghai Patentee before: UNICORECOMM (SHANGHAI) TECHNOLOGY CO.,LTD. Patentee before: Hexin Xingtong Technology (Beijing) Co., Ltd |