CN212434646U - LED chip - Google Patents

Abstract

The patent discloses an LED chip, which is characterized by comprising a substrate and an epitaxial layer, wherein the epitaxial layer is arranged on the substrate and comprises a P-type semiconductor material layer, an N-type semiconductor material layer and an active layer; the pattern unit is arranged on the side edge of at least one layer of the epitaxial layer; the pattern unit includes a relief pattern formed on a side of the substrate, the relief pattern having a diameter of less than 10 microns, the pattern unit being repeatedly disposed on the side. The mode adjusts the side wall of the chip to avoid total reflection when the side wall emits light, and meanwhile, the light emitting area of the side wall is increased, so that the light emitting efficiency of the chip is effectively improved, and meanwhile, the improvement is applicable to various chips with etching processes and full-wave-band chips.

Description

LED chip

Technical Field

The patent relates to the technical field of semiconductor devices, in particular to an LED chip.

Background

Solid state lighting sources for Light Emitting Diodes (LEDs) are sought after for their low power consumption, long life, small size, and high reliability. However, the GaN-based LED has a very large drawback in that its luminous efficiency is low. The internal quantum efficiency of GaN-based LEDs has reached 90%, while the external quantum efficiency of conventional LEDs is only 5% due to the influence of total reflection. The external quantum efficiency is the product of the internal quantum efficiency and the extraction efficiency, and the luminous efficiency is mainly limited by the external quantum efficiency. Photons emitted from the LED active layer need to penetrate the inside of the device to reach the air. The refraction of the GaN material is 2.4, the index of refraction of air is 1.0, the angle of total reflection is 24.5, and photons larger than the angle of total reflection will be reflected back (Hao M, Egawa T, Ishikawa H.high hly effective GaNbasal light emitting diodes with micro pits [ J ]. appl.Phys.Lett., 2006,89: 241907).

For the conventional rectangular cavity structure LED, the structure is shown in FIG. 1, photons larger than the total reflection angle are reflected back and forth multiple times in the device, during the multiple reflection process, some photons reach the side surface of the device and exit through the side surface, some photons cannot exit all the time during the multiple reflection process and are finally absorbed, theoretically, only about 20% of photons can exit from the device (Windisch R, Dutta B, Kuijk M, et al, 40% effective thin film surface structured light emitting diodes by optimization of natural variation [ J ] Electron Devices,2000,47: 1492-. To allow more photons to escape, the surface of the device may be roughened (Fujii T, Gao Y, Nakamur a S, et al, incorporated in the extraction efficiency of GaN based light emitting diodes, surface roughening [ J ]. appl. Phys. Lett.,2004,84(6): 855) 857).

Aiming at the traditional GaAs-based LED devices, the surface can be effectively roughened by a natural photoetching and ICP etching method (Dubiao, Liubaolin. side surface roughening for improving the light-emitting efficiency of the GaN-based LED research [ J ]. semiconductor photoelectricity, 2011, 32 (3): 352-. However, for the GaN-based LED, since the p-type layer is very thin and the etching depth is not easy to control, the device is damaged greatly after etching, and it is difficult to realize commercial application (leifen GaN-based LED surface roughening structure preparation technology research [ D ]; university of west ampere electronics science and technology; 2011). Therefore, it is not a good method to roughen the side surface of the device to improve the light emitting efficiency.

Disclosure of Invention

The invention aims to provide an epitaxial structure capable of effectively improving light extraction from the side surface of an LED, and the structure can improve the light extraction rate of a light-emitting diode chip.

In order to solve the technical problem, the technical scheme provided by the patent comprises the following steps:

the LED chip is characterized by comprising a substrate, an epitaxial layer, a first conducting layer, a second conducting layer and a third conducting layer, wherein the epitaxial layer is arranged on the substrate and comprises a P-type semiconductor material layer, an N-type semiconductor material layer and an active layer; the pattern unit is arranged on the side edge of at least one layer of the epitaxial layer; the pattern unit includes a relief pattern formed on a side of the substrate, the relief pattern having a diameter of less than 10 microns, the pattern unit being repeatedly disposed on the side.

Preferably, the pattern elements are distributed over the sides of one layer.

Preferably, the side edges of all the layers of the epitaxial layer are filled with the pattern units.

Preferably, the undulating pattern comprises a zigzag shape, convex hemispheres, concave hemispheres or concave-convex connected hemispheres.

Preferably, the LED chip comprises a front-mount LED chip, a flip LED chip, or a vertical LED chip.

Preferably, the radius of the pattern unit is 2 to 10 micrometers.

Preferably, the epitaxial layer is an epitaxial layer of a GaN system.

Preferably, the substrate is a sapphire substrate, a silicon substrate, or a silicon carbide substrate.

Compared with the prior art, the mode only adjusts the side wall of the chip, can avoid total reflection when the side wall emits light, and increases the light emitting area of the side wall, thereby effectively improving the light emitting efficiency of the chip.

Drawings

Fig. 1, fig. 2, fig. 3 and fig. 4 are schematic structural diagrams of a forward-mounted, a flip-chip, a vertical and a high-voltage LED chip, respectively;

FIG. 5 is a light path from the light exit surface under the semicircular side pattern;

FIG. 6 is a light path from the exit surface under the planar side pattern;

FIG. 7 is a schematic diagram of various side patterns;

fig. 8 is a graph comparing the light extraction efficiency of the repeating units for various sizes.

Detailed Description

The technical solution described in this patent includes various embodiments and modifications made on the various embodiments. In the present embodiment, these technical solutions are exemplarily set forth by way of the drawings so that the inventive concept, technical features, effects of the technical features, and the like of the present patent become more apparent through the description of the present embodiment. It should be noted, however, that the scope of protection of the patent should obviously not be limited to what is described in the examples, but can be implemented in various ways under the inventive concept of the patent.

In the description of the present embodiment, attention is paid to the following reading references in order to be able to accurately understand the meaning of the words in the present embodiment:

first, in the drawings of the present patent, the same or corresponding elements will be denoted by the same reference numerals. Therefore, the explanation of the reference numerals or names of the elements, etc., which have been presented before may not be repeated later. Also, in the present embodiment, if the terms "first", "second", etc. are used to modify various elements or elements, the terms "first", "second", etc. do not denote any order but merely distinguish the elements or elements from one another. Furthermore, the singular forms "a", "an" and "the" do not refer to only the singular but also the plural unless the context clearly dictates otherwise.

Further, the inclusion or inclusion should be understood to be an open description that does not exclude the presence of other elements on the basis of the elements already described; further, when a layer, region or component is referred to as being "formed on", "disposed on" another layer, region or component, the layer, region or component may be directly or indirectly formed on the other layer, region or component, and similarly, when a relationship between two elements is expressed using terms such as connection, connection or the like, it may be either directly or indirectly connected without particular limitation. The term "and/or" connects two elements in a relational or an inclusive relationship.

In addition, in order to explain the technical solution of the present patent, the sizes of the elements described in the drawings of the present patent do not represent the dimensional proportional relationship of the actual elements, and the elements may be enlarged or reduced for convenience of expression in the present patent.

Example 1

The specific embodiment provides an LED chip, and the chip adopts a GaN system. Which may be a face-up LED chip (fig. 1), a flip LED chip (fig. 2), a vertical LED chip (fig. 3), or a high voltage LED chip (fig. 4). The layers of these chips are substantially similar in composition but arranged differently.

Taking the flip-chip LED chip illustrated in fig. 2 as an example, the substrate layer 104 may be made of various substrate materials, such as, but not limited to, a silicon substrate, a sapphire substrate, a silicon carbide substrate, and the like. In this embodiment, a sapphire substrate is taken as an example to develop a corresponding technical solution to disclose the specific inventive concept of this patent.

An N-type semiconductor layer 101, a plurality of quantum wells 102, and a P-type semiconductor layer 103 are sequentially formed on a substrate to form an N-P-P double heterostructure. In this configuration, the N-type semiconductor layer 101 may be N-type GaN, and the P-type semiconductor layer 103 may be P-type GaN. The N-type semiconductor layer is connected with an N electrode, and the P-type semiconductor layer 103 is connected with a P electrode; thus, when the current is applied to both electrodes at N, P, the LED chip can generate light.

In the present embodiment, in order to improve the light extraction efficiency of the LED chip, a zigzag or wavy profile is disposed at the side edges of the N-type semiconductor layer 101, the multiple quantum wells 102, and the P-type semiconductor layer 103 of the LED chip.

Since each layer of the LED chip includes a plurality of sides, a curved pattern may be provided on the plurality of sides. A typical pattern configuration is seen in the analysis of fig. 5, which includes a pattern of semi-circles, with a plurality of semi-circles resting adjacent to each other.

Theoretically, the effect of the curved surface pattern on the light emitting path can be seen by referring to fig. 6 and fig. 5. In fig. 6, it is the light path emergence condition of the LED chip layer on the side of the plane in the prior art, and it can be seen from the figure that, for the side of the plane, since the light ray will be reflected or totally reflected on the adjacent surface between the media, the incident light will be totally reflected in fig. 6 and thus cannot emerge from the chip, which will affect the light emergence efficiency of the chip.

When the uniformly-distributed curved surface patterns are formed on the periphery of the chip, as shown in fig. 5, the uniformly-distributed curved surfaces are semicircular, and light rays form a contact surface which is perpendicular to the chip and air at a plurality of angles to be emitted, so that the light rays almost completely pass through the adjacent surface, and the light emitting efficiency can be greatly improved theoretically.

Different from coarsening in the prior art, in the specific embodiment, the uniformly-arranged curved patterns formed on the side surface of the chip are uniformly arranged, and thus, the patterns can be realized by adopting industrialized etching and other modes, so that the patterns formed by etching can not damage the corresponding layers for the layers under the GaN system, and the light path design of the light is more regular under the regular condition, thereby avoiding the mutual interference between the light or the mutual interference between the irregular pattern formation, and being beneficial to improving the light extraction efficiency.

In this embodiment, the uniformly arranged curved pattern includes a plurality of uniformly arranged pattern units, and the pattern units may have various shapes as shown in fig. 7. For example, the pattern units in fig. 7 are convex semicircles, concave-convex connected semicircles, and triangular structures. Theoretically, in the semicircular structure, the incident light from multiple angles is perpendicular to the shape of the adjacent surface, so that the light emitting efficiency is higher. However, there are complicated factors such as manufacturing and precision, and in practical experiments (under 390nm light conditions), the light extraction efficiencies of the cell patterns of different shapes are shown in the following table:

structure of the product	Luminous efficiency (%)
		Planar structure	26.7
Sawtooth structure	34.1
		Convex semi-circle structure	35.96
Concave-convex semicircular structure	36.69
		Concave semicircular structure	36.11

TABLE 1 light extraction efficiency of four structures

Therefore, the light-emitting efficiency of the semicircular repeated patterns connected by the concave and the convex is obviously highest. About one percent higher than the convex half-round structure, which is the most preferred embodiment in the corresponding application. This configuration therefore has an unexpected and outstanding technical effect.

The size of the pattern unit in the curved surface pattern of evenly arranging also can exert an influence to luminous efficiency, but in this patent, the size of pattern unit all limits to the micron level, and this is different from the pattern of nanometer impression, because this patent need avoid the reflection of light path, throws as far as possible, and the pattern of micron level just satisfies above-mentioned requirement.

In the micrometer scale, the smaller the size of the pattern unit, the higher the light extraction efficiency, for example, as shown in fig. 8, the size of the pattern unit is in proportion to the light extraction efficiency, i.e., the light extraction efficiency is the highest when the radius of the pattern unit is 2 micrometers, and the light extraction efficiency is sequentially reduced when the radius of the pattern unit is 4-10 micrometers. For cell radius sizes below 2 microns, there is no experimental data demonstration of response due to the extreme difficulty of machining. From the above experimental data, the optimum pattern unit radius is 2 microns.

Although the above-described embodiment only exemplifies a flip-chip LED chip, the repeating unit pattern of the present embodiment can be applied to a vertical LED chip, a high-voltage LED chip, and a front-mounted LED chip, and the above-described pattern is usually formed only on the side of the quantum well 102 and the P-type semiconductor layer 103 when the repeating unit pattern is used on the front-mounted LED chip due to the limitation of processing.

The experimental data of the embodiment show that the light-emitting efficiency of the chip can be improved by more than 10% by the side wall microstructure technology.

Example 2

An LED chip of this patent is described in embodiment 1, and a manufacturing method of the chip will be described in embodiment 2.

In this embodiment, step one, a GaN epitaxial layer of an LED chip is formed on a substrate.

An N-type semiconductor layer 101, a plurality of quantum wells 102, and a P-type semiconductor layer 103 are sequentially formed on a substrate to form an N-P-P double heterostructure. In this configuration, the N-type semiconductor layer 101 may be N-type GaN, and the P-type semiconductor layer 103 may be P-type GaN. The N-type semiconductor layer is connected with an N electrode, and the P-type semiconductor layer 103 is connected with a P electrode; thus, when the current is applied to both electrodes at N, P, the LED chip can generate light.

And step two, in the ICP etching process, the photoetching layout before ICP etching is adjusted, the edge of the layout is adjusted to be a wavy line or a sawtooth line from a smooth straight line, so that the etched side wall can form a wavy surface or a sawtooth surface, the side wall can avoid total reflection when the side wall emits light, and meanwhile, the light emitting area of the side wall is increased, so that the light emitting efficiency of the chip is effectively improved.

The side edge of the epitaxial layer with the repeated pattern can be manufactured by adopting a simple scheme through the steps, so that the light emitting efficiency of the LED is obviously improved under the condition of not increasing the cost, and the GaN layer cannot be damaged by operations similar to coarsening and the like.

Having shown and described the basic principles and principal features of this patent, and its advantages, it will be apparent to those skilled in the art that the patent is not limited to the details of the foregoing exemplary embodiments, but is capable of being embodied in other specific forms without departing from the spirit or essential characteristics thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the patent being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.

Furthermore, it should be understood that although the present description refers to embodiments, the embodiments do not include only one independent technical solution, and such description is only for clarity, and those skilled in the art should take the description as a whole, and the technical solutions in the embodiments may be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims (8)

1. An LED chip, comprising

A substrate, a first electrode and a second electrode,

the epitaxial layer is arranged on the substrate and comprises a P-type semiconductor material layer, an N-type semiconductor material layer and an active layer;

the pattern unit is arranged on the side edge of at least one layer of the epitaxial layer; the pattern unit includes a relief pattern formed on a side of the substrate, the relief pattern having a diameter of less than 10 microns, the pattern unit being repeatedly disposed on the side.

2. The LED chip of claim 1, wherein said pattern elements are disposed over the sides of a layer.

3. The LED chip of claim 1, wherein the pattern elements are filled on the sides of all layers of the epitaxial layer.

4. The LED chip of claim 1, wherein said relief pattern comprises a saw-tooth shape, a convex hemisphere shape, a concave hemisphere shape, or a concave-convex connected hemisphere shape.

5. The LED chip of claim 1, wherein said LED chip comprises a face-up LED chip, a flip LED chip, or a vertical LED chip.

6. The LED chip of claim 1, wherein the radius of said pattern unit is 2-10 μm.

7. The LED chip of claim 1, wherein said epitaxial layer is a GaN system epitaxial layer.

8. The LED chip of claim 1, wherein said substrate is a sapphire substrate, a silicon substrate, or a silicon carbide substrate.

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