CN212392001U - Transmission circuit, interface circuit, and memory - Google Patents

Abstract

The embodiment of the utility model provides a transmission circuit, interface circuit and memory, transmission circuit includes: the upper layer clock bonding pad is used for transmitting clock signals; m upper layer data pads for transmitting data signals; the lower layer clock bonding pad is electrically connected with the upper layer clock bonding pad, and the area of the lower layer clock bonding pad is smaller than that of the upper layer clock bonding pad; the M lower-layer data bonding pads are electrically connected with the M upper-layer data bonding pads in a one-to-one correspondence manner, and the area of each lower-layer data bonding pad is smaller than that of each upper-layer data bonding pad; the upper clock bonding pad and the upper data bonding pad are located on a first layer, the lower clock bonding pad and the lower data bonding pad are located on a second layer, a dielectric layer is arranged between the first layer and the second layer, and the first layer, the dielectric layer and the second layer are all located on the same substrate. The embodiment of the utility model provides a be favorable to shortening the clock path length that each input buffer circuit corresponds, reduce the chronogenesis violation, improve the clock path that each input buffer circuit corresponds and the matching degree of input data route.

Description

Transmission circuit, interface circuit, and memory

Technical Field

The embodiment of the utility model provides a relate to the semiconductor technology field, in particular to transmission circuit, interface circuit and memory.

Background

Dynamic Random Access Memory (DRAM) is a semiconductor Memory device commonly used in computers, and is composed of many repetitive Memory cells. Each memory cell generally includes a capacitor and a transistor, a gate of the transistor is connected to a word line, a drain of the transistor is connected to a bit line, and a source of the transistor is connected to the capacitor, and a voltage signal on the word line can control the transistor to be turned on or off, so that data information stored in the capacitor can be read through the bit line or written into the capacitor through the bit line for storage.

The DRAM may be classified into a Double Data Rate (DDR) DRAM, a gddr (graphics Double Data Rate) DRAM, and a Low Power Double Data Rate (LPDDR) DRAM. With the increasing application fields of DRAM, such as the increasing application of DRAM to mobile fields, the demands of users on DRAM power consumption indexes are higher and higher.

However, the performance of current DRAMs is still to be improved.

SUMMERY OF THE UTILITY MODEL

The embodiment of the utility model provides a technical problem who solves for providing a transmission circuit, interface circuit and contributing the year, realizes centralized processing through setting up lower floor clock pad and lower floor data pad to realize the optimization of key clock, thereby improve clock performance and reduce power loss.

In order to solve the above problem, an embodiment of the present invention provides a transmission circuit, including: the upper layer clock bonding pad is used for transmitting clock signals; m upper layer data pads for transmitting data signals; the lower-layer clock bonding pad is electrically connected with the upper-layer clock bonding pad, and the area of the lower-layer clock bonding pad is smaller than that of the upper-layer clock bonding pad; the M lower-layer data bonding pads are electrically connected with the M upper-layer data bonding pads in a one-to-one correspondence manner, and the area of each lower-layer data bonding pad is smaller than that of each upper-layer data bonding pad; the upper clock pad and the upper data pad are located on a first layer, the lower clock pad and the lower data pad are located on a second layer, a dielectric layer is arranged between the first layer and the second layer, the first layer, the dielectric layer and the second layer are all located on the same substrate, and M is an integer greater than or equal to 2.

In addition, still include: the first metal connecting wire is positioned between the lower layer clock bonding pad and the upper layer clock bonding pad; and the second metal connecting wire is positioned between any one of the lower data bonding pad and the upper data bonding pad corresponding to the lower data bonding pad, and the length of the first metal connecting wire is smaller than that of the second metal connecting wire.

In addition, the first metal line includes: the first conductive hole penetrates through the dielectric layer and is in contact with the lower clock pad; the first metal layer is positioned on one side of the dielectric layer, which is far away from the first layer, and is in contact with the first conductive hole and the upper clock pad; the second metal connecting line comprises: the second conductive hole penetrates through the dielectric layer and is in contact with the lower data pad; the second metal layer is positioned on one side of the dielectric layer, which is far away from the first layer, and is in contact with the second conductive hole and the upper data pad; the length of the first conductive hole is the same as that of the second conductive hole, and the length of the first metal layer is smaller than that of the second metal layer.

In addition, the first metal line includes: the first conductive plug penetrates through the dielectric layer and is in contact with the lower clock pad and the upper clock pad; the second metal connecting line comprises: and the second conductive plug penetrates through the dielectric layer and is in contact with the lower data pad and the upper data pad, and the length of the first conductive plug is smaller than that of the second conductive plug.

In addition, the areas of the lower clock pad and the lower data pad are the same.

In addition, still include: the lower-layer test pads have the same area, and the area of the lower-layer test pads is larger than that of the lower-layer data pads.

In addition, the upper clock pad and the M upper data pads are arranged in a first row, and the M upper data pads are arranged on both sides of the upper clock pad, each side arranged with half of the M upper data pads.

In addition, the lower layer clock pad with M lower layer data pads arranges in the second row, just M lower layer data pads arrange in the both sides of lower layer clock pad, each side arrange half of M lower layer data pads.

Correspondingly, the embodiment of the utility model provides a still provide an interface circuit, include foretell transmission circuit; the M input buffer circuits are in one-to-one correspondence with the lower data bonding pads, and each input buffer circuit is driven by the clock signal to receive the data signal transmitted by the lower data bonding pad corresponding to the input buffer circuit; wherein, lower floor's clock pad with lower floor's data pad arranges in first row, just M lower floor's data pad arrange in the both sides of lower floor's clock pad, each side is arranged half of M lower floor's data pad, M input buffer circuit arranges in the second row, with lower floor's data pad is the benchmark, forms the perpendicular to the axis of first row, M input buffer circuit arrange in the both sides of axis, each side is arranged half of M input buffer circuit, each input buffer circuit with the distance of axis is less than input buffer circuit corresponds lower floor's data pad with the distance of axis.

In addition, the path length of input data from each input buffer circuit to the upper layer clock pad corresponding to the input buffer circuit is a first length, the path length of clock between each input buffer circuit and the upper layer clock pad is a second length, and the first length is positively correlated with the second length.

In addition, the lower clock pad is a differential input pad and comprises a first lower clock pad and a second lower clock pad, and the first lower clock pad and the second lower clock pad respectively transmit complementary clock signals.

In addition, the first lower clock pad and the second lower clock pad are symmetrically arranged with respect to the axis.

In addition, still include: and the clock processing circuit is electrically connected with the lower layer clock bonding pad and the M input buffer circuits, and is used for receiving the clock signal and processing the clock signal to be used as a driving clock of the M input buffer circuits.

In addition, the clock processing circuit includes a clock receiving circuit electrically connected to the lower clock pad for receiving the clock signal, an output of the clock receiving circuit serving as an input of the phase generating circuit, and a phase generating circuit for generating the driving clock.

In addition, still include: an upper layer flag pad for transmitting a flag signal, the upper layer flag pad being located on the first layer; the lower layer mark bonding pad is electrically connected with the upper layer mark bonding pad, the lower layer mark bonding pad is positioned on the second layer, and the area of the lower layer mark bonding pad is smaller than that of the upper layer mark bonding pad; and the mark buffer circuit corresponds to the lower mark pad and is used for receiving the mark signal transmitted by the upper mark pad under the driving of the clock signal.

In addition, the lower layer mark pad is arranged in the first row and is positioned between the lower layer data pad and the lower layer clock pad; the mark buffer circuit is arranged in the second row, is positioned on the same side of the axis as the lower mark pad and is positioned between the input buffer circuit and the axis; the distance between the mark buffer circuit and the axis is smaller than the distance between the lower layer mark pad corresponding to the mark buffer circuit and the axis.

In addition, still include: and the M output buffer circuits are in one-to-one correspondence with the lower-layer data bonding pads, and each output buffer circuit is driven by the clock signal to send the data signal to the corresponding lower-layer data bonding pad.

In addition, the output data path length from each output buffer circuit to the lower layer data pad corresponding to the output buffer circuit is the same.

In addition, the input buffer circuit comprises a multiplexer and a latch, the multiplexer receives the data signal, processes the data signal and outputs the processed data signal to the latch, and the output of the latch is used as the output of the input buffer circuit.

Correspondingly, the embodiment of the present invention further provides a memory, including the above-mentioned interface circuit.

Compared with the prior art, the embodiment of the utility model provides a technical scheme has following advantage:

the embodiment of the utility model provides a transmission circuit that structural performance is superior, M upper strata data pad and upper clock pad are located the first layer, and M lower floor's data pad and lower floor's clock pad are located the second floor, and the area of lower floor's clock pad is less than the area of upper clock pad, and the area of lower floor's data pad is less than the area of upper strata data pad. Therefore, compared with the position relationship between the upper data pad and the upper clock pad, the distance between the lower data pad and the lower clock pad is shorter, so that the centralized processing of the lower data pad is realized, the centralized processing of the input buffer circuit can be realized, the clock path for transmitting the clock signal to each input buffer circuit is shortened, the matching degree of the clock path and the data path is improved, and the tDQS2DQ or tWCK2DQ and the timing violation are reduced; in addition, the power consumption of the interface circuit is reduced due to the reduction of the clock path.

Drawings

One or more embodiments are illustrated by way of example in the accompanying drawings, which correspond to the figures in which like reference numerals refer to similar elements and which are not to scale unless otherwise specified.

FIG. 1 is a schematic diagram of an interface circuit;

fig. 2 is a schematic diagram of an equivalent circuit layout of a transmission circuit according to an embodiment of the present invention;

FIG. 3 is a schematic cross-sectional view of an on die RDL;

fig. 4 is a schematic partial cross-sectional structure diagram of a transmission circuit provided in this embodiment;

fig. 5 is a schematic structural diagram of an interface circuit according to an embodiment of the present invention;

fig. 6 is a schematic diagram of an interface circuit according to an embodiment of the present invention;

fig. 7 is another layout diagram of an interface circuit according to an embodiment of the present invention.

Detailed Description

As is known in the art, the performance of the prior art DRAM still remains to be improved.

In the memory, the write data sampling signal (Dqs signal or Wck signal) serves as a clock for write data; at the time of a write operation, the edges (rising and falling) of the Dqs signal or Wck should be aligned in timing with the center of the data signal (DQ signal) (substantial alignment at the center may also be allowed in view of timing margins). The transmission path of the DQ signal is defined as a data path, the length of the data path affects the time when the edge of the DQ signal reaches a device port (e.g., a data port of a register), the transmission path of Dqs or Wck is defined as a clock path, the length of the clock path affects the time when the Dqs or Wck signal reaches the device port (e.g., a clock port of a register), the difference between the data path of the DQ signal and the clock path of the Dqs or Wck signal (the time interval between the edge of the Dqs or Wck signal and the center of the DQ signal) is defined as tDQS2DQ or tdck 2DQ, the smaller the tDQS2DQ or tdck 2DQ, the better the matching between the data path and the clock path, and the better the corresponding circuit timing. Wck has the same or similar application as Dqs, for example, the clock is referred to as Dqs in LPDDR4 and Wck in LPDDR 5.

Now, a detailed analysis is performed with reference to fig. 1, and fig. 1 is a schematic structural diagram of an interface circuit.

Referring to fig. 1, the interface circuit includes: a plurality of data pads 11 arranged side by side for transmitting data signals, a central axis AA1, and half of the plurality of data pads 11 are distributed on one side of the central axis AA1, and the other half are distributed on the other side of the central axis AA 1; a clock pad 13, the clock pad 13 being located at the central axis AA 1; a plurality of input buffer circuits 14 corresponding to the data pads 11, and the data path from each input buffer circuit 14 to the corresponding data pad 11 is the same (or substantially the same within a certain error range, considering that the same path is only an ideal case in the actual circuit design and manufacturing process, the same path here and below includes substantially the same meaning within a certain error range, and a certain error range here can be understood but not limited to the error between different paths being within 1% or within 3%); a plurality of output buffer circuits (not shown) corresponding to the data pads 101, and each having the same timing path to the corresponding data pad 11; a clock receiving circuit 16 and a clock generating circuit 17, the clock receiving circuit 16 is electrically connected to the clock pad 13 for receiving a clock signal and transmitting the clock signal to the clock generating circuit 17, the clock generating circuit 17 receives the clock signal and generates a driving clock, and the input buffer circuit 14 receives the driving clock and a data signal and transmits a data signal.

In fig. 1, DQ0/DQ1 … DQ7 denotes the data pad 11, CLK denotes the clock pad 13, CLK may be represented as Dqs or Wck, RX0/RX1 … RX7 denotes the input buffer circuit 14, the input buffer circuit 14 is also a receiving circuit, RX _ CLK denotes the clock receiving circuit 16, and CLK GEN denotes the clock generating circuit 17.

The data path through which the data signal of the data pad 11 is transmitted to the corresponding input buffer circuit 14 is a first path, and the timing path through which the clock signal of the clock pad is transmitted to the corresponding input buffer circuit 14 is a second path. In fig. 1, different input buffer circuits 14 have the same first path, but the input buffer circuits 14 farther from the clock pad have longer second paths, and therefore, the farther from the clock pad, the larger the difference between the respective first paths and the second paths, resulting in the larger the corresponding tDQS2DQ or tvck 2DQ, and the more serious the problem of timing violations, fig. 1 shows the corresponding tDQS2DQ or tvck 2DQ of the input buffer circuit 14 farthest from the clock pad.

The data signals of different data pads 11 arrive at the corresponding input buffer circuits 14 close to each other, and taking the input buffer circuit 14 farthest from the clock pad and closest to the clock pad in fig. 1 as an example, the clock signal arrives at the input buffer circuit 14 farthest from the clock pad 13 (the input buffer circuit 14 corresponding to DQ 0) at the latest, and the clock signal arrives at the input buffer circuit 14 closest to the clock pad (the input buffer circuit 14 corresponding to DQ 3) at the earliest, which results in that the input buffer circuit 14 closest to the clock pad receives and transmits the data signal first, and the input buffer circuit 14 farthest from the clock pad transmits the data signal at the latest, and the time difference between the data signals transmitted by the two input buffer circuits 14 is large. Accordingly, if the clock path of the input buffer circuit 14 corresponding to DQ3 matches the data path, then the clock path of the input buffer circuit 14 corresponding to DQ0 does not match the data path as easily.

Specifically, referring to fig. 1, each data pad 11 has a first port d0/d1 … … d7, each input buffer circuit 14 has a second port r0/r1 … r7 connected to the first port of the corresponding data pad 11, each input buffer circuit 14 has a third port v0/v1 … v7 connected to the clock generation circuit 17, the clock generation circuit 17 has a fourth port c0 connected to each input buffer circuit 14 on one side of the central axis AA1, and the clock generation circuit 17 further has a fifth port c1 connected to each input buffer circuit 14 on the other side of the central axis AA 1. For RX0, the clock path for the clock signal is c0 → v0, and the data path for the data signal is d0 → r 0; for RX1, the clock path for the clock signal is c1 → v1, and the data path for the data signal is d1 → r 1; and so on; it is easy to find that the corresponding data paths do not change for different input buffer circuits 14, but the closer to the central axis AA1 the input buffer circuits 14 have shorter clock paths, and therefore, the problem of large differences in tDQS2DQ or tvck 2DQ arises.

From the above analysis, the difference between tDQS2DQ or tdck 2DQ corresponding to different input buffer circuits 13 is large, and in the memory, there are strict requirements on the value of tDQS2DQ or tdck 2DQ, for example, the value of tDQS2DQ or tdck 2DQ cannot be greater than 800ps, otherwise, timing violation may be caused.

In order to solve the above problem, an embodiment of the present invention provides a transmission circuit, upper clock pad and upper data pad connected with lower floor clock pad and lower floor data pad respectively are designed through the mode of on die RDL (redistribution layer), and the mode of lower floor clock pad and lower floor data pad centralized layout, make each input buffer circuit connected with lower floor data pad also can centralized layout, thereby clock signal transmission to each input buffer circuit's clock route has been shortened, clock signal's clock route and data signal's data route's difference has been shortened, thereby tDQS2DQ or tvck 2DQ has been shortened, further improve the problem of chronogenesis violation. The interface circuit provided in the present embodiment will be described in detail below with reference to the drawings.

Fig. 2 is a schematic diagram of an equivalent circuit layout of a transmission circuit according to an embodiment of the present invention; FIG. 3 is a schematic cross-sectional view of an on die RDL; fig. 4 is a schematic partial cross-sectional structure diagram of the transmission circuit provided in this embodiment.

Referring to fig. 2 to 4, in the present embodiment, the transmission circuit includes: an upper clock pad 101 for transmitting a clock signal; m upper data pads 102 for transmitting data signals; a lower clock pad 111 electrically connected to the upper clock pad 101, wherein the area of the lower clock pad 111 is smaller than that of the upper clock pad 101; the M lower data bonding pads 112 are electrically connected with the M upper data bonding pads 102 in a one-to-one correspondence manner, and the area of the lower data bonding pad 112 is smaller than that of the upper data bonding pad 102; the upper clock pad 101 and the upper data pad 102 are located on a first layer, the lower clock pad 111 and the lower data pad 112 are located on a second layer, the dielectric layer 103 is included between the first layer and the second layer, the first layer, the dielectric layer 103 and the second layer are all located on the same substrate 100, and M is an integer greater than or equal to 2.

The transmission circuit provided in the present embodiment will be described in detail below with reference to the drawings.

In this embodiment, the transmission circuit can be applied to a DRAM, such as LPDDR 5.

Upper layer clock pad 101 and M upper layer data pads 102 are arranged in a first row and M upper layer data pads 102 are arranged on both sides of upper layer clock pad 101, one half of M upper layer data pads 102 being arranged on each side. The upper layer data pad 102 is a DQ data pad for transmitting a DQ signal, i.e., the data signal includes input and output data. When M is even, e.g., M equals 8, then 4 upper data pads 102 are disposed on each side of axis AA 1; when M is odd, e.g., M equals 7, then 3 upper layer data pads 102 are disposed on one side of axis AA1 and 4 upper layer data pads 102 are disposed on the other side. The term "half" as used above is to be understood as M/2 when M is an even number, and as (M-1)/2 or (M +1)/2 when M is an odd number, the same applies hereinafter.

The 8 upper layer data pads 102 in fig. 2 are taken as an example, and each upper layer data pad 102 is labeled with DQ0, DQ1, DQ2, DQ3, DQ4, DQ5, DQ6, and DA 7. It will be appreciated that in other embodiments, the number of upper layer data pads may be set appropriately according to the actual requirements of the transmission circuit.

The upper clock pad 101 may be used to transmit the CLK signal, i.e., the clock signal is Dqs or the WCK signal, and the Dqs or WCK signal refers to the write clock signal or the read clock signal. Correspondingly, the upper clock pads 101 are differential input pads, and include a first upper clock pad 141 and a second upper clock pad 151, and the first upper clock pad 141 and the second upper clock pad 151 respectively transmit complementary clock signals. Specifically, in fig. 2, a first upper clock pad 141 is denoted by Wckt, and the first upper clock pad 141 is used for transmitting a Wckt clock signal; the second upper clock pad 151 is denoted by Wckc, and the second upper clock pad 151 is used to transmit a Wckc clock signal.

The number of lower clock pads 111 is the same as the number of upper clock pads 101, and the number of lower data pads 112 is the same as the number of upper data packets 102. Specifically, the lower clock pad 111 includes: a first lower clock pad 142 electrically connected to the first upper clock pad 141; the second lower clock pad 152 is electrically connected to the second upper clock pad 151.

In this embodiment, the lower layer clock pad 111 and the M lower layer data pads 112 are arranged in the second row, and the M lower layer data pads 112 are arranged on both sides of the lower layer clock pad 111, and half of the M lower layer data pads 112 are arranged on each side.

It should be noted that the "first layer" does not mean that the upper clock pad 101 and the upper data pad 102 are located in the first layer of the overall structure of the transmission circuit, but merely means that the upper clock pad 101 and the upper data pad 102 are disposed in the same layer in the transmission circuit. In an actual transmission circuit, the upper clock pad 101 and the upper data pad 102 may be located at any layer in the overall structure of the transmission circuit. Similarly, the "second layer" does not mean that the lower clock pad 111 and the lower data pad 112 are located in the second layer of the entire transmission circuit structure, but merely means that the lower clock pad 111 and the lower data pad 112 are provided in the same layer in the transmission circuit and are located in a different layer from the upper clock pad 101 and the upper data pad 102. In an actual transmission circuit, the lower clock pad 111 and the lower data pad 112 may be located at any layer of the overall structure of the transmission circuit, and other functional layers may be further disposed between the first layer and the second layer.

Accordingly, it is to be understood that similar meanings as described above are also satisfied in relation to the "first row" and the "second row".

The distance between each lower data pad 112 and the lower clock pad 111 is a first distance, and the distance between the corresponding upper data pad 102 and the corresponding upper clock pad 101 is a second distance; since the area of the lower data pad 112 is smaller than that of the upper data pad 102 and the area of the lower clock pad 111 is smaller than that of the upper clock pad 101, the first distance is smaller than the second distance, i.e., the lower data pad 112 is closer to the lower clock pad 111 than the upper data pad 102 and the upper clock pad 101.

Compared with the scheme shown in fig. 1, when the transmission circuit in this embodiment is applied to a memory, an input buffer circuit is correspondingly disposed on the lower layer data pad 112, and the clock path of the input buffer circuit farthest from the lower layer clock pad 111 is reduced, so that the clock signal can be transmitted to the input buffer circuit farthest from the lower layer clock pad 111 more quickly, thereby reducing the signal delay time caused by the arrival of the data signal but the non-arrival of the clock signal. Accordingly, the clock path of each input buffer circuit is reduced, and thus the signal delay time of all the input buffer circuits can be reduced accordingly. That is, the present embodiment can reduce tDQS2DQ or tvck 2DQ, reduce timing violations, and reduce power consumed on clock paths.

In addition, compared with the difference between the data path between each upper clock pad 101 and the input buffer circuit and the clock path between each upper data pad 102 and the input buffer circuit, the difference between the corresponding data path between each lower clock pad 111 and the input buffer circuit and the corresponding clock path between each lower data pad 112 and the input buffer circuit is reduced, so that the embodiment can shorten the tDQS2DQ or the tdck 2DQ of different input buffer circuits, thereby improving the matching degree of the clock paths and the data paths of different input buffer circuits, and improving the timing characteristics of the different input buffer circuits for transmitting data signals.

In this embodiment, the area of the lower data pad 112 is the same as the area of the lower clock pad 111. In other embodiments, the area of the underlying data pad may also be greater or less than the area of the underlying clock pad.

The transmission circuit further includes: a first metal connecting line 104, wherein the first metal connecting line 104 is positioned between the lower clock pad 111 and the upper clock pad 101; and a second metal connection 105, wherein the second metal connection 105 is located between any lower data pad 112 and the upper data pad 102 corresponding to the lower data pad 112, and the length of the first metal connection 104 is smaller than that of the second metal connection 105.

Since the length of the first metal line 104 is smaller than that of the second metal line 105, it is beneficial to the centralized layout of the lower clock pad 111.

In this embodiment, the electrical connection between the lower layer clock pad 111 and the upper layer clock pad 101, and the electrical connection between the lower layer data pad 112 and the upper layer data pad 102 are realized in an on die RDL manner.

Fig. 3 is a schematic cross-sectional view of an on die RDL, as shown in fig. 3, including: a first functional layer 1101 and a second functional layer 1102 stacked in this order; a first pad 1103 and a second pad 1104 located within the first functional layer 1101; a first conductive plug 1113 penetrating the second functional layer 1102 and electrically connected to the first pad 1103, and a second conductive plug 1114 penetrating the second functional layer 1102 and electrically connected to the second pad 1104; a first redistribution layer 1123 on the surface of the second functional layer 1102 and electrically connected to the first conductive plugs 1113, and a second redistribution layer 1124 on the surface of the second functional layer 1102 and electrically connected to the second conductive plugs 1114; a first rewiring pad 1133 located on the surface of the second functional layer 1102 and electrically connected to the first rewiring layer 1123, and a second rewiring pad 1134 located on the surface of the second functional layer 1102 and electrically connected to the second rewiring layer 1124. Through the position arrangement of the first conductive plug 1113 and the first rewiring layer 1123, the relative position and size relationship between the first rewiring pad 1133 and the first pad 1103 are reasonably adjusted, and the relative position and size relationship between the second rewiring pad 1134 and the second pad 1104 are also adjusted, so that the size of the first rewiring pad 1133 is larger than that of the first pad 1103, the size of the second rewiring pad 1134 is larger than that of the second pad 1104, and the distance between the first rewiring pad 1133 and the second rewiring pad 1134 is larger than that between the first pad 1103 and the second pad 1104. The first redistribution layer 1123 is much thicker than the metal layer where the first pad 1103 is located, for example, the thickness of the first redistribution layer 1123 is 4um, and the thickness of the metal layer where the first pad 1103 is located is 400 nm.

Specifically, in this embodiment, the first pad 1103 and the second pad 1104 may be lower data pads or lower clock pads, and the first rerouting pad 1133 and the second rerouting pad 1134 may be upper data pads or upper clock pads. Fig. 4 is a schematic partial cross-sectional structure diagram of the transmission circuit provided in this embodiment.

As shown in fig. 4, in one example, the lower clock pad 111 and the lower data pad 112 are located in the substrate layer 100, and the dielectric layer 103 is stacked on the substrate layer 100; the first metal line 104 includes: and a first conductive via 114, wherein the first conductive via 114 penetrates through the dielectric layer 103 and contacts the lower clock pad 111 and the upper clock pad 101. The second metal line 105 includes: a second conductive via 115, the second conductive via 115 penetrating the dielectric layer 103 and contacting the lower data pad 112; and a second metal layer 125, wherein the second metal layer 125 is located on the side of the dielectric layer 103 away from the first layer, and contacts the second conductive via 115 and the upper data pad 102.

The first metal line 104 may further include: and the first metal layer is positioned on the surface of the dielectric layer 103 far away from the substrate layer 100 and is in contact with the first conductive hole 114 and the upper clock pad 101.

Wherein the length of the first conductive via 114 is the same as the length of the second conductive via 115, and the length of the first metal layer is smaller than the length of the second metal layer 125. The cross-sectional shape of the first conductive via 114 can be a straight line, the cross-sectional shape of the second conductive via 115 can be a straight line, and the lengths of the first conductive via 114 and the second conductive via 115 are the same as the thickness of the dielectric layer 103.

In another example, the first metal line 104 may include: the first conductive plug penetrates through the dielectric layer 103 and is in contact with the lower clock pad 111 and the upper clock pad 101; the second metal line 105 includes: and the second conductive plug penetrates through the dielectric layer 103 and is in contact with the lower data pad 112 and the upper data pad 102, and the length of the first conductive plug is smaller than that of the second conductive plug.

Specifically, the cross-sectional shape of the first conductive plug may be a linear structure, the cross-sectional shape of the second conductive plug may be a zigzag structure, the length of the first conductive plug may be the same as the thickness of the dielectric layer, and the length of the second conductive plug may be greater than the thickness of the dielectric layer.

In this embodiment, referring to fig. 2, the transmission circuit may further include: a plurality of lower test pads 106, the plurality of lower test pads 106 having the same area, and the area of the lower test pads 106 being larger than the area of the lower data pads 112. Specifically, the lower layer test pad 106, the lower layer data pad 112, and the lower layer clock pad 111 are disposed on the same layer, and may be used as a test pad for performing a probe test, and a probe needs to be in contact with the lower layer test pad 106 during a test process, so that the lower layer test pad 106 needs to have a relatively large area to reduce a test difficulty. For example, the area of the lower test pad 106 is 60 μm by 60 μm, and the area of the lower data pad 112 is 40 μm by 40 μm.

In the transmission circuit provided by this embodiment, a lower layer clock pad electrically connected to an upper layer clock pad is laid out in an on die RDL manner, and a lower layer data pad electrically connected to an upper layer data pad is laid out, where an area of the lower layer clock pad is smaller than an area of the upper layer clock pad, and an area of the lower layer data pad is smaller than an area of the upper layer data pad; after the input buffer circuits corresponding to the lower data bonding pads are arranged, the length of a clock path required by the transmission of a clock signal to each input buffer circuit is favorably shortened, and the matching degree of the clock path and the data path is improved, so that tDQS2DQ or tWCK2DQ and time sequence violation are reduced. The clock path lengths corresponding to the input buffer circuits have small difference, and the requirement of high matching degree of the clock path and the data path of each input buffer circuit can be met at the same time.

Correspondingly, the embodiment of the present invention further provides an interface circuit, which includes the transmission circuit in the above embodiment, and further includes M input buffer circuits. The interface circuit provided in the present embodiment will be described in detail below with reference to the drawings.

Fig. 5 is a schematic structural diagram of an interface circuit according to an embodiment of the present invention.

Referring to fig. 5, in the present embodiment, the interface circuit includes: an upper clock pad 101 for transmitting a clock signal; m upper data pads 102 for transmitting data signals; a lower clock pad 111 electrically connected to the upper clock pad 101, wherein the area of the lower clock pad 111 is smaller than that of the upper clock pad 101; the M lower data bonding pads 112 are electrically connected with the M upper data bonding pads 102 in a one-to-one correspondence manner, and the area of the lower data bonding pad 112 is smaller than that of the upper data bonding pad 102; the upper clock pad 101 and the upper data pad 102 are located on a first layer, the lower clock pad 111 and the lower data pad 112 are located on a second layer, a dielectric layer 103 is arranged between the first layer and the second layer, the first layer, the dielectric layer 103 and the second layer are all located on the same substrate, and M is an integer greater than or equal to 2; the M input buffer circuits 201 correspond to the lower data pads 112 one by one, and each input buffer circuit 201 receives the data signal transmitted by the lower data pad corresponding to the input buffer circuit under the driving of the clock signal; the lower-layer clock pad 111 and the lower-layer data pad 112 are arranged in a first row, the M lower-layer data pads 112 are arranged on two sides of the lower-layer clock pad 111, half of the M lower-layer data pads 112 are arranged on each side, the M input buffer circuits 201 are arranged in a second row, an axis AA1 perpendicular to the first row is formed by taking the lower-layer data pads 112 as a reference, the M input buffer circuits 201 are arranged on two sides of an axis AA1, half of the M input buffer circuits 201 are arranged on each side, and the distance between each input buffer circuit 201 and the axis is smaller than the distance between the lower-layer data pad 112 corresponding to the input buffer circuit 201 and the axis AA 1.

The interface circuit provided in the present embodiment will be described in detail below with reference to the drawings.

The lower clock pad 111 is a differential input pad, and includes a first lower clock pad 142 and a second lower clock pad 152, and the first lower clock pad 142 and the second lower clock pad 152 respectively transmit complementary clock signals. And the first lower clock pad 142 and the second lower clock pad 152 are symmetrically arranged with respect to the axis AA 1.

In this embodiment, the first lower clock pad 142 and the second lower clock pad 152 are symmetrically arranged with respect to the axis AA 1. The arrangement that the clock paths of the first lower clock pad 142 and the input buffer circuit 201 on one side of the axis AA1 are the first clock path and the clock paths of the second lower clock pad 152 and the input buffer circuit 201 on the other side of the axis AA1 are the second clock path is beneficial to reducing the difference between the first clock path and the second clock path, thereby reducing or avoiding the adverse effect on tDQS2DQ or tvck 2DQ caused by the difference between the first clock path and the second clock path.

It should be noted that, in other embodiments, the first lower clock pad and the second lower clock pad may be disposed on the same side of the axis.

In addition, the "first row" and the "second row" do not refer to the first row and the second row in the pads of the transmission circuit as a whole, but are for explaining that the pads in the first row are in a different row from the pads in the second row.

The interface circuit further includes: and the clock processing circuit 202 is electrically connected with the lower-layer clock pad 111 and the plurality of input buffer circuits 201, and is used for receiving the clock signal and processing the clock signal to be used as the driving clock of the M input buffer circuits 201. The clock processing circuit 202 includes a clock receiving circuit electrically connected to the lower clock pad 111 for receiving the clock signal, an output of the clock receiving circuit serving as an input of a phase generating circuit for generating a driving clock, and a phase generating circuit.

The clock processing circuit 202 is coincident with the axis AA1, i.e., the clock processing circuit 202 is located at the position of the axis AA 1. As such, it is advantageous to reduce the difference in clock paths required to drive the clock to the input buffer circuits 201 on both sides of the axis AA 1. The above-mentioned location of the clock processing circuit 202 on the axis AA1 does not mean that the clock processing circuit 202 is completely symmetrical with respect to the axis AA1, and considering the practical situation of circuit design and manufacture, the clock processing circuit is located approximately at the location of AA1, allowing its center line to deviate from AA1 by a certain amount, for example, by 10% or 20%.

Each input buffer circuit 201 is located directly below a corresponding lower data pad 112. The input buffer circuit 201 receives the data signal driven by the clock signal and continues to transmit the data signal. That is, when the data signal of the upper data pad 102 is transmitted to the input buffer circuit 201, the input buffer circuit 201 will receive the data signal and transmit the data signal only if the clock signal is also transmitted to the input buffer circuit 201; if the data signal is transmitted to the input buffer circuit 201 and the clock signal is not yet reached, the input buffer circuit 201 will not transmit the data signal.

In this embodiment, because the lower data pads 112 are disposed in a centralized manner compared to the upper data pads 102, the distance between each input buffer circuit 201 and the axis AA1 is smaller than the distance between the corresponding upper data pad 102 of the input buffer circuit 201 and the axis AA1, i.e., the input buffer circuits 201 are closer to the axis AA1 than the upper data pads 101. Specifically, with the axis AA1 as a reference, the layout density of the M input buffer circuits 201 is greater than the layout density of the M upper layer data pads 102; for each upper layer data pad 102 and its corresponding input buffer circuit 201, the distance between the upper layer data pad 102 and the axis AA1 is greater than the distance between the input buffer circuit 201 and the axis AA 1. The closer the upper layer data pad 102 is to the axis AA1, the closer the input buffer circuit 201 corresponding to the upper layer data pad 102 is to the axis AA 1.

Specifically, the input data path length from each input buffer circuit 201 to the upper layer data pad 102 corresponding to the input buffer circuit 201 is a first length, the clock path length between each input buffer circuit 201 and the upper layer clock pad 101 is a second length, and the first length and the second length are in positive correlation. That is, for all the input buffer circuits 201, the larger the first length is, the larger the corresponding second length is, and the smaller the first length is, the smaller the corresponding second length is. That is, the further from the axis AA1 the upper data pad 102 is, the further from the axis AA1 the corresponding input buffer circuit 201 is; the closer to the axis AA1 the upper layer data pad 102 is, the closer to the axis AA1 the corresponding input buffer circuit 201 is.

Compared to the solution shown in fig. 1 in which the distance between each input buffer circuit and the axis is equal to the distance between the corresponding data pad and the axis, in the present embodiment, for each upper data pad 102 and input buffer circuit 201 on the same side of the axis AA1, the clock path of the input buffer circuit 201 farthest from the upper clock pad 101 is reduced, so that the clock signal can be transmitted to the input buffer circuit 201 farthest from the upper clock pad 101 more quickly, thereby reducing the signal delay time caused by the arrival of the data signal but the non-arrival of the clock signal. Accordingly, the clock path of each input buffer circuit 201 is reduced, and thus the signal delay time of all the input buffer circuits 201 can be reduced accordingly. That is, the present embodiment can reduce tDQS2DQ or tvck 2DQ, reduce timing violations, and reduce power consumed on clock paths.

In addition, the difference between the data path between each upper layer data pad 102 and the input buffer circuit 201 and the clock path between each upper layer clock pad 101 and the input buffer circuit 201 is reduced, so that the present embodiment can shorten the tDQS2DQ or the tWCK2DQ of different input buffer circuits 201, thereby improving the matching degree of the clock path and the data path of different input buffer circuits 201, and improving the timing characteristics of different input buffer circuits 201 for transmitting data signals.

For example, the data signal of the upper data pad 102 labeled DQ0 in fig. 5 is transmitted to the corresponding input buffer circuit 201 via a first length transmission path, the corresponding input buffer circuit is labeled 2010 in fig. 5, and the clock signal is transmitted to the corresponding input buffer circuit 201 via a second length transmission path; for DQ0, the first length refers to a length from a point a0 to a point b0, the second length refers to a length from a point c0 to a point d0, a point a0 can be understood as a connection point of a transmission line to the upper data pad 102, a point b0 can be understood as a connection point of a transmission line to the lower data pad 112, a point c0 can be understood as a connection point of a transmission line to the clock processing circuit 202, a point d0 can be understood as a connection point of a transmission line to the lower data pad 112, and d0 and b0 can be the same connection point. When the data signal is transmitted to the input buffer circuit 201, the clock signal is transmitted to the input buffer circuit 201 after time t1, so that the input buffer circuit 201 can transmit the data signal within time t1 after receiving the data signal; as the data pad 201 transmits the data signal DQ0 at higher and higher rates, the DQ0 maintains the high level "1" or the low level "0" for shorter and shorter periods, so that the required waiting time t1 is smaller and smaller, and the first length (corresponding to the data path) and the second length (corresponding to the clock path) are matched as much as possible.

The data signal of the upper layer data pad 102 marked as DQ3 in fig. 5 is transmitted to the corresponding input buffer circuit 201 through a first length transmission path, the corresponding input buffer circuit is marked as 2013 in fig. 5, and the clock signal is transmitted to the corresponding input buffer circuit 201 through a second length transmission path; for DQ3, the first length refers to the length from point a3 to point b3, the second length refers to the length from point c0 to point d3, and b3 and d3 may be the same point. When the data signal is transmitted to the input buffer circuit 201, the clock signal is transmitted to the input buffer circuit 201 after time t2, so as to ensure that the input buffer circuit 201 can transmit the data signal within time t2 after receiving the data signal. For data pad 101 labeled DQ0 and labeled DQ3, t1 is equal or approximately equal to t2 because the first length and the second length of input buffer circuit 201 corresponding to DQ0 are matched and the first length and the second length of input buffer circuit 201 corresponding to DQ3 are also matched. Therefore, in the present embodiment, the time consistency of the data signal transmission by the different input buffer circuits 201, i.e., better timing characteristics, can be improved.

In addition, the input data path from each input buffer circuit 201 to the lower data pad 112 corresponding to the input buffer circuit 201 has a third length, the clock path from each input buffer circuit 201 to the lower clock pad 111 corresponding to the input buffer circuit 201 has a fourth length, and the third length is positively correlated with the fourth length.

Further, the interface circuit may further include: an upper flag pad 203 for transmitting a flag signal, the upper flag pad 203 being located at a first layer; a lower flag pad 213 electrically connected to the upper flag pad 203 and located at a second layer, and the area of the lower flag pad 213 is smaller than that of the upper flag pad 203; the flag buffer circuit 223 corresponds to the flag pad 203 and is used for receiving the flag signal transmitted from the upper flag pad 203 under the driving of the clock signal.

The flag signal is usually called a data mask inverter for indicating whether each data signal is inverted, the upper flag pad 203 is usually called a DMI (data mask inverter) pad, a DM pad, or a DBI pad, and the upper flag pad 203 is indicated by DMI in fig. 5.

In this embodiment, the lower flag pad 213 is disposed in the first row and between the lower data pad 112 and the lower clock pad 111; the flag buffer circuit 223 is disposed in the second row, and is located on the same side of the axis AA1 as the lower flag pad 213, and is located between the input buffer circuit 201 and the axis AA 1; the distance between the flag buffer circuit 223 and the axis AA1 is smaller than the distance between the lower flag pad 213 corresponding to the flag buffer circuit 223 and the axis AA 1.

The interface circuit may further include: m output buffer circuits corresponding to the lower data pads 112 one-to-one, each of which transmits a data signal to the corresponding lower data pad 112 under the driving of a clock signal. The output buffer circuit is electrically connected to the lower clock pad 111 in addition to the lower data pad 112.

Specifically, the output buffer circuit is electrically connected to the lower clock pad 111 via the time receiving circuit and the phase generating circuit.

In this embodiment, the output data path length from each output buffer circuit to the corresponding lower data pad 112 of the output buffer circuit is the same. Specifically, each output buffer circuit is located directly below the corresponding lower data pad 111, or the distance between each output buffer circuit and the axis AA1 is equal to the distance between the corresponding lower data pad and the axis AA 1. Similarly, in consideration of the actual situation of circuit design and manufacture, the lengths or distances equal may also be approximately the same or approximately the same, allowing for certain errors, and similar descriptions will not be repeated.

In this embodiment, the output buffer circuit and the input buffer circuit 201 can be integrated into one functional module.

The interface circuit may further include: and the power supply pads and the grounding pads are used for grounding or connecting a fixed power supply. With multiple power and ground pads in the same row as upper data pads 102.

The interface circuit may further include: a first upper layer function pad 301 and a second upper layer function pad 302 on a first layer, wherein the first upper layer function pad 301 and the second upper layer function pad 302 are located between the upper layer function pad 102 and the upper layer clock pad 101, the first upper layer function pad 301 transmits an Rqst signal, and the second upper layer function pad 302 transmits an Rqsc signal; and the first lower-layer functional pad 311 and the second lower-layer functional pad 312 are positioned on the second layer, the first lower-layer functional pad 311 is electrically connected with the first upper-layer functional pad 301, the second lower-layer functional pad 312 is electrically connected with the second upper-layer functional pad 302, the area of the first lower-layer functional pad 311 is smaller than that of the first upper-layer functional pad 301, and the area of the second lower-layer functional pad 312 is smaller than that of the second upper-layer functional pad 302. In fig. 5, the first upper functional pad 301 is denoted by Rqst, and the second upper functional pad 302 is denoted by Rqsc.

The interface circuit may further include: a first functional buffer circuit 321, configured to receive the flag signal transmitted by the first lower functional pad 311 under the driving of the clock signal; and a second functional buffer circuit 322, configured to receive the Rqsc signal transmitted by the second lower functional pad 312 under the driving of the clock signal.

The input buffer circuit comprises a multiplexer (mux) and a latch (latch), the multiplexer receives the data signal, processes the data signal and outputs the processed data signal to the latch, and the output of the latch is used as the output of the input buffer circuit.

The interface circuit may further include: m serial-parallel conversion circuits (S2P) corresponding one-to-one to the M input buffer circuits 201, the output of each input buffer circuit 201 being the input of the corresponding serial-parallel conversion circuit. The M serial-to-parallel conversion circuits correspond to the M lower data pads 112 one to one, and the distance from each serial-to-parallel conversion circuit to the lower data pad 112 corresponding to the serial-to-parallel conversion circuit is the same. It can be considered that each serial-to-parallel conversion circuit layout is directly below the corresponding lower layer data pad 112.

The interface circuit may further include: m first-in first-out circuits (Output FIFO) corresponding to M serial-Parallel conversion circuits (S2P, Sequential to Parallel) one by one; m Parallel-serial conversion circuits (P2S, Parallel to serial) are in one-to-one correspondence with M First-in First-out circuits (Output FIFO, Output First Input First Output), and the Output of each First-in First-out circuit is used as the Input of the Parallel-serial conversion circuit corresponding to the First-in First-out circuit; the M driving circuits correspond to the M parallel-serial conversion circuits one by one, and the output of each parallel-serial conversion circuit is used as the input of the driving circuit corresponding to the parallel-serial conversion circuit; and the M driving circuits also correspond one-to-one to the M lower data pads 112.

Fig. 6 is a schematic layout diagram of the interface circuit provided in this embodiment, and fig. 7 is a schematic layout diagram of another interface circuit provided in this embodiment. In fig. 6 and 7, lower layer data pads are denoted by DQ0, DQ1, DQ2, DQ3, DQ4, DQ5, DQ6, and DQ7, corresponding upper layer data pads are denoted by RDL _ DQ0, RDL _ DQ1, RDL _ DQ2, RDL _ DQ3, RDL _ DQ4, RDL _ DQ5, RDL _ DQ6, and RDL _ DQ7, corresponding lower layer clock pads are denoted by Dqs, and corresponding upper layer clock pads are denoted by RDL _ Dqs.

As shown in fig. 6, in one example, the upper data pads and the upper clock pads are disposed in the same row, and the lower data pads and the lower clock pads are disposed in the same row. As shown in fig. 7, in another example, some of the upper data pads and the upper clock pads are disposed in the same row, and the rest of the upper data pads and the upper clock pads are disposed in the same column, and the lower data pads and the lower clock pads are disposed in two rows, it is understood that the lower data pads and the lower clock pads may be disposed in the same row, or the upper clock pads and the upper data pads may be disposed in three or four sides disposed around the lower clock pads and the lower data pads, and it is understood that the upper clock pads and the upper data pads are disposed in two sides disposed around the lower clock pads and the lower data pads in the case shown in fig. 7. In the interface circuit provided in this embodiment, an on die RDL manner is adopted, a lower layer clock pad electrically connected to an upper layer clock pad is arranged, a lower layer data pad electrically connected to an upper layer data pad is arranged, an area of the lower layer clock pad is smaller than an area of the upper layer clock pad, and an area of the lower layer data pad is smaller than an area of the upper layer data pad, so that a centralized arrangement of each input buffer circuit is realized, a clock path length required by clock signal transmission to each input buffer circuit is shortened, a matching degree of a clock path and a data path is improved, and thus tDQS2DQ or tvck 2DQ and a timing violation are reduced. The clock path lengths corresponding to the input buffer circuits have small difference, and the requirement of high matching degree of the clock path and the data path of each input buffer circuit can be met at the same time.

In addition, since the length of the clock path is shortened, the length of a wire for transmitting the clock signal is correspondingly shortened, and therefore, the power consumption of the data transmission circuit can be reduced to a certain extent.

Correspondingly, the embodiment of the present invention further provides a memory, including the above-mentioned interface circuit.

The memory can be DRAM, SRAM, MRAM, FeRAM, PCRAM, NAND, NOR, etc. For example, the memory may be LPDDR4 memory or LPDDR5 memory.

It will be understood by those skilled in the art that the foregoing embodiments are specific examples of the invention, and that various changes in form and details may be made therein without departing from the spirit and scope of the invention in its practical application. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (19)

1. A transmission circuit, comprising:

the upper layer clock bonding pad is used for transmitting clock signals;

m upper layer data pads for transmitting data signals;

the lower-layer clock bonding pad is electrically connected with the upper-layer clock bonding pad, and the area of the lower-layer clock bonding pad is smaller than that of the upper-layer clock bonding pad;

the M lower-layer data bonding pads are electrically connected with the M upper-layer data bonding pads in a one-to-one correspondence manner, and the area of each lower-layer data bonding pad is smaller than that of each upper-layer data bonding pad;

the upper clock pad and the upper data pad are located on a first layer, the lower clock pad and the lower data pad are located on a second layer, a dielectric layer is arranged between the first layer and the second layer, the first layer, the dielectric layer and the second layer are all located on the same substrate, and M is an integer greater than or equal to 2.

2. The transmission circuit of claim 1, further comprising: the first metal connecting wire is positioned between the lower layer clock bonding pad and the upper layer clock bonding pad; and the second metal connecting wire is positioned between any one of the lower data bonding pad and the upper data bonding pad corresponding to the lower data bonding pad, and the length of the first metal connecting wire is smaller than that of the second metal connecting wire.

3. The transmission circuit of claim 2, wherein the first metal line comprises: the first conductive hole penetrates through the dielectric layer and is in contact with the lower clock pad; the first metal layer is positioned on one side of the dielectric layer, which is far away from the first layer, and is in contact with the first conductive hole and the upper clock pad; the second metal connecting line comprises: the second conductive hole penetrates through the dielectric layer and is in contact with the lower data pad; the second metal layer is positioned on one side of the dielectric layer, which is far away from the first layer, and is in contact with the second conductive hole and the upper data pad; the length of the first conductive hole is the same as that of the second conductive hole, and the length of the first metal layer is smaller than that of the second metal layer.

4. The transmission circuit of claim 2, wherein the first metal line comprises: the first conductive plug penetrates through the dielectric layer and is in contact with the lower clock pad and the upper clock pad; the second metal connecting line comprises: and the second conductive plug penetrates through the dielectric layer and is in contact with the lower data pad and the upper data pad, and the length of the first conductive plug is smaller than that of the second conductive plug.

5. The transmission circuit of claim 1, wherein the lower clock pad and the lower data pad have the same area.

6. The transmission circuit of claim 1, further comprising: the lower-layer test pads have the same area, and the area of the lower-layer test pads is larger than that of the lower-layer data pads.

7. The transmit circuit of claim 1, wherein the upper clock pad and the M upper data pads are arranged in a first row, and the M upper data pads are arranged on both sides of the upper clock pad, each side arranged with half of the M upper data pads.

8. The transmission circuit of claim 7, wherein the lower layer clock pad and the M lower layer data pads are arranged in a second row, and the M lower layer data pads are arranged on both sides of the lower layer clock pad, each side arranged with half of the M lower layer data pads.

9. An interface circuit, comprising:

the transmission circuit of any one of claims 1 to 6;

the M input buffer circuits are in one-to-one correspondence with the lower data bonding pads, and each input buffer circuit is driven by the clock signal to receive the data signal transmitted by the lower data bonding pad corresponding to the input buffer circuit;

wherein, lower floor's clock pad with lower floor's data pad arranges in first row, just M lower floor's data pad arrange in the both sides of lower floor's clock pad, each side is arranged half of M lower floor's data pad, M input buffer circuit arranges in the second row, with lower floor's data pad is the benchmark, forms the perpendicular to the axis of first row, M input buffer circuit arrange in the both sides of axis, each side is arranged half of M input buffer circuit, each input buffer circuit with the distance of axis is less than input buffer circuit corresponds lower floor's data pad with the distance of axis.

10. The interface circuit of claim 9, wherein an input data path length between each of the input buffer circuits to the corresponding upper layer clock pad of the input buffer circuit is a first length, a clock path length between each of the input buffer circuits and the upper layer clock pad is a second length, and the first length is positively correlated to the second length.

11. The interface circuit of claim 9, wherein the lower clock pads are differential input pads, including a first lower clock pad and a second lower clock pad, the first lower clock pad and the second lower clock pad each transmitting the complementary clock signal.

12. The interface circuit of claim 11, wherein the first lower layer clock pad and the second lower layer clock pad are symmetrically arranged with respect to the axis.

13. The interface circuit of claim 9, further comprising: and the clock processing circuit is electrically connected with the lower layer clock bonding pad and the M input buffer circuits, and is used for receiving the clock signal and processing the clock signal to be used as a driving clock of the M input buffer circuits.

14. The interface circuit of claim 13, wherein said clock processing circuit includes a clock receiving circuit electrically connected to said lower clock pad for receiving said clock signal and an output of said clock receiving circuit as an input to said phase generating circuit for generating said driving clock.

15. The interface circuit of claim 9, further comprising:

an upper layer flag pad for transmitting a flag signal, the upper layer flag pad being located on the first layer;

the lower layer mark bonding pad is electrically connected with the upper layer mark bonding pad, the lower layer mark bonding pad is positioned on the second layer, and the area of the lower layer mark bonding pad is smaller than that of the upper layer mark bonding pad;

and the mark buffer circuit corresponds to the lower mark pad and is used for receiving the mark signal transmitted by the upper mark pad under the driving of the clock signal.

16. The interface circuit of claim 15, wherein the lower flag pad is arranged in the first row between the lower data pad and the lower clock pad; the mark buffer circuit is arranged in the second row, is positioned on the same side of the axis as the lower mark pad and is positioned between the input buffer circuit and the axis; the distance between the mark buffer circuit and the axis is smaller than the distance between the lower layer mark pad corresponding to the mark buffer circuit and the axis.

17. The interface circuit of claim 9, further comprising: and the M output buffer circuits are in one-to-one correspondence with the lower-layer data bonding pads, and each output buffer circuit is driven by the clock signal to send the data signal to the corresponding lower-layer data bonding pad.

18. The interface circuit of claim 17, wherein an output data path length between each of the output buffer circuits to the corresponding lower data pad of the output buffer circuit is the same.

19. The interface circuit of claim 9, wherein said input buffer circuit includes a multiplexer and a latch, said multiplexer receiving said data signal and processing said data signal for output to said latch, an output of said latch being an output of said input buffer circuit.

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