CN212367132U - Feedback push-free circuit - Google Patents
Feedback push-free circuit Download PDFInfo
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- CN212367132U CN212367132U CN202021030646.1U CN202021030646U CN212367132U CN 212367132 U CN212367132 U CN 212367132U CN 202021030646 U CN202021030646 U CN 202021030646U CN 212367132 U CN212367132 U CN 212367132U
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Abstract
The utility model relates to a controller performance detection technical field, in particular to circuit is exempted from in feedback pushing away, including signal isolation circuit, the complementary circuit of exempting from that pushes away, feedback circuit, chip U1 and chip U3, the complementary circuit of exempting from is connected with signal isolation circuit and feedback circuit electricity respectively, feedback circuit respectively with chip U1's second pin, chip U1's third pin and chip U3's first pin electricity are connected, chip U1's fourth pin is connected with chip U3's second pin electricity, through setting up isolation circuit, can avoid 24V's voltage signal directly to receive chip U1's first pin; by arranging the complementary push-pull circuit, the driving capability of the circuit can be enhanced, so that the duty ratio of high and low levels is clear; through setting up feedback circuit, give feedback circuit with the trouble feedback signal of chip U3 output, the electric connection keeps real-time communication state between feedback circuit and the chip U1, is convenient for circuit trouble to seek the location fast.
Description
Technical Field
The utility model relates to a controller performance detects technical field, in particular to feedback exempts from circuit.
Background
At present, in the aspect of safety and stability of circuit board functions, a master control chip with high integration level is available in the market, and resources for connecting peripheral equipment are rich; most of the chips have multiple cores and are high in processing capacity, but the integration level is high, resources needing to be connected with external devices are rich, for some simple circuits, too many resources are not needed, the cost is high, and resource waste is easily caused; and the system has multiple cores, needs to increase the operation difficulty of programmers, and has higher software threshold.
SUMMERY OF THE UTILITY MODEL
In order to overcome the defects of the prior art, the utility model aims to solve the technical problems that: the feedback exempting circuit can realize the circuit inspection of the controller.
In order to solve the technical problem, the utility model discloses a technical scheme be:
the utility model provides a feedback exempts from circuit, includes that signal isolation circuit, complementation exempt from circuit, feedback circuit, chip U1 and chip U3, complementary exempts from the circuit and is connected and complementary exempts from circuit, signal isolation circuit and the equal ground connection of feedback circuit with signal isolation circuit and feedback circuit electricity respectively, complementary exempts from circuit, signal isolation circuit and feedback circuit and all connects the power of peripheral hardware, chip U1's first pin is connected with signal isolation circuit electricity, feedback circuit is connected with chip U1's second pin, chip U1's third pin and chip U3's first pin electricity respectively, chip U1's fourth pin is connected with chip U3's second pin electricity.
Further, the device also comprises a capacitor C1, wherein one end of the capacitor C1 is respectively electrically connected with the signal isolation circuit, the complementary boosting circuit, the feedback circuit and the anode of the external power supply, the other end of the capacitor C1 is electrically connected with the cathode of the external power supply, and the other end of the capacitor C1 and the cathode of the external power supply are both grounded.
Further, the complementary push-free circuit includes a resistor R4, a resistor R5, a resistor R6, a resistor R7, a transistor Q2, and a transistor Q3, a base of the transistor Q2 is electrically connected to one end of the resistor R4, another end of the resistor R4 is electrically connected to one end of the signal isolation circuit and one end of the resistor R5, another end of the resistor R5 is electrically connected to a base of the transistor Q3, an emitter of the transistor Q3 is electrically connected to one end of the resistor R7, another end of the resistor R7 is electrically connected to one end of the resistor R6, the feedback circuit, and the first pin of the chip U3, another end of the resistor R6 is electrically connected to an emitter of the transistor Q2, a collector of the transistor Q2 is electrically connected to an external power supply, a collector of the transistor Q3 is electrically connected to the signal isolation circuit and the feedback circuit, and a collector of the transistor Q3 is grounded.
Further, the feedback circuit includes a resistor R8, a resistor R9, a diode D1, and a chip U2, one end of the resistor R8 is electrically connected to an anode of the diode D1, a complementary pull-up circuit, and a first pin of the chip U3, a cathode of the diode D1 is electrically connected to a signal isolation circuit, the complementary pull-up circuit, and an external power supply, the other end of the resistor R8 is electrically connected to one end of the resistor R9 and a first pin of the chip U2, the other end of the resistor R9 is electrically connected to the signal isolation circuit and the complementary pull-up circuit, and the other end of the resistor R9 is grounded, a second pin of the chip U2 is electrically connected to a third pin of the chip U1, and a third pin of the chip U2 is electrically connected to a second pin of the chip U1.
Further, the signal isolation circuit includes a resistor R1, a resistor R2, a resistor R3 and a transistor Q1, a base of the transistor Q1 is electrically connected with one end of the resistor R1 and one end of the resistor R2, the other end of the resistor R1 is electrically connected with a first pin of the chip U1, an emitter of the transistor Q1 is electrically connected with the other end of the resistor R2, the complementary push-free circuit and the feedback circuit respectively, an emitter of the transistor Q1 and the other end of the resistor R2 are both grounded, a collector of the transistor Q1 is electrically connected with one end of the resistor R3 and the complementary push-free circuit respectively, and the other end of the resistor R3 is electrically connected with the power supply of the complementary push-free circuit, the feedback circuit and the peripheral device respectively.
The beneficial effects of the utility model reside in that:
by arranging the isolation circuit, the voltage signal of 24V can be prevented from being directly connected to the first pin of the chip U1; by arranging the complementary push-pull circuit, the driving capability of the circuit can be enhanced, so that the duty ratio of high and low levels is clear; the feedback circuit is arranged to monitor whether a circuit on a PCB (printed circuit board) in front of the equipment end outputs a signal from the U1 end to work normally or not, a fault feedback signal output by the U3 is sent to the feedback circuit, and the feedback circuit is electrically connected with the U1 to keep a real-time communication state, so that circuit faults can be conveniently and rapidly found and positioned, and the normal work of the whole engine system is guaranteed; the feedback exempting circuit designed by the scheme can realize the real-time detection function of the circuit, enhances the reliability of the circuit, is convenient for fault location, and improves the functional safety performance of the whole system.
Drawings
Fig. 1 is an overall circuit block diagram of a feedback push-free circuit according to the present invention;
fig. 2 is a schematic circuit diagram of a feedback boost-free circuit according to the present invention;
description of reference numerals:
1. a signal isolation circuit; 2. a complementary push-to-immune circuit; 3. a feedback circuit.
Detailed Description
In order to explain the technical content, the objects and the effects of the present invention in detail, the following description is made with reference to the accompanying drawings in combination with the embodiments.
Referring to fig. 1, the technical solution provided by the present invention is:
the utility model provides a feedback exempts from circuit, includes that signal isolation circuit, complementation exempt from circuit, feedback circuit, chip U1 and chip U3, complementary exempts from the circuit and is connected and complementary exempts from circuit, signal isolation circuit and the equal ground connection of feedback circuit with signal isolation circuit and feedback circuit electricity respectively, complementary exempts from circuit, signal isolation circuit and feedback circuit and all connects the power of peripheral hardware, chip U1's first pin is connected with signal isolation circuit electricity, feedback circuit is connected with chip U1's second pin, chip U1's third pin and chip U3's first pin electricity respectively, chip U1's fourth pin is connected with chip U3's second pin electricity.
From the above description, the beneficial effects of the present invention are:
by arranging the isolation circuit, the voltage signal of 24V can be prevented from being directly connected to the first pin of the chip U1; by arranging the complementary push-pull circuit, the driving capability of the circuit can be enhanced, so that the duty ratio of high and low levels is clear; the feedback circuit is arranged to monitor whether a circuit on a PCB (printed circuit board) in front of the equipment end outputs a signal from the U1 end to work normally or not, a fault feedback signal output by the U3 is sent to the feedback circuit, and the feedback circuit is electrically connected with the U1 to keep a real-time communication state, so that circuit faults can be conveniently and rapidly found and positioned, and the normal work of the whole engine system is guaranteed; the feedback exempting circuit designed by the scheme can realize the real-time detection function of the circuit, enhances the reliability of the circuit, is convenient for fault location, and improves the functional safety performance of the whole system.
Further, the device also comprises a capacitor C1, wherein one end of the capacitor C1 is respectively electrically connected with the signal isolation circuit, the complementary boosting circuit, the feedback circuit and the anode of the external power supply, the other end of the capacitor C1 is electrically connected with the cathode of the external power supply, and the other end of the capacitor C1 and the cathode of the external power supply are both grounded.
As can be seen from the above description, the capacitor C1 is provided to perform a filtering function to absorb the power glitch, thereby avoiding signal interference.
Further, the complementary push-free circuit includes a resistor R4, a resistor R5, a resistor R6, a resistor R7, a transistor Q2, and a transistor Q3, a base of the transistor Q2 is electrically connected to one end of the resistor R4, another end of the resistor R4 is electrically connected to one end of the signal isolation circuit and one end of the resistor R5, another end of the resistor R5 is electrically connected to a base of the transistor Q3, an emitter of the transistor Q3 is electrically connected to one end of the resistor R7, another end of the resistor R7 is electrically connected to one end of the resistor R6, the feedback circuit, and the first pin of the chip U3, another end of the resistor R6 is electrically connected to an emitter of the transistor Q2, a collector of the transistor Q2 is electrically connected to an external power supply, a collector of the transistor Q3 is electrically connected to the signal isolation circuit and the feedback circuit, and a collector of the transistor Q3 is grounded.
As can be seen from the above description, the transistor Q2 is an NPN transistor, the transistor Q3 is a PNP transistor, the base of the transistor Q2 and the base of the transistor Q3 are connected to point b through a current-limiting resistor (respectively, the resistor R4 and the resistor R5), and a PWM input signal is added to the base of the transistor Q2 and the base b of the transistor Q3 as a driving signal; the emitter of the triode Q2 is connected with the emitter of the triode Q3, because the polarities of the triode Q2 and the triode Q3 are different, the voltage of the input signal on the base electrode is positive bias for one triode and reverse bias for the other triode, when the signal isolation circuit outputs low level, the point b of the base electrode of the triode Q2 and the base electrode of the triode Q3 is high level, at the moment, the input signal adds positive bias voltage to the triode Q2, so the triode Q2 enters a conducting and amplifying state, and the triode Q3 is in a stopping state; when the signal isolation circuit outputs a high level, the b point applied to the base of the transistor Q2 and the base of the transistor Q3 is a low level, and at this time, the input signal applies a forward bias voltage to the transistor Q3, so that the transistor Q3 is turned on and amplified, and the transistor Q2 is turned off.
Further, the feedback circuit includes a resistor R8, a resistor R9, a diode D1, and a chip U2, one end of the resistor R8 is electrically connected to an anode of the diode D1, a complementary pull-up circuit, and a first pin of the chip U3, a cathode of the diode D1 is electrically connected to a signal isolation circuit, the complementary pull-up circuit, and an external power supply, the other end of the resistor R8 is electrically connected to one end of the resistor R9 and a first pin of the chip U2, the other end of the resistor R9 is electrically connected to the signal isolation circuit and the complementary pull-up circuit, and the other end of the resistor R9 is grounded, a second pin of the chip U2 is electrically connected to a third pin of the chip U1, and a third pin of the chip U2 is electrically connected to a second pin of the chip U1.
As can be seen from the above description, the diode D1 is provided to mainly perform a clamping function, so as to protect the first pin of the chip U3 and the first pin of the chip U2 from being damaged due to the over-high voltage; the resistor R8 and the resistor R9 are used for dividing the voltage of a PWM signal sent by the chip U1 after the PWM signal is enhanced by the complementary push-pull circuit, then the PWM signal is sent to the first pin of the chip U2 for sampling, and the sampled data is compared with the third pin through the second pin and the third pin of the chip U2 and the second pin and the third pin of the chip U1.
Further, the signal isolation circuit includes a resistor R1, a resistor R2, a resistor R3 and a transistor Q1, a base of the transistor Q1 is electrically connected with one end of the resistor R1 and one end of the resistor R2, the other end of the resistor R1 is electrically connected with a first pin of the chip U1, an emitter of the transistor Q1 is electrically connected with the other end of the resistor R2, the complementary push-free circuit and the feedback circuit respectively, an emitter of the transistor Q1 and the other end of the resistor R2 are both grounded, a collector of the transistor Q1 is electrically connected with one end of the resistor R3 and the complementary push-free circuit respectively, and the other end of the resistor R3 is electrically connected with the power supply of the complementary push-free circuit, the feedback circuit and the peripheral device respectively.
As can be seen from the above description, the resistor R1 is provided to limit the current; the resistor R2 is pulled down to be grounded, and the initial state plays a stabilizing role; the transistor Q1 is saturated and turned on as a switch.
Referring to fig. 1 and fig. 2, a first embodiment of the present invention is:
referring to fig. 1, a feedback push-and-pull circuit includes a signal isolation circuit 1, a complementary push-and-pull circuit 2, a feedback circuit 3, a chip U1 (model is FS32K146 hatormlqt), and a chip U3 (the chip U3 is a peripheral device with PWM input, and the peripheral device is a heat dissipation fan with PWM and feedback), the complementary push-and-pull circuit 2 is electrically connected to the signal isolation circuit 1 and the feedback circuit 3, and the complementary push-and-pull circuit 2, the signal isolation circuit 1, and the feedback circuit 3 are all grounded, the complementary push-and-pull circuit 2, the signal isolation circuit 1, and the feedback circuit 3 are all connected to a peripheral power supply, a first pin of the chip U1 is electrically connected to the signal isolation circuit 1, the feedback circuit 3 is electrically connected to a second pin of the chip U1, a third pin of the chip U1, and a first pin of the chip U3, and a fourth pin of the chip U1 is electrically connected to a second pin of the chip U3.
Referring to fig. 1, the apparatus further includes a capacitor C1 (a capacitance value is 0.1uF), one end of the capacitor C1 is electrically connected to the signal isolation circuit 1, the complementary immune circuit 2, the feedback circuit 3, and the positive electrode of the external power supply, the other end of the capacitor C1 is electrically connected to the negative electrode of the external power supply, and the other end of the capacitor C1 and the negative electrode of the external power supply are both grounded.
Referring to fig. 2, the complementary push-pull circuit 2 includes a resistor R4 (with a resistance of 10K Ω), a resistor R5 (with a resistance of 47K Ω), a resistor R6 (with a resistance of 47K Ω), a resistor R7 (with a resistance of 30 Ω), a transistor Q2 (with a model of MMBT4401LT1G) and a transistor Q3 (with a model of MMBT4403LT1G), a base of the transistor Q2 is electrically connected to one end of a resistor R4, the other end of the resistor R4 is electrically connected to one ends of a signal isolation circuit 1 and a resistor R5, the other end of the resistor R5 is electrically connected to a base of the transistor Q3, an emitter of the transistor Q3 is electrically connected to one end of the resistor R7, the other end of the resistor R7 is electrically connected to one end of the resistor R6, the feedback circuit 3 and a first pin of the chip U3, the other end of the resistor R6 is electrically connected to an emitter of the transistor Q2, and a collector of the transistor Q2, the collector of the transistor Q3 is electrically connected to the signal isolation circuit 1 and the feedback circuit 3, respectively, and the collector of the transistor Q3 is grounded.
Referring to fig. 2, the feedback circuit 3 includes a resistor R8 (with a resistance of 10K Ω), a resistor R9 (with a resistance of 2K Ω), a diode D1 (with a model of 1N4148), and a chip U2 (with a model of S9KEAZ128AMLK), one end of the resistor R8 is electrically connected with the anode of the diode D1, the complementary push-pull circuit 2 and the first pin of the chip U3 respectively, the cathode of the diode D1 is electrically connected to the signal isolation circuit 1, the complementary drive-free circuit 2 and the power supply of the peripheral device, the other end of the resistor R8 is electrically connected with one end of the resistor R9 and the first pin of the chip U2 respectively, the other end of the resistor R9 is electrically connected with the signal isolation circuit 1 and the complementary drive-free circuit 2 respectively and the other end of the resistor R9 is grounded, the second pin of the chip U2 is electrically connected to the third pin of the chip U1, and the third pin of the chip U2 is electrically connected to the second pin of the chip U1.
Referring to fig. 2, the signal isolation circuit 1 includes a resistor R1 (with a resistance value of 10K Ω), a resistor R2 (with a resistance value of 10K Ω), a resistor R3 (with a resistance value of 10K Ω), and a transistor Q1 (with a model of MMBT4401LT1G), a base of the transistor Q1 is electrically connected to one end of the resistor R1 and one end of the resistor R2, respectively, the other end of the resistor R1 is electrically connected to a first pin of the chip U1, an emitter of the transistor Q1 is electrically connected to the other end of the resistor R2, the complementary push-pull circuit 2, and the feedback circuit 3, respectively, an emitter of the transistor Q1 and the other end of the resistor R2 are grounded, a collector of the transistor Q1 is electrically connected to one end of the resistor R3 and the complementary push-pull circuit 2, and another end of the resistor R3 is electrically connected to the complementary push-pull circuit 2, the feedback circuit 3.
The feedback exempting circuit designed by the scheme can be applied to a hydrogen fuel cell controller, is provided with a circuit with feedback and complementary exempting functions, is high in stability and reliable in work, completes a circuit form which cannot be formed by an electronic pipeline by using a transistor, simplifies a peripheral hardware circuit, realizes the inspection of the circuit of the controller, and improves the safety of the circuit design function.
The working principle of the feedback exemption circuit is as follows:
the chip U1 sends out PWM signals with different duty ratios through a first pin (namely an FTM pin) of the chip U1, and the PWM signals are subjected to current limiting and voltage division through a resistor R1 and a resistor R2 and are sent to a triode Q1; the resistor R1 plays a role in limiting current; the resistor R2 is pulled down to be grounded, and the initial state plays a stabilizing role; the triode Q1 is in saturation conduction and serves as a switching tube; the resistor R3 is pulled up to VCC (the power supply of the peripheral on the vehicle is generally 24V); the working voltage range of a fourth pin (i.e. an I/O pin) of the chip U1 is 0V-5.5V, and the triode Q1 isolates two different voltages of 5V and 24V, so that the fourth pin (i.e. the I/O pin) of the chip U1 is protected;
a triode Q2 in the complementary drive-free circuit 2 is an NPN triode, a triode Q3 is a PNP triode, the base electrode of the triode Q2 and the base electrode of the triode Q3 are respectively connected with a point b through a current-limiting resistor (a resistor R4 and a resistor R5 respectively), and a PWM input signal is added to the base electrode of the triode Q2 and the point b of the base electrode of the triode Q3 to serve as a drive signal; the emitter of the triode Q2 is connected with the emitter of the triode Q3, because the polarities of the triode Q2 and the triode Q3 are different, the voltage of the input signal on the base electrode is positive bias for one triode and reverse bias for the other triode, when the point a in the signal isolation circuit 1 outputs low level, the point b added on the base electrode of the triode Q2 and the base electrode of the triode Q3 is high level, at the moment, the input signal adds positive bias voltage to the triode Q2, so the triode Q2 tube enters a conducting and amplifying state, and the triode Q3 is in a cut-off state; when the point a in the signal isolation circuit 1 outputs high level, the point b added to the base of the triode Q2 and the base of the triode Q3 is low level, and at this time, the input signal adds forward bias voltage to the triode Q3, so that the triode Q3 enters a conducting and amplifying state, and the triode Q2 is in a cut-off state;
the diode D1 mainly plays a role in clamping and protecting the first pin of the chip U3 and the first pin of the chip U2 from being damaged due to overhigh voltage; the resistor R8 and the resistor R9 divide the voltage of the PWM signal sent by the chip U1 after the PWM signal is enhanced by the complementary push-pull circuit, then the PWM signal is sent to the first pin of the chip U2 for sampling, and the sampled data is compared with the third pin through the second pin and the third pin of the chip U2 and the second pin and the third pin of the chip U1: if the sampled data is different from the original data sent by the chip U1, the chip U1 initiates a fault report to a Vehicle Control Unit (VCU for short) of the electric Vehicle through a second pin and a third pin thereof, and at this time, the fault can be located to a circuit on a front end board of the device; if the sampled data is consistent with the original data sent by the chip U1, and the second pin of the chip U3 sends a fault feedback signal to the fourth pin (i.e., I/O pin) of the chip U1, the chip U1 and the chip U1 initiate a fault report to a Vehicle Control Unit (VCU) through the second pin and the third pin, and at this time, a peripheral fault can be located.
In summary, the feedback exempting circuit provided by the utility model can avoid the voltage signal of 24V from directly connecting to the first pin of the chip U1 by arranging the isolation circuit; by arranging the complementary push-pull circuit, the driving capability of the circuit can be enhanced, so that the duty ratio of high and low levels is clear; by arranging the feedback circuit, whether a circuit on a PCB (printed circuit board) in front of an equipment end is normally operated by monitoring a signal output by a U1 end of the chip, a fault feedback signal output by a U3 of the chip is sent to a U2 of the chip, and a real-time communication state is kept between the U2 of the chip and the U1 of the chip through a corresponding second pin and a corresponding third pin (namely a CAN _ H pin and a CAN _ L pin), so that the circuit fault CAN be quickly searched and positioned, and the normal operation of the whole engine system is guaranteed; the feedback exempting circuit designed by the scheme can realize the real-time detection function of the circuit, enhances the reliability of the circuit, is convenient for fault location, and improves the functional safety performance of the whole system.
The above mentioned is only the embodiment of the present invention, and not the limitation of the patent scope of the present invention, all the equivalent transformations made by the contents of the specification and the drawings, or the direct or indirect application in the related technical field, are included in the patent protection scope of the present invention.
Claims (5)
1. The utility model provides a feedback exempts from circuit, its characterized in that, exempts from circuit, feedback circuit, chip U1 and chip U3 including signal isolation circuit, complementation, complementary exempts from the circuit and is connected and complementary exempts from circuit, signal isolation circuit and the equal ground connection of feedback circuit with signal isolation circuit and feedback circuit electricity respectively, complementary exempts from circuit, signal isolation circuit and feedback circuit and all connects the power of peripheral hardware, chip U1's first pin is connected with signal isolation circuit electricity, feedback circuit is connected with chip U1's second pin, chip U1's third pin and chip U3's first pin electricity respectively, chip U1's fourth pin is connected with chip U3's second pin electricity.
2. The feedback push-free circuit according to claim 1, further comprising a capacitor C1, wherein one end of the capacitor C1 is electrically connected to the signal isolation circuit, the complementary push-free circuit, the feedback circuit and the positive pole of the external power supply, respectively, the other end of the capacitor C1 is electrically connected to the negative pole of the external power supply, and the other end of the capacitor C1 and the negative pole of the external power supply are both grounded.
3. The feedback push-free circuit of claim 1, wherein the complementary push-free circuit comprises a resistor R4, a resistor R5, a resistor R6, a resistor R7, a transistor Q2, and a transistor Q3, the base electrode of the triode Q2 is electrically connected with one end of a resistor R4, the other end of the resistor R4 is respectively and electrically connected with a signal isolation circuit and one end of a resistor R5, the other end of the resistor R5 is electrically connected with the base electrode of the triode Q3, the emitter electrode of the triode Q3 is electrically connected with one end of the resistor R7, the other end of the resistor R7 is respectively and electrically connected with one end of the resistor R6, the feedback circuit and the first pin of the chip U3, the other end of the resistor R6 is electrically connected with the emitter of the triode Q2, the collector of the triode Q2 is electrically connected with the external power supply, the collector of the transistor Q3 is electrically connected with the signal isolation circuit and the feedback circuit respectively, and the collector of the transistor Q3 is grounded.
4. The feedback push-free circuit according to claim 1, wherein the feedback circuit comprises a resistor R8, a resistor R9, a diode D1 and a chip U2, one end of the resistor R8 is electrically connected to an anode of the diode D1, a complementary push-free circuit and a first pin of the chip U3, a cathode of the diode D1 is electrically connected to the signal isolation circuit, the complementary push-free circuit and an external power supply, the other end of the resistor R8 is electrically connected to one end of the resistor R9 and a first pin of the chip U2, the other end of the resistor R9 is electrically connected to the signal isolation circuit and the complementary push-free circuit, and the other end of the resistor R9 is grounded, a second pin of the chip U2 is electrically connected to a third pin of the chip U1, and a third pin of the chip U2 is electrically connected to a second pin of the chip U1.
5. The feedback push-free circuit according to claim 1, wherein the signal isolation circuit comprises a resistor R1, a resistor R2, a resistor R3 and a transistor Q1, a base of the transistor Q1 is electrically connected with one end of the resistor R1 and one end of the resistor R2 respectively, the other end of the resistor R1 is electrically connected with the first pin of the chip U1, an emitter of the transistor Q1 is electrically connected with the other end of the resistor R2, the complementary push-free circuit and the feedback circuit respectively, an emitter of the transistor Q1 and the other end of the resistor R2 are both grounded, a collector of the transistor Q1 is electrically connected with one end of the resistor R3 and the complementary push-free circuit respectively, and the other end of the resistor R3 is electrically connected with the complementary push-free circuit, the feedback circuit and a peripheral power supply respectively.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202021030646.1U CN212367132U (en) | 2020-06-08 | 2020-06-08 | Feedback push-free circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202021030646.1U CN212367132U (en) | 2020-06-08 | 2020-06-08 | Feedback push-free circuit |
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| Publication Number | Publication Date |
|---|---|
| CN212367132U true CN212367132U (en) | 2021-01-15 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202021030646.1U Active CN212367132U (en) | 2020-06-08 | 2020-06-08 | Feedback push-free circuit |
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| CN (1) | CN212367132U (en) |
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- 2020-06-08 CN CN202021030646.1U patent/CN212367132U/en active Active
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Effective date of registration: 20210601 Address after: 350000 No.8, Dongjiang West Road, Liren Industrial Zone, Hangcheng street, Changle District, Fuzhou City, Fujian Province Patentee after: Fujian Snowman Hydrogen Technology Co.,Ltd. Address before: 350000 No.8, Dongjiang West Road, Liren Industrial Zone, Hangcheng street, Changle District, Fuzhou City, Fujian Province Patentee before: Fuzhou Snowman New Energy Technology Co.,Ltd. |