CN212276288U - Band gap reference circuit - Google Patents
Band gap reference circuit Download PDFInfo
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- CN212276288U CN212276288U CN202022087711.0U CN202022087711U CN212276288U CN 212276288 U CN212276288 U CN 212276288U CN 202022087711 U CN202022087711 U CN 202022087711U CN 212276288 U CN212276288 U CN 212276288U
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Abstract
The application provides a band gap reference circuit, which comprises a band gap reference main body circuit and a band gap reference control circuit, wherein the band gap reference main body circuit comprises a first PMOS tube and a second PMOS tube, the source electrode of the first PMOS tube is connected with a power supply, the source electrode of the second PMOS tube is connected with the power supply, the grid electrode of the second PMOS tube is connected with the grid electrode of the first PMOS tube as a detection point, the band gap reference control circuit comprises a third PMOS tube, a fourth PMOS tube, a first NMOS tube and an adjusting unit, the source electrode of the third PMOS tube is connected with the power supply, the grid electrode of the third PMOS tube is connected with the detection point, the source electrode of the fourth PMOS tube is connected with the drain electrode of the third PMOS tube, the grid electrode of the fourth PMOS tube is connected with a first enable signal, if the voltage of the detection point is high level, the drain electrode of the first NMOS tube is connected with the drain electrode of the fourth PMOS tube, the grid electrode of the first NMOS tube is connected with the detection point, the input, the input end of the adjusting unit is connected with a low level, the output of the adjusting unit is the low level, and the level of the detecting point is changed.
Description
Technical Field
The application relates to the field of circuit design, in particular to a band-gap reference circuit.
Background
The band-gap reference source is widely applied to various integrated circuits such as analog and digital-analog mixed signals, power management and the like, and aims to establish direct current voltage or current independent of power supply voltage, temperature and process. The design quality of the bandgap reference source directly affects the performance of the chip circuit and even the whole system, and circuits such as a data converter, a comparator, an error amplifier and the like all need the bandgap reference source to provide accurate and stable reference voltage and reference current. Therefore, the design of the reference source occupies an important position in the whole circuit system, and the improvement of the performance of the bandgap reference source is helpful for improving the stability and reliability of the operation of the circuit system.
The band-gap reference circuit has a non-ideal stable state called as a degeneracy point, and when the band-gap reference circuit is at the degeneracy point, the output of the band-gap reference circuit is constantly zero, so that the band-gap reference circuit cannot normally work to provide reference voltage.
SUMMERY OF THE UTILITY MODEL
The application provides a band gap reference circuit, which can be separated from a degeneracy point under a certain condition.
In order to solve the above problem, the present application provides a bandgap reference circuit, including a bandgap reference control circuit and a bandgap reference control circuit connected to the bandgap reference main circuit, the bandgap reference main circuit includes: the source electrode of the first PMOS tube is connected with a power supply; a source electrode of the second PMOS tube is connected with the power supply, and a grid electrode of the second PMOS tube is connected with a grid electrode of the first PMOS tube and is used as a detection point of the band-gap reference main body circuit; the bandgap reference control circuit includes: a source electrode of the third PMOS tube is connected with a power supply, and a grid electrode of the third PMOS tube is connected with the detection point; a source electrode of the fourth PMOS tube is connected with a drain electrode of the third PMOS tube, a grid electrode of the fourth PMOS tube is connected with a first enabling signal, and if the voltage of the detection point is high level, the first enabling signal is low level; the drain electrode of the first NMOS tube is connected with the drain electrode of the fourth PMOS tube, the grid electrode of the first NMOS tube is connected with the detection point, and the source electrode of the first NMOS tube is grounded; and the input end of the adjusting unit is connected with the source electrode of the fourth PMOS tube, the output end of the adjusting unit is connected with the detection point, and when the input end of the adjusting unit is connected with a low level, the output of the adjusting unit is at the low level.
In one embodiment of the present application, the adjusting unit includes: a source electrode of the fifth PMOS tube is connected with the power supply, and a grid electrode of the fifth PMOS tube is used as an input end of the regulating unit and is connected with a source electrode of the fourth PMOS tube; the first input end of the first operational amplifier is connected with the drain electrode of the first PMOS tube, the second input end of the first operational amplifier is connected with the drain electrode of the second PMOS tube, and the output end of the first operational amplifier is connected with the detection point.
In one embodiment of the present application, the bandgap reference control circuit further comprises: the input end of the circuit turn-off unit is connected with the power supply, the control end of the circuit turn-off unit is connected with a second enabling signal, the output end of the circuit turn-off unit is connected with the detection point, and the second enabling signal controls the circuit turn-off unit to work or turn off.
In one embodiment of the present application, the circuit shutdown unit includes: and the source electrode of the sixth PMOS tube is used as the input end of the circuit turn-off unit and connected with the power supply, the grid electrode of the sixth PMOS tube is used as the control end of the circuit turn-off unit and connected with the second enabling signal, and the drain electrode of the fourth PMOS tube is used as the output end of the circuit turn-off unit and connected with the detection point.
In one embodiment of the present application, if the second enable signal is at a high level, the circuit shutdown unit does not affect the bandgap reference main circuit; if the second enable signal is at a low level, the circuit shutdown unit changes the voltage at the detection point of the bandgap reference main circuit to a high level, and the bandgap reference main circuit is shut down.
In one embodiment of the present application, the bandgap reference control circuit further comprises: and the source electrode of the first NMOS tube is grounded through the current limiting unit.
In one embodiment of the present application, the current limiting unit includes: the drain electrode of the second NMOS tube is connected with the source electrode of the first NMOS tube, the grid electrode of the second NMOS tube is connected with the drain electrode of the second NMOS tube, and the source electrode of the second NMOS tube is grounded.
In one embodiment of the present application, the bandgap reference main body circuit further includes: the emitter of the first triode is connected with the drain of the first PMOS tube, and the base of the first triode is connected with the collector of the first triode and grounded; and the emitter of the second triode is connected with the drain of the second PMOS tube through a first resistor, and the base of the second triode is connected with the collector of the second triode and grounded.
In one embodiment of the present application, the bandgap reference main body circuit further includes: a source electrode of the seventh PMOS tube is connected with the power supply, a grid electrode of the seventh PMOS tube is connected with a grid electrode of the first PMOS tube, and a drain electrode of the seventh PMOS tube is used as an output end of the band-gap reference circuit to output reference voltage; a first end of the second resistor is connected with the drain electrode of the seventh PMOS tube; and an emitter of the third triode is connected with the second end of the second resistor, and a base of the third triode is connected with a collector of the third triode and grounded.
According to the technical scheme, the method has at least the following advantages and positive effects:
the band-gap reference circuit comprises a band-gap reference main body circuit and a band-gap reference control circuit connected with the band-gap reference main body circuit, wherein the band-gap reference main body circuit comprises a first PMOS (P-channel metal oxide semiconductor) tube and a second PMOS tube, the source electrode of the first PMOS tube is connected with a power supply, the source electrode of the second PMOS tube is connected with the power supply, the gate electrode of the second PMOS tube is connected with the gate electrode of the first PMOS tube to be used as a detection point of the band-gap reference main body circuit, if the voltage of the detection point is high level, the first PMOS tube and the second PMOS tube are both turned off, the band-gap reference control circuit is at a degenerate point, the band-gap reference control circuit comprises a third PMOS tube, a fourth PMOS tube, a first NMOS (N-channel metal oxide semiconductor) tube and an adjusting unit, the source electrode of the third PMOS tube is connected with the power supply, the gate electrode of the third PMOS tube is connected with the detection point, the source electrode of the fourth PMOS tube, the first enable signal is low level, the fourth PMOS tube is conducted, the drain electrode of the first NMOS tube is connected with the drain electrode of the fourth PMOS tube, the grid electrode of the first NMOS tube is connected with the detection point, the first NMOS tube is conducted, the source electrode of the first NMOS tube is grounded, the source electrode of the first NMOS tube is low level, the input end of the adjusting unit is connected with the source electrode of the fourth PMOS tube, the output end of the adjusting unit is connected with the detection point, the input end of the adjusting unit is connected with the low level, the output of the adjusting unit is low level, therefore, the level of the detection point is changed from high level to low level, and the band gap reference control circuit is separated from a degenerate point.
Drawings
Fig. 1 schematically shows a bandgap reference circuit according to an embodiment of the present application.
The reference numerals are explained below:
1. bandgap reference main body circuit, M1A first PMOS transistor M2A second PMOS transistor, Q1A first triode, Q2A second triode, R1A first resistor OP, a second operational amplifier 11, a first input of the second operational amplifier 12, a second input of the second operational amplifier VBDetection point, M3A seventh PMOS transistor, R2A second resistor, 13, a first terminal of the second resistor, 14, a second terminal of the second resistor, Q3A third triode;
2. bandgap reference control circuit, M4A third PMOS transistor M5Fourth PMOS transistor, M6A first NMOS transistor M7A second NMOS transistor M8A fifth PMOS transistor M9A sixth PMOS transistor VBGReference voltage, ENB, first enable signal, EN, second enable signal.
Detailed Description
Exemplary embodiments that embody features and advantages of the present application will be described in detail in the following description. It is to be understood that the present application is capable of various modifications in various embodiments without departing from the scope of the application, and that the description and drawings are to be taken as illustrative and not restrictive in character.
The band gap reference circuit provided by the present embodiment includes a band gap reference main circuit 1 and a band gap reference control circuit 2 connected to the band gap reference main circuit 1, as shown in fig. 1.
In one embodiment of the present application, the bandgap reference main circuit 1 may be a bandgap reference main circuit 1 having a second operational amplifier OP, including: first PMOS transistor M1A second PMOS transistor M2A first triode Q1A first resistor R1A second triode Q2A second operational amplifier OP, a seventh PMOS transistor M3A second resistor R2And a third triode Q3. First PMOS transistor M1The source electrode of the PMOS transistor M is connected with a power supply, and a second PMOS transistor M2The source electrode of the PMOS transistor M is connected with a power supply, and a second PMOS transistor M2The grid electrode of the transistor is connected with a first PMOS transistor M1The first triode Q1The emitting electrode of the PMOS transistor is connected with a first PMOS transistor M1The first triode Q1The base electrode of the first triode Q is connected1The collector of the second triode Q is grounded2Through a first resistor R1Is connected with a second PMOS tube M2And a second triode Q2The base of the first triode is connected with the second triode Q2The collector of the second operational amplifier OP is grounded, and the first input end 11 of the second operational amplifier OP is connected with the first PMOS transistor M1A second input end 12 of the second operational amplifier OP is connected with a second PMOS tube M2The output end of the second operational amplifier OP is connected with the first PMOS tube M1As a detection point V of the bandgap reference main circuit 1BSeventh PMOS transistor M3The source electrode of the PMOS transistor is connected with a power supply, and a seventh PMOS transistor M3The grid electrode of the transistor is connected with a first PMOS transistor M1The grid of the second PMOS transistor is connected with the output end of the second operational amplifier OP, and a seventh PMOS transistor M3The drain electrode of the reference circuit is used as the output end of the band-gap reference circuit to output a reference voltage VBGThe first end 13 of the second resistor is connected with a seventh PMOS tube M3The drain electrode of the third triode Q3Is connected to the second terminal 14 of the second resistor and the third transistor Q3The base of the transistor is connected with a third triode Q3And the collector of (a) is grounded. A first triode Q1And a second triode Q2A third triode Q with a base-emitter voltage difference providing a positive temperature coefficient3A negative temperature coefficient is provided to enable the bandgap reference circuit to output a stable voltage that is not affected by temperature.
In other embodiments of the present application, the bandgap reference bulk circuit may have a current mirror without the second operational amplifier OP, including: first PMOS transistor M1A second PMOS transistor M2A third NMOS tube, a fourth NMOS tube, a first triode Q1A first resistor R1A second triode Q2Seventh PMOS transistor M3A second resistor R2And a third triode Q3. First PMOS transistor M1The source electrode of the PMOS transistor M is connected with a power supply, and a second PMOS transistor M2The source electrode of the PMOS transistor M is connected with a power supply, and a second PMOS transistor M2The grid electrode of the transistor is connected with a first PMOS transistor M1As a detection point V of the bandgap reference main circuit 1BSecond PMOS transistor M2The drain electrode of the transistor is connected with a second PMOS tube M2The source electrode of the third NMOS tube is connected with the first PMOS tube M1The source electrode of the fourth NMOS tube is connected with the second PMOS tube M2The grid electrode of the third NMOS tube is connected with the grid electrode of the fourth NMOS tube, the source electrode of the fourth NMOS tube is connected with the grid electrode of the third NMOS tube, and a first triode Q1The emitting electrode of the first triode Q is connected with the drain electrode of the third NMOS tube1The base electrode of the first triode Q is connected1The collector of the second triode Q is grounded2Through a first resistor R1A drain electrode connected with the fourth NMOS transistor, and a second triode Q2The base of the first triode is connected with the second triode Q2Collector of the PMOS transistor is grounded, and a seventh PMOS transistor M3The source electrode of the PMOS transistor is connected with a power supply, and a seventh PMOS transistor M3The grid electrode of the transistor is connected with a second PMOS transistor M2Grid of (1), seventh PMOS transistor M3The drain electrode of the reference circuit is used as the output end of the band-gap reference circuit to output a reference voltage VBGThe first end 13 of the second resistor is connected with a seventh PMOS tube M3The drain electrode of the third triode Q3Is connected with a second resistor R2The second terminal of the third triode Q3The base of the transistor is connected with a third triode Q3And the collector of (a) is grounded.
In the above embodiment, the second PMOS transistor M2The grid electrode of the transistor is connected with a first PMOS transistor M1If the second PMOS transistor M is turned on at a low voltage2The grid of the transistor is high level, then the first PMOS transistor M1And a second PMOS transistor M2All will be turned off, the band gap reference main body circuit 1 will enter into a degeneracy point and cannot output the reference voltage VBGThe bandgap reference control circuit 2 can be used to control the second PMOS transistor M2The gate of (1) is at a low level to make the bandgap reference bulk circuit 1 go out of degeneracy.
In one embodiment of the present application, the bandgap reference control circuit 2 may include a third PMOS transistor M4And the fourth PMOS transistor M5A first NMOS transistor M6And an adjusting unit, a third PMOS transistor M4The source electrode of the PMOS transistor is connected with a power supply, and a third PMOS transistor M4Gate connection detecting point VBFourth PMOS transistor M5The source electrode of the PMOS transistor is connected with a third PMOS transistor M4Drain electrode of (1), fourth PMOS tube M5Is connected to a first enable signal ENB if a detection point V is detectedBThe voltage of (3) is high level, the first enable signal is low level, and the third PMOS transistor M4Turn-off, fourth PMOS transistor M5Conducting the first NMOS transistor M6The drain electrode of the transistor is connected with a fourth PMOS tube M5The first NMOS transistor M6Gate connection detecting point VBFirst NMOS transistor M6The source electrode of the NMOS transistor is grounded through the current limiting unit, and the first NMOS transistor M6Conducting the fourth PMOS transistor M5The source of (2) is low level; the input end of the regulating unit is connected with a fourth PMOS tube M5The output end of the regulating unit is connected with a detection point VBWhen the input end of the regulating unit is connected with low level, the output of the regulating unit is low level, thereby enabling the detection point VBAnd is low, so that the bandgap reference main body circuit 1 is separated from the degeneracy point.
In this embodiment, the third PMOS transistor M4And the fourth PMOS transistor M5A first NMOS transistor M6The first enabling signal ENB is used for controlling the detection point VBThe high level of the NMOS transistor is converted into the low level, and the first NMOS transistor M in the branch is also reduced6The drain current plays a role in limiting current and reduces power consumption.
In one embodiment of the present application, the adjusting unit may include a fifth PMOS transistor M8And the first operational amplifier, the fifth PMOS transistor M8The source electrode of the PMOS tube M is connected with a power supply, and a fifth PMOS tube M8The grid electrode of the grid electrode is used as the input end of the regulating unit and is connected with the fourth PMOS tube M5The first input end of the first operational amplifier is connected with the first PMOS tube M1The second input end of the first operational amplifier is connected with a second PMOS tube M2The output end of the first operational amplifier is connected with a detection point VB. Input end of regulating unit, namely fifth PMOS tube M8When the grid of the transistor is at low level, the fifth PMOS transistor M8Conducting, second PMOS transistor M2The voltage of the second input terminal of the first operational amplifier changes, and the first operational amplifier can make the voltages at the two ends of the first input terminal and the second input terminal equal, so that the band-gap reference main body circuit 1 starts to work, and the band-gap reference main body circuit 1 is separated from a degeneracy point.
In an embodiment of the present application, the first operational amplifier may be a second operational amplifier OP in the bandgap reference main circuit 1 having the second operational amplifier OP, and may be a first PMOS transistor M1Is connected to the first input terminal 11 of the second operational amplifier OP, and a second PMOS transistor M2Is connected to a second input terminal 12 of a second operational amplifier OP, the output terminal of the second operational amplifier OP being a detection point VB。
In one embodiment of the present application, the first input terminal 11 may be a negative input terminal of the first operational amplifier, and the second input terminal 12 may be a positive input terminal of the first operational amplifier, when the fifth PMOS transistor M8When the negative phase input terminal is turned on and becomes high level, the output of the first operational amplifier can be made to become low level, so that the detection point V is detectedBIs changed from high level to low level。
In an embodiment of the present application, the bandgap reference control circuit 2 further includes a circuit shutdown unit, an input terminal of the circuit shutdown unit is connected to the power supply, a control terminal of the circuit shutdown unit is connected to the second enable signal EN, and an output terminal of the circuit shutdown unit is connected to the detection point VBThe second enable signal EN controls the circuit to turn off or turn off the unit.
In one embodiment of the present application, the circuit shutdown unit includes a sixth PMOS transistor M9Sixth PMOS transistor M9The source electrode of the PMOS tube M is used as the input end of the circuit turn-off unit and is connected with a power supply, and the sixth PMOS tube M9The grid electrode of the circuit turn-off unit is used as a control end of the circuit turn-off unit and is connected with a second enable signal EN, and a fourth PMOS tube M5The drain electrode of the circuit turn-off unit is used as the output end of the circuit turn-off unit to be connected with the detection point VB。
In an embodiment of the present application, if the second enable signal EN is high, the sixth PMOS transistor M9And the work of the band-gap reference main body circuit 1 is not influenced by the turn-off unit.
In one embodiment of the present application, if the detection point V of the bandgap reference main body circuit 1BThe voltage of (1) is low level, the second enable signal EN is low level, and the sixth PMOS transistor M9When conducting, the detection point VBVoltage is controlled by the sixth PMOS transistor M9The source of the bandgap reference body circuit 1 is pulled high to make the bandgap reference body circuit 1 enter a degenerate state, and the bandgap reference body circuit 1 is turned off.
In an embodiment of the present application, the bandgap reference control circuit 2 further includes a current limiting unit, and the first NMOS transistor M6The source electrode of the power amplifier is grounded through the current limiting unit, and power consumption is reduced.
In one embodiment of the present application, the current limiting unit may include a second NMOS transistor M7Second NMOS transistor M7The drain electrode of the first NMOS tube M is connected with the first NMOS tube6Source electrode of (1), second NMOS tube M7The grid of the first NMOS tube M is connected with the second NMOS tube M7Drain electrode of (1), second NMOS tube M7Is a third PMOS transistor M4And the fourth PMOS transistor M5And a first NMOS transistor M6Partial pressure is the second NMOS tube M7Threshold value ofA voltage.
In other embodiments of the present application, the NMOS transistors may include a plurality of NMOS transistors connected in series, a source of a first NMOS transistor in two adjacent NMOS transistors of the plurality of NMOS transistors connected in series is connected to a drain of a second NMOS transistor, and a drain of a first NMOS transistor of the plurality of NMOS transistors connected in series is connected to a first NMOS transistor M6The source electrode of the last NMOS tube in the NMOS tubes connected in series is grounded, the grid electrode of each NMOS tube in the NMOS tubes connected in series is connected with the drain electrode of the NMOS tube, and the divided voltage is the sum of the threshold voltages of the NMOS tubes.
The band-gap reference circuit comprises a band-gap reference main body circuit 1 and a band-gap reference control circuit 2 connected with the band-gap reference main body circuit 1, wherein the band-gap reference main body circuit 1 comprises a first PMOS (P-channel metal oxide semiconductor) transistor M1And a second PMOS transistor M2The first PMOS transistor M1The source electrode of the PMOS transistor M is connected with a power supply, and a second PMOS transistor M2The source electrode of the PMOS transistor M is connected with a power supply, and a second PMOS transistor M2The grid electrode of the transistor is connected with a first PMOS transistor M1As a detection point V of the bandgap reference main circuit 1BIf the point V is detectedBThe voltage of (D) is high level, then the first PMOS transistor M1And a second PMOS transistor M2All are turned off, the band gap reference control circuit 2 is at a degenerate point, and the band gap reference control circuit 2 comprises a third PMOS tube M4And the fourth PMOS transistor M5A first NMOS transistor M6And an adjusting unit, a third PMOS transistor M4The source electrode of the PMOS transistor is connected with a power supply, and a third PMOS transistor M4Gate connection detecting point VBFourth PMOS transistor M5The source electrode of the PMOS transistor is connected with a third PMOS transistor M4Drain electrode of (1), fourth PMOS tube M5Is connected to a first enable signal ENB if a detection point V is detectedBThe voltage of (3) is high level, the first enable signal is low level, and then the fourth PMOS transistor M5Conducting the first NMOS transistor M6The drain electrode of the transistor is connected with a fourth PMOS tube M5The first NMOS transistor M6Gate connection detecting point VBFirst NMOS transistor M6Conducting the first NMOS transistor M6The source electrode of the NMOS transistor is grounded through the current limiting unit, and the first NMOS transistor M6The drain of the regulating unit is at a low level, and the input end of the regulating unitIs connected with a fourth PMOS tube M5The output end of the regulating unit is connected with a detection point VBThe input end of the regulating unit is connected with low level, and the output of the regulating unit is low level, so that the detection point V is detectedBThe level by the height step-down, make band gap reference control circuit 2 break away from the degeneracy point, the band gap control circuit simple structure of this application only comprises the transistor, and after accomplishing band gap reference circuit's start-up, the turn-off starting circuit can not produce static electric leakage, has consequently saved consumption and chip area to guarantee that reference circuit can break away from the degeneracy point when power is on, realize a low-power consumption and stable work's band gap reference circuit.
While the present application has been described with reference to several exemplary embodiments, it is understood that the terminology used is intended to be in the nature of words of description and illustration, rather than of limitation. As the present application may be embodied in several forms without departing from the spirit or essential characteristics thereof, it should also be understood that the above-described embodiments are not limited by any of the details of the foregoing description, but rather should be construed broadly within its spirit and scope as defined in the appended claims, and therefore all changes and modifications that fall within the meets and bounds of the claims, or equivalences of such meets and bounds are therefore intended to be embraced by the appended claims.
Claims (9)
1. A band-gap reference circuit is characterized in that the band-gap reference circuit comprises a band-gap reference main circuit and a band-gap reference control circuit connected with the band-gap reference main circuit,
the band-gap reference main body circuit comprises:
the source electrode of the first PMOS tube is connected with a power supply;
a source electrode of the second PMOS tube is connected with the power supply, and a grid electrode of the second PMOS tube is connected with a grid electrode of the first PMOS tube and is used as a detection point of the band-gap reference main body circuit;
the bandgap reference control circuit includes:
a source electrode of the third PMOS tube is connected with a power supply, and a grid electrode of the third PMOS tube is connected with the detection point;
a source electrode of the fourth PMOS tube is connected with a drain electrode of the third PMOS tube, a grid electrode of the fourth PMOS tube is connected with a first enabling signal, and if the voltage of the detection point is high level, the first enabling signal is low level;
the drain electrode of the first NMOS tube is connected with the drain electrode of the fourth PMOS tube, the grid electrode of the first NMOS tube is connected with the detection point, and the source electrode of the first NMOS tube is grounded;
and the input end of the adjusting unit is connected with the source electrode of the fourth PMOS tube, the output end of the adjusting unit is connected with the detection point, and when the input end of the adjusting unit is connected with a low level, the output of the adjusting unit is at the low level.
2. The bandgap reference circuit of claim 1,
the adjusting unit includes:
a source electrode of the fifth PMOS tube is connected with the power supply, and a grid electrode of the fifth PMOS tube is used as an input end of the regulating unit and is connected with a source electrode of the fourth PMOS tube;
the first input end of the first operational amplifier is connected with the drain electrode of the first PMOS tube, the second input end of the first operational amplifier is connected with the drain electrode of the second PMOS tube, and the output end of the first operational amplifier is connected with the detection point.
3. The bandgap reference circuit according to claim 1, wherein the bandgap reference control circuit further comprises:
the input end of the circuit turn-off unit is connected with the power supply, the control end of the circuit turn-off unit is connected with a second enabling signal, the output end of the circuit turn-off unit is connected with the detection point, and the second enabling signal controls the circuit turn-off unit to work or turn off.
4. The bandgap reference circuit according to claim 3, wherein the circuit turn-off unit comprises:
and the source electrode of the sixth PMOS tube is used as the input end of the circuit turn-off unit and connected with the power supply, the grid electrode of the sixth PMOS tube is used as the control end of the circuit turn-off unit and connected with the second enabling signal, and the drain electrode of the fourth PMOS tube is used as the output end of the circuit turn-off unit and connected with the detection point.
5. The bandgap reference circuit of claim 4,
if the second enable signal is at a high level, the circuit turn-off unit does not affect the band-gap reference main circuit;
if the second enable signal is at a low level, the circuit shutdown unit changes the voltage at the detection point of the bandgap reference main circuit to a high level, and the bandgap reference main circuit is shut down.
6. The bandgap reference circuit according to claim 1, wherein the bandgap reference control circuit further comprises:
and the source electrode of the first NMOS tube is grounded through the current limiting unit.
7. The bandgap reference circuit according to claim 6, wherein the current limiting unit comprises:
the drain electrode of the second NMOS tube is connected with the source electrode of the first NMOS tube, the grid electrode of the second NMOS tube is connected with the drain electrode of the second NMOS tube, and the source electrode of the second NMOS tube is grounded.
8. The bandgap reference circuit of claim 1, wherein the bandgap reference bulk circuit further comprises:
the emitter of the first triode is connected with the drain of the first PMOS tube, and the base of the first triode is connected with the collector of the first triode and grounded;
and the emitter of the second triode is connected with the drain of the second PMOS tube through a first resistor, and the base of the second triode is connected with the collector of the second triode and grounded.
9. The bandgap reference circuit of claim 1, wherein the bandgap reference bulk circuit further comprises:
a source electrode of the seventh PMOS tube is connected with the power supply, a grid electrode of the seventh PMOS tube is connected with a grid electrode of the first PMOS tube, and a drain electrode of the seventh PMOS tube is used as an output end of the band-gap reference circuit to output reference voltage;
a first end of the second resistor is connected with the drain electrode of the seventh PMOS tube;
and an emitter of the third triode is connected with the second end of the second resistor, and a base of the third triode is connected with a collector of the third triode and grounded.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202022087711.0U CN212276288U (en) | 2020-09-21 | 2020-09-21 | Band gap reference circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202022087711.0U CN212276288U (en) | 2020-09-21 | 2020-09-21 | Band gap reference circuit |
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| CN212276288U true CN212276288U (en) | 2021-01-01 |
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| CN202022087711.0U Active CN212276288U (en) | 2020-09-21 | 2020-09-21 | Band gap reference circuit |
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2020
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