CN212229454U

CN212229454U - Large-bandwidth high-stability frequency source component

Info

Publication number: CN212229454U
Application number: CN202021091555.9U
Authority: CN
Inventors: 李博
Original assignee: Nanjing Zhihang Technology Research Institute Co ltd; Nanjing Yunhang Information Technology Co ltd
Current assignee: Nanjing Anmaisen Electronic Technology Co ltd
Priority date: 2020-06-12
Filing date: 2020-06-12
Publication date: 2020-12-25
Anticipated expiration: 2030-06-12

Abstract

The utility model discloses a high stable frequency source subassembly of big bandwidth, including host computer, central processing module, direct digital frequency synthesis module, clock signal production module, host computer, central processing module, direct digital frequency synthesis module serial port communication connecting plate in proper order, clock signal production module respectively with central processing module, direct digital frequency synthesis module serial port communication connection; the upper computer outputs a control instruction according to the set parameters; the central processing module analyzes a control instruction of the upper computer and configures the clock signal generating module according to the control instruction; the clock signal generating module generates a clock signal according to a control instruction; and the direct digital frequency synthesis module outputs a frequency signal matched with the set parameters.

Description

Large-bandwidth high-stability frequency source component

Technical Field

The utility model belongs to the technical field of wireless communication, concretely relates to frequency source subassembly is stabilized to big bandwidth height.

Background

The signal source, as an electronic instrument for generating a standard signal, has a wide application in the fields of production practice, teaching experiment, and science and technology, and is called the heart of many electronic systems. A local oscillator with excellent performance has an important influence on modulation and demodulation of a communication system, detection accuracy of a radar system, and the like. With the development of science and technology, people have higher and higher requirements on signal sources, and the signal sources designed by the traditional frequency synthesis method have the defects and shortcomings of low frequency precision, low resolution, narrow bandwidth, low frequency stability and the like in the aspects of functions, precision and the like, and cannot meet the actual requirements.

SUMMERY OF THE UTILITY MODEL

The utility model aims to solve the technical problem that to the not enough of above-mentioned prior art, provide a frequency source subassembly is stabilized to big bandwidth height.

In order to realize the technical purpose, the utility model discloses the technical scheme who takes does:

a large bandwidth high stability frequency source assembly, wherein: the system comprises an upper computer, a central processing module, a direct digital frequency synthesis module and a clock signal generation module, wherein the upper computer, the central processing module and the direct digital frequency synthesis module are sequentially connected with a serial port communication connecting plate, and the clock signal generation module is respectively connected with the central processing module and the direct digital frequency synthesis module in a serial port communication way;

the upper computer outputs a control instruction according to the set parameters;

the central processing module analyzes a control instruction of the upper computer and configures the clock signal generating module according to the control instruction;

the clock signal generating module generates a clock signal according to a control instruction;

and the direct digital frequency synthesis module outputs a frequency signal matched with the set parameters.

In order to optimize the technical scheme, the specific measures adopted further comprise:

further, the setting parameters include frequency, phase and amplitude.

Further, the clock signal generating module comprises a high-stability crystal oscillator and a phase-locked loop, the high-stability crystal oscillator generates a low-frequency reference clock signal, the low-frequency reference clock signal is input into the phase-locked loop after resistance-capacitance matching, and the phase-locked loop performs frequency multiplication and frequency division on the low-frequency reference clock signal according to a control instruction and outputs a high-frequency stable clock signal.

Furthermore, the central processing module adopts an STM32F407 single chip microcomputer, and the direct digital frequency synthesis module adopts an AD9910 direct digital frequency synthesizer.

Further, the high-stability crystal oscillator adopts an ECOC-2522 singlechip, and the phase-locked loop adopts an ADF4351 singlechip.

The power supply module is used for converting external input voltage into different grades and respectively providing corresponding working voltage for each module.

The utility model has the advantages that:

the frequency source component solves the problems of narrow bandwidth and low stability of the traditional signal source, and under the drive of a high-stability clock signal, the direct digital frequency synthesis module can generate a low-phase-noise single-frequency signal with large bandwidth, and the direct digital frequency synthesis module drifts to be smaller along with time, and also solves the problems of the volume and the weight of the traditional signal source and reduces the circuit cost.

Drawings

FIG. 1 is a block diagram of the system architecture;

FIG. 2 is a circuit diagram of a low frequency reference clock;

FIG. 3 is a DDS module connection circuit diagram;

FIG. 4 is a circuit diagram of level shifting;

FIG. 5 is a graph of stability testing of frequency source signal output;

FIG. 6 is a power module circuit schematic;

fig. 7 is a spectrum analysis diagram.

Detailed Description

Embodiments of the present invention are described in further detail below with reference to the accompanying drawings.

As shown in fig. 1, the present invention is a large bandwidth high stability frequency source assembly, wherein: the system comprises an upper computer, a central processing module, a direct digital frequency synthesis module and a clock signal generation module, wherein the upper computer, the central processing module and the direct digital frequency synthesis module are sequentially connected with a serial port communication connecting plate, and the clock signal generation module is respectively connected with the central processing module and the direct digital frequency synthesis module in a serial port communication way;

Setting parameters including frequency, phase and amplitude; the clock signal generating module comprises a high-stability crystal oscillator and a phase-locked loop, wherein the high-stability crystal oscillator generates a low-frequency reference clock signal, the low-frequency reference clock signal is input into the phase-locked loop after resistance-capacitance matching, and the phase-locked loop performs frequency multiplication and frequency division on the low-frequency reference clock signal according to a control instruction and outputs a high-frequency stable clock signal; the central processing module adopts an STM32F407 singlechip, the direct digital frequency synthesis module adopts an AD9910 direct digital frequency synthesizer, the high-stability crystal oscillator adopts an ECOC-2522 singlechip, and the phase-locked loop adopts an ADF4351 singlechip; the power supply module is used for converting external input voltage into different grades and respectively providing corresponding working voltage for each module; the power module selects ADM7150ACPZ and TPS7A9201 DSKR.

IN fig. 2, the ECOC-2522 high-stability crystal oscillator is connected to the reference clock input terminal of the ADF4351 pll chip to provide a low-frequency stable signal for the operation of the pll, VCC provides the power supply for the circuit power supply chip, and CLK _ REF _ IN is connected to the input clock pin of the ADF4351 pll chip.

In fig. 3, a low-frequency stable signal input by a crystal oscillator is connected with a clock input pin of an ADF4351, the ADF4351 is locked under the control of an STM32F407 single chip microcomputer to generate a high-frequency differential clock signal for driving an AD9910, and an output signal has the following characteristics:

frequency range: 1MHz-400MHz

Frequency resolution: 0.23Hz

Phase noise: less than or equal to-125 dBc/Hz

Dynamic performance: >80dB narrow-band SFDF

FIG. 4 illustrates peripheral circuitry of AD9910, VDD is connected to power generated by the power module, GND is circuit ground, DDS _ pin is connected to the CPU, REF _ CLK is connected to the ADF43551 PLL chip, SYNC _ pin is connected to an external socket, and an interface is reserved for time synchronization between multiple boards.

Fig. 5 shows that the central processing module selects an STM32F407 single chip microcomputer, communicates with the upper computer through a serial port, analyzes a command issued by the upper computer, and then configures an ADF4351 phase-locked loop chip and an AD9910 direct digital frequency synthesizer, and a frequency source is output after the configuration is completed.

Fig. 6 illustrates a power module of the circuit, which provides the voltage required by the whole system, the external inputs +5V to the system, and the +5V is converted into +3.3V and +1.8V required by the system by the power module, wherein the power chip is selected: the +5V to +3.3V adopts ADM7150ACPZ-3.3 and TPS7A9201DSKR, and the +5V to +1.8V adopts ADM7150ACPZ-1.8 and TPS7A9201 DSKR;

the voltage is respectively supplied to an ADF4351 phase-locked loop chip and is +3.3V, an AD9910 direct digital frequency synthesizer is +3.3V, +1.8V, a high-stability crystal oscillator is +3.3V, and the voltage of an STM32F407 singlechip control chip is +3.3V, wherein ADM7150ACPZ-3.3 and TPS7A9201DSKR are adopted when +5V is converted into +3.3V, and ADM7150ACPZ-1.8 and TPS7A9201DSKR are adopted when +5V is converted into + 1.8V.

Fig. 7 was tested using the maximum hold function of the spectrum analyzer for up to 25 minutes, with no significant frequency shift observed on the screen. The design gives full play to the excellent performance of each chip, obtains a low-phase noise single-frequency signal in a large bandwidth range, has high stability and small drift along with time, and has high integration level and more flexible installation and control.

The utility model discloses design of big bandwidth high stable frequency source and realization pass through in the actual experimentation in the test, have realized the production of big bandwidth high stable frequency signal to there are following characteristics: the generated frequency signal has high stability, large adjustable bandwidth range and simple and convenient operation. The hardware circuit is simple, the volume is small, and exploration and basis are provided for future system integration. The main functions are simple in programming and easy to modify, so that the system has great universality and flexibility. The expected functions are completely realized, and the realization is simple.

Above only the utility model discloses an it is preferred embodiment, the utility model discloses a scope of protection not only limits in above-mentioned embodiment, and the all belongs to the utility model discloses a technical scheme under the thinking all belongs to the utility model discloses a scope of protection. It should be noted that, for those skilled in the art, a plurality of modifications and decorations without departing from the principle of the present invention should be considered as the protection scope of the present invention.

Claims

1. A large bandwidth high stability frequency source assembly, characterized by: the system comprises an upper computer, a central processing module, a direct digital frequency synthesis module and a clock signal generation module, wherein the upper computer, the central processing module and the direct digital frequency synthesis module are sequentially connected with a serial port communication connecting plate, and the clock signal generation module is respectively connected with the central processing module and the direct digital frequency synthesis module in a serial port communication way;

the clock signal generating module generates a high-frequency clock signal according to the control instruction, and the high-frequency clock signal is used as a beat clock of the direct digital frequency synthesis module;

2. The large-bandwidth high-stability frequency source assembly according to claim 1, wherein: the setting parameters comprise frequency, phase and amplitude.

3. The large-bandwidth high-stability frequency source assembly according to claim 1, wherein: the clock signal generating module comprises a high-stability crystal oscillator and a phase-locked loop, the high-stability crystal oscillator generates a low-frequency reference clock signal, the low-frequency reference clock signal is input into the phase-locked loop after resistance-capacitance matching, and the phase-locked loop performs frequency multiplication and frequency division on the low-frequency reference clock signal according to a control instruction and outputs a high-frequency stable clock signal.

4. The large-bandwidth high-stability frequency source assembly according to claim 3, wherein: the high-stability crystal oscillator adopts an ECOC-2522 singlechip, and the phase-locked loop adopts an ADF4351 singlechip.

5. The large-bandwidth high-stability frequency source assembly according to claim 1, wherein: the central processing module adopts an STM32F407 single chip microcomputer, and the direct digital frequency synthesis module adopts an AD9910 direct digital frequency synthesizer.

6. The large-bandwidth high-stability frequency source assembly according to claim 1, further comprising a power supply module, wherein the power supply module drops an external input voltage to different levels to provide corresponding operating voltages to the modules respectively.