CN212209488U - Pixel structure, display panel and display device - Google Patents
Pixel structure, display panel and display device Download PDFInfo
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- CN212209488U CN212209488U CN202021146129.0U CN202021146129U CN212209488U CN 212209488 U CN212209488 U CN 212209488U CN 202021146129 U CN202021146129 U CN 202021146129U CN 212209488 U CN212209488 U CN 212209488U
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Abstract
The utility model relates to a pixel structure, display panel and display device. A pixel structure comprises a plurality of pixel groups which are arranged in an array form to form an array structure; each pixel group comprises a first chip, a second chip and a third chip with the number ratio of 1: 1; in each pixel group, the first chip, the second chip and the third chip are respectively positioned at three vertexes of a virtual equilateral triangle; for two adjacent pixel groups in the same row, a first chip and a third chip in one pixel group and a second chip in the other pixel group are respectively positioned at three vertexes of a virtual equilateral triangle, and the third chip in one pixel group and the first chip and the second chip in the other pixel group are respectively positioned at three vertexes of the virtual equilateral triangle; the arrangement modes of the first chip, the second chip and the third chip in all the pixel groups in the same column are the same. The pixel structure can improve the resolution of the display panel.
Description
Technical Field
The utility model relates to a display element technical field especially relates to a pixel structure, display panel and display device.
Background
The virtual pixels are formed by controlling the light emitting chips of each color to participate in the imaging of a plurality of adjacent pixels by using a software algorithm, so that the larger resolution is realized by using fewer lamp tubes, and the display resolution can be improved.
However, the dot pitch between the pixel points of a Chip On Board (COB) display panel on the market is generally 2mm, and in order to improve the resolution of the display panel, the pitch between the pixel points needs to be reduced, so that the amount of the pixel points needs to be increased, which leads to an increase in cost.
SUMMERY OF THE UTILITY MODEL
Therefore, it is necessary to provide a display panel and a display device, aiming at the problem that the conventional technology needs to reduce the distance between the pixels, and thus needs to increase the amount of the pixels, resulting in an increase in cost.
A pixel structure comprises a plurality of pixel groups which are arranged in an array form to form an array structure; each pixel group comprises a first chip, a second chip and a third chip in a number ratio of 1: 1, and the first chip, the second chip and the third chip in all the pixel groups in the same row share a cathode;
in each pixel group, the first chip, the second chip and the third chip are respectively positioned at three vertexes of a virtual equilateral triangle;
for two adjacent pixel groups in the same row, the first chip and the third chip in one pixel group and the second chip in the other pixel group are respectively located at three vertexes of a virtual equilateral triangle, and the third chip in one pixel group and the first chip and the second chip in the other pixel group are respectively located at three vertexes of a virtual equilateral triangle;
the first chips, the second chips and the third chips in all the pixel groups in the same column are arranged in the same mode.
According to the pixel structure, by controlling the time-sharing lighting of each chip, a virtual pixel point can be formed after the three chips on the three vertexes of any virtual equilateral triangle are lighted, namely, a virtual pixel technology (namely, a technology of carrying out time-sharing multiplexing on real pixels and reproducing more virtual pixels by utilizing the persistence of vision of human eyes) is utilized, so that the resolution ratio of a display panel and a real pixel display panel applying the pixel structure can be improved on the premise of having the same number of chips, and the manufacturing cost of the display panel is reduced; in addition, the virtual pixel points can reduce the fatigue of the user during watching.
In one embodiment, all the pixel groups in the same column of the array structure are uniformly spaced, and the distance between two adjacent pixel groups in the same row of the array structure is equal to the distance between two adjacent pixel groups in the array structure.
In one embodiment, the first chip, the second chip and the third chip are all one of a red light emitting chip, a blue light emitting chip or a green light emitting chip, and the light emitting colors of the first chip, the second chip and the third chip are different from each other.
In one embodiment, the number of the first chips, the second chips and the third chips in each pixel group is one.
In one embodiment, the first chip, the second chip, and the third chip each include a front-mounted light emitting chip or a flip-chip light emitting chip.
A display panel comprises a circuit board and a pixel structure, wherein the pixel structure comprises a plurality of pixel groups which are arranged in an array manner to form an array structure; each pixel group comprises a first chip, a second chip and a third chip in a number ratio of 1: 1, and the first chip, the second chip and the third chip in all the pixel groups in the same row share a cathode; the first chip, the second chip and the third chip are all positioned on the same surface of the circuit board;
in each pixel group, the first chip, the second chip and the third chip are respectively positioned at three vertexes of a virtual equilateral triangle;
for two adjacent pixel groups in the same row, the first chip and the third chip in one pixel group and the second chip in the other pixel group are respectively located at three vertexes of a virtual equilateral triangle, and the third chip in one pixel group and the first chip and the second chip in the other pixel group are respectively located at three vertexes of a virtual equilateral triangle;
the first chips, the second chips and the third chips in all the pixel groups in the same column are arranged in the same mode.
In one embodiment, the circuit board includes common electrodes, first bonding wire areas, second bonding wire areas and third bonding wire areas, the number of the common electrodes is the same as the number of rows of the array structure and is in one-to-one correspondence with each row of the pixel groups, the number of the first bonding wire areas is the same as that of the first chips and is in one-to-one correspondence with each other, the number of the second bonding wire areas is the same as that of the second chips and is in one-to-one correspondence with each other, and the number of the third bonding wire areas is the same as that of the third chips and is in one-to-one correspondence with each other;
the cathodes of all the first chips, the second chips and the third chips in the pixel groups in the same row are connected with the corresponding common electrodes, the anodes of the first chips are connected with the corresponding first welding line areas, the anodes of the second chips are connected with the corresponding second welding line areas, and the anodes of the third chips are connected with the corresponding third welding line areas.
In one embodiment, all the pixel groups in the same column of the array structure are uniformly spaced, and the distance between two adjacent pixel groups in the same row of the array structure is equal to the distance between two adjacent pixel groups in the array structure.
In one embodiment, the first chip, the second chip and the third chip are all one of a red light emitting chip, a blue light emitting chip or a green light emitting chip, and the light emitting colors of the first chip, the second chip and the third chip are different from each other.
A display device comprising a display panel as claimed in any one of the above.
Drawings
Fig. 1 is a schematic diagram of a pixel structure in an embodiment.
Fig. 2 is a schematic view of a solder structure of pixel groups in the same row in an embodiment.
Description of reference numerals:
110. a pixel group; 111. a first chip; 112. a second chip; 113. a third chip; 121. a first wire bonding area; 122. a second wire bonding area; 123. a third wire bonding area; 124. a common pole.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
It will be understood that when an element is referred to as being "secured to" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present. The terms "vertical," "horizontal," "left," "right," and the like as used herein are for illustrative purposes only and do not represent the only embodiments.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
In the present invention, the terms "first" and "second" do not denote any particular quantity or order, but are merely used to distinguish names.
The dot spacing between the pixel points of the COB display panel in the conventional technology is generally 2mm, and for improving the resolution of the display panel, the spacing between the pixel points needs to be reduced, so that the use amount of the pixel points needs to be increased, and the cost is increased. Therefore, the pixel structure can improve the resolution of the panel under the condition of using less real pixel points without reducing the distance between the pixel points.
The pixel structure comprises a plurality of pixel groups which are arranged in an array mode to form an array structure. Each pixel group comprises a first chip, a second chip and a third chip with the number ratio of 1: 1. The first chip, the second chip and the third chip in all the pixel groups in the same row share a cathode; in each pixel group, the first chip, the second chip and the third chip are respectively positioned at three vertexes of a virtual equilateral triangle; for two adjacent pixel groups in the same row, a first chip and a third chip in one pixel group and a second chip in the other pixel group are respectively positioned at three vertexes of a virtual equilateral triangle, and the third chip in one pixel group and the first chip and the second chip in the other pixel group are respectively positioned at three vertexes of the virtual equilateral triangle; the arrangement modes of the first chip, the second chip and the third chip in all the pixel groups in the same column are the same.
Fig. 1 is a schematic diagram of a pixel structure in an embodiment. As shown in fig. 1, the number of the first chip 111, the second chip 112 and the third chip 113 in each pixel group 110 is one. In other embodiments, the number of the first chip 111, the second chip 112, and the third chip 113 in each pixel group 110 may also be two, three, etc., as long as the number ratio of the first chip 111, the second chip 112, and the third chip 113 is ensured to be 1: 1. The first chip 111, the second chip 112 and the third chip 113 may be one of a red light emitting chip, a blue light emitting chip and a green light emitting chip, respectively, and the light emitting colors of the first chip 111, the second chip 112 and the third chip 113 are different.
Illustratively, the first chip 111 is a green light emitting chip, the second chip 112 is a red light emitting chip, and the third chip 113 is a blue light emitting chip. Of course, the first chip 111 may be a green light emitting chip, the second chip 112 may be a blue light emitting chip, and the third chip 113 may be a red light emitting chip.
Illustratively, the first chip 111 is a red light emitting chip, the second chip 112 is a green light emitting chip, and the third chip 113 is a blue light emitting chip. Of course, the first chip 111 may be a red light emitting chip, the second chip 112 may be a blue light emitting chip, and the third chip 113 may be a green light emitting chip.
Illustratively, the first chip 111 is a blue light emitting chip, the second chip 112 is a red light emitting chip, and the third chip 113 is a green light emitting chip. Of course, the first chip 111 may be a blue light emitting chip, the second chip 112 may be a green light emitting chip, and the third chip 113 may be a red light emitting chip.
Of course, the first chip 111, the second chip 112, and the third chip 113 may be light emitting chips of other colors.
For the pixel group 110 in the same row, the first chip 111, the second chip 112, and the third chip 113 all share a cathode, that is, the cathodes of the first chip 111, the second chip 112, and the third chip 113 in the pixel group 110 in the same row are all connected together. In each pixel group 110, the first chip 111, the second chip 112, and the third chip 113 are respectively located at three vertices of the virtual equilateral triangle, and the light emitting color of the chip located at each vertex of the virtual equilateral triangle can be adjusted according to actual requirements.
Still taking fig. 1 as an example, for two adjacent pixel groups 110 in the same row, the first chip 111, the second chip 112, and the third chip 113 in the left pixel group 110a are respectively located at three vertices of a virtual equilateral triangle, the first chip 111 and the third chip 113 in the left pixel group 110a and the second chip 112 in the right pixel group 110b are respectively located at three vertices of a virtual equilateral triangle, the third chip 113 in the left pixel group 110a and the first chip 111 and the second chip 112 in the right pixel group 110b are respectively located at three vertices of a virtual equilateral triangle, and the first chip 111, the second chip 112, and the third chip 113 in the right pixel group 110b are respectively located at three vertices of a virtual equilateral triangle. In the same row, the relationship between the side length of each virtual equilateral triangle and the distance P between adjacent real pixel points in the same row is that the side length of the virtual equilateral triangle is equal to
For the pixel groups 110 in the same column, for example, the first chips 111, the second chips 112, and the third chips 113 in the upper pixel group 110a and the lower pixel group 110c are arranged in the same manner, and the first chips 111, the second chips 112, and the third chips 113 in the upper pixel group 110b and the lower pixel group 110d are arranged in the same manner. The first chip 111, the second chip 112, and the third chip 113 in the upper pixel group 110a are respectively located at three vertices of a virtual equilateral triangle, the first chip 111, the second chip 112, and the third chip 113 in the lower pixel group 110c are respectively located at three vertices of a virtual equilateral triangle, and the second chip 112 and the third chip 113 in the upper pixel group 110a and the first chip 111 in the lower pixel group 110c are respectively located at three vertices of a virtual equilateral triangle. The first chip 111, the second chip 112 and the third chip 113 in the upper pixel group 110b are respectively located at three vertexes of a virtual equilateral triangle, the first chip 111, the second chip 112 and the third chip 113 in the lower pixel group 110d are respectively located at three vertexes of a virtual equilateral triangle, and the first chip 111 in the upper pixel group 110b and the second chip 112 and the third chip 113 in the lower pixel group 110d are respectively located at three vertexes of a virtual equilateral triangle.
The pixel structure enables three chips on three vertexes of any virtual equilateral triangle to form a virtual pixel point after being lightened by controlling the time-sharing lightening of each chip, namely, a virtual pixel technology (namely, a technology of carrying out time-sharing multiplexing on real pixels and reproducing more virtual pixels by utilizing the vision persistence phenomenon of human eyes) is utilized, so that the resolution ratio of a display panel and a real pixel display panel applying the pixel structure can be improved on the premise of having the same number of chips, and the manufacturing cost of the display panel is reduced; in addition, the virtual pixel points can reduce the fatigue of the user during watching.
In addition, when the number of the first chips 111, the second chips 112 and the third chips 113 in each pixel group 110 is one, the display panel using the pixel structure uses one half of less chips compared with the conventional display panel under the same resolution, thereby reducing the use of driving chips and further reducing the cost.
Optionally, when time-division multiplexing of real pixels is performed, the sharpness of the edge of the display image on the display panel may be reduced by using a sub-pixel algorithm.
In one embodiment, all the pixel groups 110 in the same row of the array structure are uniformly spaced, and the distance between two adjacent pixel groups 110 in the same row of the array structure is equal to the distance between two adjacent pixel groups 110 in the array structure. Therefore, the pixel points are distributed more uniformly, and the fatigue of the user during watching is further reduced. In this embodiment, for the pixel groups 110 in the same column, the first chips 111, the second chips 112, and the third chips 113 in each pixel group 110 are all on the same straight line. For the pixel groups 110 in the same column, the center points of any two of the first chip 111, the second chip 112, and the third chip 113 in each pixel group 110 are all on a straight line. For the array structure, the distances between the central points of every two adjacent virtual equilateral triangles are equal, and the central points are arranged orderly.
In an embodiment, the first chip 111, the second chip 112, and the third chip 113 all include a front-mounted light emitting chip or a flip-chip light emitting chip, and the front-mounted light emitting chip or the flip-chip light emitting chip is selected according to actual requirements.
The application also provides a display panel. The display panel may be an OLED (Organic Light-Emitting Diode) display panel, a COB display panel, an LED (Light-Emitting Diode) display panel, or the like.
The display panel comprises a circuit board and a pixel structure, wherein the pixel structure comprises a plurality of pixel groups 110 which are arranged in an array manner to form an array structure; each pixel group 110 comprises a first chip 111, a second chip 112 and a third chip 113 with the number ratio of 1: 1, and the first chip 111, the second chip 112 and the third chip 113 in all the pixel groups 110 in the same row share a cathode; the first chip 111, the second chip 112 and the third chip 113 are all located on the same side of the circuit board (not shown); in each pixel group 110, the first chip 111, the second chip 112 and the third chip 113 are respectively located at three vertexes of a virtual equilateral triangle; for two adjacent pixel groups 110 in the same row, the first chip 111 and the third chip 113 in one pixel group 110 and the second chip 112 in the other pixel group 110 are respectively located at three vertexes of a virtual equilateral triangle, and the third chip 113 in one pixel group 110 and the first chip 111 and the second chip 112 in the other pixel group 110 are respectively located at three vertexes of a virtual equilateral triangle; the first chips 111, the second chips 112 and the third chips 113 in all the pixel groups 110 in the same column are arranged in the same manner.
The display panel can form a virtual pixel point after three chips on three vertexes of any virtual equilateral triangle are lightened by controlling the time-sharing lightening of each chip, namely, a virtual pixel technology (namely, a technology of carrying out time-sharing multiplexing on real pixels and reproducing more virtual pixels by utilizing the vision persistence phenomenon of human eyes) is utilized, so that the resolution ratio of the display panel utilizing the pixel structure and the real pixel display panel can be improved on the premise of having the same number of chips, and the manufacturing cost of the display panel is reduced; in addition, the virtual pixel points can reduce the fatigue of the user during watching.
It should be noted that the pixel structure included in the display panel provided by the present application may be the pixel structure in any one of the embodiments described above.
Fig. 2 is a schematic view of a bonding structure of a pixel group in an embodiment. As shown in fig. 2, the circuit board includes a first bonding pad area 121, a second bonding pad area 122, a third bonding pad area 123 and a common electrode 124. The number of the common electrodes 124 is the same as the number of rows of the array structure and corresponds to each row of the pixel groups 110, and the cathodes of the first chip 111, the second chip 112 and the third chip 113 in each pixel group 110 in the same row are all connected to the corresponding common electrodes 124 through bonding wires (not shown). The number of the first wire bonding areas 121 is the same as that of the first chips 111, each first chip 111 is provided with a corresponding one of the first wire bonding areas 121, and the anode of the first chip 111 is connected to the corresponding one of the first wire bonding areas 121 by a bonding wire. The number of the second wire bonding areas 122 is the same as that of the second chips 112, each second chip 112 is provided with a corresponding one of the second wire bonding areas 122, and the anode of the second chip 112 is connected to the corresponding second wire bonding area 122 through a bonding wire. The number of the third wire bonding areas 123 is the same as that of the third chips 113, each third chip 113 is provided with a corresponding one of the third wire bonding areas 123, and the anodes of the third chips 113 are connected to the corresponding third wire bonding areas 123 by bonding wires. In other embodiments, the solder structures of the pixel groups 110 may take other forms.
The application also provides a display device. The display device includes the display panel as in any one of the above embodiments. For example, the display device may be a display screen, a mobile phone, a tablet, a palm computer, a smart watch, or other digital devices.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only represent some embodiments of the present invention, and the description thereof is specific and detailed, but not to be construed as limiting the scope of the present invention. It should be noted that, for those skilled in the art, without departing from the spirit of the present invention, several variations and modifications can be made, which are within the scope of the present invention. Therefore, the protection scope of the present invention should be subject to the appended claims.
Claims (10)
1. A pixel structure is characterized by comprising a plurality of pixel groups which are arranged in an array manner to form an array structure; each pixel group comprises a first chip, a second chip and a third chip in a number ratio of 1: 1, and the first chip, the second chip and the third chip in all the pixel groups in the same row share a cathode;
in each pixel group, the first chip, the second chip and the third chip are respectively positioned at three vertexes of a virtual equilateral triangle;
for two adjacent pixel groups in the same row, the first chip and the third chip in one pixel group and the second chip in the other pixel group are respectively located at three vertexes of a virtual equilateral triangle, and the third chip in one pixel group and the first chip and the second chip in the other pixel group are respectively located at three vertexes of a virtual equilateral triangle;
the first chips, the second chips and the third chips in all the pixel groups in the same column are arranged in the same mode.
2. The pixel structure according to claim 1, wherein all the pixel groups in the same column of the array structure are uniformly spaced, and a distance between two adjacent pixel groups in the same row of the array structure is equal to a distance between two adjacent pixel groups in the array structure.
3. The pixel structure according to claim 1, wherein the first chip, the second chip, and the third chip are each one of a red light emitting chip, a blue light emitting chip, or a green light emitting chip, and the light emitting colors of the first chip, the second chip, and the third chip are different from each other.
4. The pixel structure according to claim 1, wherein the number of the first chip, the second chip and the third chip in each pixel group is one.
5. The pixel structure of claim 1, wherein the first chip, the second chip, and the third chip each comprise a front-side light emitting chip or a flip-chip light emitting chip.
6. A display panel is characterized by comprising a circuit board and a pixel structure, wherein the pixel structure comprises a plurality of pixel groups which are arranged in an array manner to form an array structure; each pixel group comprises a first chip, a second chip and a third chip in a number ratio of 1: 1, and the first chip, the second chip and the third chip in all the pixel groups in the same row share a cathode; the first chip, the second chip and the third chip are all positioned on the same surface of the circuit board;
in each pixel group, the first chip, the second chip and the third chip are respectively positioned at three vertexes of a virtual equilateral triangle;
for two adjacent pixel groups in the same row, the first chip and the third chip in one pixel group and the second chip in the other pixel group are respectively located at three vertexes of a virtual equilateral triangle, and the third chip in one pixel group and the first chip and the second chip in the other pixel group are respectively located at three vertexes of a virtual equilateral triangle;
the first chips, the second chips and the third chips in all the pixel groups in the same column are arranged in the same mode.
7. The display panel according to claim 6, wherein the circuit board comprises a common electrode, a first bonding wire area, a second bonding wire area and a third bonding wire area, the number of the common electrodes is the same as the number of rows of the array structure and corresponds to the pixel groups in each row one by one, the number of the first bonding wire areas is the same as the number of the first chips one by one, the number of the second bonding wire areas is the same as the number of the second chips one by one, and the number of the third bonding wire areas is the same as the number of the third chips one by one;
the cathodes of all the first chips, the second chips and the third chips in the pixel groups in the same row are connected with the corresponding common electrodes, the anodes of the first chips are connected with the corresponding first welding line areas, the anodes of the second chips are connected with the corresponding second welding line areas, and the anodes of the third chips are connected with the corresponding third welding line areas.
8. The display panel according to claim 6, wherein all the pixel groups in the same column of the array structure are uniformly spaced, and a distance between two adjacent pixel groups in the same row of the array structure is equal to a distance between two adjacent pixel groups in the array structure.
9. The display panel according to claim 6, wherein the first chip, the second chip, and the third chip are each one of a red light emitting chip, a blue light emitting chip, or a green light emitting chip, and wherein the first chip, the second chip, and the third chip have different emission colors.
10. A display device comprising the display panel according to any one of claims 6 to 9.
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| CN114913783A (en) * | 2022-05-27 | 2022-08-16 | 福州大学 | Method for reducing number of micron-sized LED backlight source chips |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN114913783A (en) * | 2022-05-27 | 2022-08-16 | 福州大学 | Method for reducing number of micron-sized LED backlight source chips |
| CN114913783B (en) * | 2022-05-27 | 2023-02-21 | 福州大学 | Method for reducing number of micron-sized LED backlight source chips |
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